Author: matt
Date: 2007-11-14 02:31:30 -0700 (Wed, 14 Nov 2007)
New Revision: 6894
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
Log:
add in uart model
Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
2007-11-14 09:30:39 UTC (rev 6893)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
2007-11-14 09:31:30 UTC (rev 6894)
@@ -131,12 +131,22 @@
assign dsp_clk = clock_ready ? clk_fpga : aux_clk;
assign wb_clk = div_clk;
-
+
+ /* // Div by 4
always @(posedge dsp_clk or negedge dsp_clk)
+ if(div_ctr==7)
+ div_ctr <= 0;
+ else
+ div_ctr <= div_ctr + 1;
+ assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2) |
(div_ctr == 3);
+ */
+
+ // Div by 3
+ always @(posedge dsp_clk or negedge dsp_clk)
if(div_ctr==5)
- div_ctr = 0;
+ div_ctr <= 0;
else
- div_ctr = div_ctr + 1;
+ div_ctr <= div_ctr + 1;
assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
initial
@@ -255,10 +265,16 @@
.sen_rx_dac (sen_rx_dac),
.io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]),
+ .uart_tx_o (uart_tx_o),
+ .uart_rx_i (uart_rx_i),
+ .uart_baud_o (uart_baud_o),
.sim_mode (1'b1)
);
// Experimental printf-like function
+ uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
+
+ /*
reg print_edge_det;
always @(posedge wb_clk)
begin
@@ -266,10 +282,14 @@
if(!print_edge_det & (io_tx[7] == 1'd1))
$write("%c",io_tx[15:8]);
end
+ */
// End the simulation
always @(posedge wb_clk)
if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC2F0))
- $finish;
+ begin
+ $display($time, "Finish called.",);
+ $finish;
+ end
endmodule // u2_sim_top
_______________________________________________
Commit-gnuradio mailing list
[email protected]
http://lists.gnu.org/mailman/listinfo/commit-gnuradio
