Author: matt
Date: 2007-11-14 19:20:10 -0700 (Wed, 14 Nov 2007)
New Revision: 6915
Modified:
gnuradio/branches/developers/matt/u2f/opencores/uart16550/rtl/verilog/uart_regs.v
Log:
this is ugly, but it lets us actually use the fifo...
Modified:
gnuradio/branches/developers/matt/u2f/opencores/uart16550/rtl/verilog/uart_regs.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/uart16550/rtl/verilog/uart_regs.v
2007-11-15 02:09:56 UTC (rev 6914)
+++
gnuradio/branches/developers/matt/u2f/opencores/uart16550/rtl/verilog/uart_regs.v
2007-11-15 02:20:10 UTC (rev 6915)
@@ -599,7 +599,7 @@
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
-assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
+assign lsr5 = (tf_count!=5'b11111); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0));
// transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
@@ -668,7 +668,8 @@
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= #1 1;
- else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
+ else lsr5r <= #1 lsr5;
+ //else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
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