Author: matt
Date: 2007-11-15 15:14:03 -0700 (Thu, 15 Nov 2007)
New Revision: 6936
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
proper bus timings
Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-11-15 22:12:57 UTC (rev 6935)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
2007-11-15 22:14:03 UTC (rev 6936)
@@ -190,24 +190,26 @@
// Wishbone Outputs
// Use the following lines if ram output and mux can be made fast enough
- //always @(posedge wb_clk_i)
- // wb_ack_o <= wb_stb_i;
- //assign wb_dat_o = buf_doa[which_buf];
- // Use this if we can't make the RAM+MUX fast enough
- reg [31:0] wb_dat_o_reg;
- reg stb_d1;
- always @(posedge wb_clk_i)
- begin
- wb_dat_o_reg <= buf_doa[which_buf];
- stb_d1 <= wb_stb_i;
- wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
- end
- assign wb_dat_o = wb_dat_o_reg;
-
assign wb_err_o = 1'b0; // Unused for now
assign wb_rty_o = 1'b0; // Unused for now
+ always @(posedge wb_clk_i)
+ wb_ack_o <= wb_stb_i & ~wb_ack_o;
+ assign wb_dat_o = buf_doa[which_buf];
+
+ // Use this if we can't make the RAM+MUX fast enough
+ // reg [31:0] wb_dat_o_reg;
+ // reg stb_d1;
+
+ // always @(posedge wb_clk_i)
+ // begin
+ // wb_dat_o_reg <= buf_doa[which_buf];
+ // stb_d1 <= wb_stb_i;
+ // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
+ // end
+ //assign wb_dat_o = wb_dat_o_reg;
+
mux8 #(.WIDTH(1))
mux8_wr_ready0(.en(~write_src[0][3]),.sel(write_src[0][2:0]),
.i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
.i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
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