Author: matt
Date: 2007-11-15 22:47:38 -0700 (Thu, 15 Nov 2007)
New Revision: 6961
Modified:
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v
Log:
turn on barrel shifter
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v 2007-11-16
05:40:06 UTC (rev 6960)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v 2007-11-16
05:47:38 UTC (rev 6961)
@@ -31,7 +31,7 @@
`define NEW_AEMB 1
`ifdef NEW_AEMB
- aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(0),.BSF(0))
+ aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(0),.BSF(1))
aeMB_edk32 (.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
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