Author: matt Date: 2007-11-16 15:46:10 -0700 (Fri, 16 Nov 2007) New Revision: 6971
Modified: usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v Log: fixed fifo overflow Modified: usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v =================================================================== --- usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v 2007-11-16 21:32:48 UTC (rev 6970) +++ usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v 2007-11-16 22:46:10 UTC (rev 6971) @@ -599,7 +599,11 @@ assign lsr2 = rf_data_out[1]; // parity error bit assign lsr3 = rf_data_out[0]; // framing error bit assign lsr4 = rf_data_out[2]; // break error in the character -assign lsr5 = (tf_count!=5'b11111); // transmitter fifo is empty + +// Why is this here? Empty should be signalled in the fifo itself, + // to properly account for fifo length parameters + +assign lsr5 = (tf_count!=5'b01111); // transmitter fifo is empty assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty assign lsr7 = rf_error_bit | rf_overrun; _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
