Author: matt
Date: 2007-11-16 18:07:30 -0700 (Fri, 16 Nov 2007)
New Revision: 6973
Modified:
usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
Log:
in the interest of Eric's sanity...
Modified: usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
===================================================================
--- usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
2007-11-17 00:21:37 UTC (rev 6972)
+++ usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
2007-11-17 01:07:30 UTC (rev 6973)
@@ -603,8 +603,8 @@
// Why is this here? Empty should be signalled in the fifo itself,
// to properly account for fifo length parameters
-assign lsr5 = (tf_count!=5'b01111); // transmitter fifo is empty
-assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0));
// transmitter empty
+assign lsr5 = (tf_count!=5'b01111); // transmitter fifo is not full
+assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0));
// transmitter completely empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
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