Author: matt
Date: 2007-11-17 15:33:41 -0700 (Sat, 17 Nov 2007)
New Revision: 6977
Modified:
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v
Log:
no barrel shifter by default, allow upper level to choose it.
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v 2007-11-17
22:00:32 UTC (rev 6976)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v 2007-11-17
22:33:41 UTC (rev 6977)
@@ -6,7 +6,8 @@
// Make it big-endian like the standard MicroBlaze
module aeMB_core_BE
- #(parameter ISIZ=32, parameter DSIZ=32)
+ #(parameter ISIZ=32, parameter DSIZ=32,
+ parameter MUL=0, parameter BSF=0)
(input sys_clk_i,
input sys_rst_i,
@@ -31,7 +32,7 @@
`define NEW_AEMB 1
`ifdef NEW_AEMB
- aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(0),.BSF(1))
+ aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(0),.BSF(0))
aeMB_edk32 (.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
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