Author: matt
Date: 2007-11-17 16:49:00 -0700 (Sat, 17 Nov 2007)
New Revision: 6979
Modified:
usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
Log:
change where the uart connects
Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v 2007-11-17 23:14:34 UTC (rev
6978)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v 2007-11-17 23:49:00 UTC (rev
6979)
@@ -320,10 +320,11 @@
.sen_rx_dac (sen_rx_dac),
.io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]),
- .uart_tx_o (uart_tx_o),
- .uart_rx_i (uart_rx_i),
- .uart_baud_o (uart_baud_o),
- .sim_mode (1'b0)
+ .uart_tx_o (),
+ .uart_rx_i (),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
);
endmodule // u2_fpga_top
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