Author: matt
Date: 2007-11-17 18:40:44 -0700 (Sat, 17 Nov 2007)
New Revision: 6982
Modified:
usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
changed debug
Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v 2007-11-18 00:55:45 UTC (rev
6981)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v 2007-11-18 01:40:44 UTC (rev
6982)
@@ -539,10 +539,10 @@
//
/////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
-
+
wire [31:0] debug_cpld =
{{ram_loader_we,ram_loader_done,clock_ready,ram_loader_ack,ram_loader_stb,ram_loader_rst,wb_rst,dsp_rst},
- {ram_loader_done ? {2'b00, iwb_adr[13:0]} :
{2'b00,ram_loader_adr[13:0]}},
-
{proc_int,timer_int,cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached}
};
+ {ram_loader_done ? {2'b00, iwb_adr[13:0]} :
{2'b00,ram_loader_adr[13:0]}},
+
{proc_int,timer_int,cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached}
};
wire [31:0] debug_new = {{ram_loader_done ? {2'b00, iwb_adr[13:0]} :
{2'b00, ram_loader_adr[13:0]}},
{3'b0,ram_loader_done,clock_ready, wb_rst,
proc_int,timer_int},
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