Author: matt
Date: 2007-11-18 00:31:20 -0700 (Sun, 18 Nov 2007)
New Revision: 6985
Modified:
usrp2/trunk/fpga/sdr_lib/rx_control.v
Log:
use double cascaded fifo to make routing easier for ISE, which sucks
Modified: usrp2/trunk/fpga/sdr_lib/rx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_control.v 2007-11-18 07:28:54 UTC (rev
6984)
+++ usrp2/trunk/fpga/sdr_lib/rx_control.v 2007-11-18 07:31:20 UTC (rev
6985)
@@ -82,7 +82,7 @@
wire [33:0] fifo_line;
// Internal FIFO, size 9 is 2K, size 10 is 4K
- longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
+ cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
(.clk(clk),.rst(rst),
.datain(fifo_line), .write(write), .full(full),
.dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty)
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