Author: matt
Date: 2007-11-18 00:32:42 -0700 (Sun, 18 Nov 2007)
New Revision: 6987
Modified:
usrp2/trunk/fpga/control_lib/serdes_rx.v
Log:
fixed some used-before-declared signals and switched to a cascaded fifo because
ISE sucks
Modified: usrp2/trunk/fpga/control_lib/serdes_rx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/serdes_rx.v 2007-11-18 07:31:58 UTC (rev
6986)
+++ usrp2/trunk/fpga/control_lib/serdes_rx.v 2007-11-18 07:32:42 UTC (rev
6987)
@@ -62,10 +62,11 @@
reg [31:0] line_i;
reg sop_i, eop_i, error_i;
- wire full;
+ wire error_o, sop_o, eop_o, write, read, empty, full;
reg [15:0] halfline;
reg data_valid, phase;
reg [8:0] holder;
+ wire [31:0] line_o;
reg [2:0] state;
@@ -233,9 +234,8 @@
else write_d <= write_pre;
// Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
- wire write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
- wire [31:0] line_o;
- longfifo #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
+ assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
+ cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
(.clk(clk),.rst(rst),
.datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
.dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty) );
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