Author: matt
Date: 2007-11-20 11:44:57 -0700 (Tue, 20 Nov 2007)
New Revision: 7007
Modified:
usrp2/trunk/fpga/sdr_lib/rx_control.v
Log:
fix typos
Modified: usrp2/trunk/fpga/sdr_lib/rx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_control.v 2007-11-20 09:09:57 UTC (rev
7006)
+++ usrp2/trunk/fpga/sdr_lib/rx_control.v 2007-11-20 18:44:57 UTC (rev
7007)
@@ -24,8 +24,8 @@
input strobe
);
- wire [31:0] new_time, new_command, clear_overrun;
- wire sc_pre1, store_command;
+ wire [31:0] new_time, new_command;
+ wire sc_pre1, store_command, clear_overrun;
setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(new_time),.changed(sc_pre1));
@@ -151,7 +151,7 @@
end // else: !if(full)
IBS_OVERRUN :
if(clear_overrun)
- IBS_STATE <= IBS_IDLE;
+ ibs_state <= IBS_IDLE;
endcase // case(ibs_state)
assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {1'b1,1'b0,master_time} :
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