Author: matt Date: 2007-11-26 00:00:56 -0700 (Mon, 26 Nov 2007) New Revision: 7022
Removed: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_aslu.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_control.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_decode.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_fetch.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_regfile.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_scon.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ucore.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_wbbus.v usrp2/trunk/fpga/opencores/aemb/sim/verilog/testbench.v usrp2/trunk/fpga/opencores/aemb/sim/verilog/utestbench.v Modified: usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c usrp2/trunk/fpga/opencores/aemb/sw/gccrom Log: keep up with shawn's latest, remove deprecated version, switch interrupts to level sensitive Modified: usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries =================================================================== --- usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/doc/CVS/Entries 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,2 +1,2 @@ -/aeMB_datasheet.pdf/1.3/Wed Nov 14 17:40:27 2007/-kb/ +/aeMB_datasheet.pdf/1.3/Sat Nov 24 05:11:12 2007/-kb/ D Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries =================================================================== --- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,16 +1,8 @@ -/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007// -/aeMB_wbbus.v/1.1/Tue May 8 20:32:13 2007// -/aeMB_aslu.v/1.11/Sat Nov 3 19:53:43 2007// -/aeMB_control.v/1.8/Sat Nov 3 19:53:44 2007// -/aeMB_core.v/1.8/Sat Nov 3 19:53:44 2007// -/aeMB_decode.v/1.11/Sat Nov 3 19:53:44 2007// -/aeMB_fetch.v/1.7/Sat Nov 3 19:53:44 2007// -/aeMB_regfile.v/1.19/Sat Nov 3 19:53:44 2007// -/aeMB_regf.v/1.3/Sun Nov 11 19:45:41 2007// -/aeMB_bpcu.v/1.4/Wed Nov 14 23:37:06 2007// -/aeMB_ctrl.v/1.8/Wed Nov 14 23:37:06 2007// -/aeMB_edk32.v/1.9/Wed Nov 14 23:37:06 2007// -/aeMB_scon.v/1.6/Wed Nov 14 23:37:06 2007// -/aeMB_xecu.v/1.7/Wed Nov 14 23:37:06 2007// -/aeMB_ibuf.v/1.6/Wed Nov 14 23:38:26 2007// +/aeMB_bpcu.v/1.4/Sat Nov 24 05:11:03 2007// +/aeMB_core.v/1.9/Mon Nov 26 06:53:03 2007// +/aeMB_edk32.v/1.10/Mon Nov 26 06:53:03 2007// +/aeMB_ibuf.v/1.7/Mon Nov 26 06:53:03 2007// +/aeMB_regf.v/1.3/Sat Nov 24 05:11:03 2007// +/aeMB_xecu.v/1.8/Mon Nov 26 06:53:03 2007// +/aeMB_ctrl.v/1.9/Mon Nov 26 06:56:30 2007// D Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_aslu.v Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_control.v Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core.v =================================================================== --- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core.v 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_core.v 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,256 +1,137 @@ -/* - * $Id: aeMB_core.v,v 1.8 2007/10/22 19:12:59 sybreon Exp $ - * - * AEMB 32-bit Microblaze Compatible Core - * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <[EMAIL PROTECTED]> - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public License - * as published by the Free Software Foundation; either version 2.1 of - * the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - * - * DESCRIPTION - * Microblaze compatible, WISHBONE compliant hardware core. This core is - * capable of executing software compile for EDK 2.1 using GCC. It has the - * capability of handling interrupts as well as exceptions. - * - * HISTORY - * $Log: aeMB_core.v,v $ - * Revision 1.8 2007/10/22 19:12:59 sybreon - * Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. - * - * Revision 1.7 2007/05/30 18:44:30 sybreon - * Added interrupt support. - * - * Revision 1.6 2007/05/17 09:08:21 sybreon - * Removed asynchronous reset signal. - * - * Revision 1.5 2007/04/27 00:23:55 sybreon - * Added code documentation. - * Improved size & speed of rtl/verilog/aeMB_aslu.v - * - * Revision 1.4 2007/04/25 22:15:04 sybreon - * Added support for 8-bit and 16-bit data types. - * - * Revision 1.3 2007/04/11 04:30:43 sybreon - * Added pipeline stalling from incomplete bus cycles. - * Separated sync and async portions of code. - * - * Revision 1.2 2007/04/04 06:13:23 sybreon - * Removed unused signals - * - * Revision 1.1 2007/03/09 17:52:17 sybreon - * initial import - * - */ +// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $ +// +// AEMB 32'bit RISC MICROPROCESSOR CORE +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <[EMAIL PROTECTED]> +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see <http://www.gnu.org/licenses/>. +// +// HISTORY +// $Log: aeMB_core.v,v $ +// Revision 1.9 2007/11/23 14:06:41 sybreon +// Old version deprecated. +// +// Revision 1.8 2007/10/22 19:12:59 sybreon +// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. +// +// Revision 1.7 2007/05/30 18:44:30 sybreon +// Added interrupt support. +// +// Revision 1.6 2007/05/17 09:08:21 sybreon +// Removed asynchronous reset signal. +// +// Revision 1.5 2007/04/27 00:23:55 sybreon +// Added code documentation. +// Improved size & speed of rtl/verilog/aeMB_aslu.v +// +// Revision 1.4 2007/04/25 22:15:04 sybreon +// Added support for 8-bit and 16-bit data types. +// +// Revision 1.3 2007/04/11 04:30:43 sybreon +// Added pipeline stalling from incomplete bus cycles. +// Separated sync and async portions of code. +// +// Revision 1.2 2007/04/04 06:13:23 sybreon +// Removed unused signals +// +// Revision 1.1 2007/03/09 17:52:17 sybreon +// initial import +// + module aeMB_core (/*AUTOARG*/ // Outputs - iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, - dwb_adr_o, + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, // Inputs - sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i, - dwb_ack_i + sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, + fsl_ack_i, dwb_dat_i, dwb_ack_i ); // Instruction WB address space parameter ISIZ = 32; // Data WB address space - parameter DSIZ = 32; + parameter DSIZ = 32; + // Multiplier + parameter MUL = 1; + // Barrel Shifter + parameter BSF = 1; /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) - output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v - output [31:0] dwb_dat_o; // From regfile of aeMB_regfile.v - output [3:0] dwb_sel_o; // From aslu of aeMB_aslu.v - output dwb_stb_o; // From decode of aeMB_decode.v - output dwb_we_o; // From decode of aeMB_decode.v - output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v - output iwb_stb_o; // From fetch of aeMB_fetch.v + output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v + output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v + output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v + output dwb_stb_o; // From edk32 of aeMB_edk32.v + output dwb_wre_o; // From edk32 of aeMB_edk32.v + output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v + output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v + output fsl_stb_o; // From edk32 of aeMB_edk32.v + output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v + output fsl_wre_o; // From edk32 of aeMB_edk32.v + output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v + output iwb_stb_o; // From edk32 of aeMB_edk32.v // End of automatics /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) - input dwb_ack_i; // To control of aeMB_control.v - input [31:0] dwb_dat_i; // To regfile of aeMB_regfile.v - input iwb_ack_i; // To control of aeMB_control.v - input [31:0] iwb_dat_i; // To fetch of aeMB_fetch.v, ... - input sys_clk_i; // To control of aeMB_control.v - input sys_int_i; // To control of aeMB_control.v - input sys_rst_i; // To control of aeMB_control.v + input dwb_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v + input fsl_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v + input iwb_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v + input sys_clk_i; // To edk32 of aeMB_edk32.v + input sys_int_i; // To edk32 of aeMB_edk32.v + input sys_rst_i; // To edk32 of aeMB_edk32.v // End of automatics /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire drun; // From control of aeMB_control.v - wire frun; // From control of aeMB_control.v - wire nclk; // From control of aeMB_control.v - wire prst; // From control of aeMB_control.v - wire prun; // From control of aeMB_control.v - wire [1:0] rATOM; // From decode of aeMB_decode.v - wire rBRA; // From decode of aeMB_decode.v - wire rDLY; // From decode of aeMB_decode.v - wire [3:0] rDWBSEL; // From aslu of aeMB_aslu.v - wire rDWBSTB; // From decode of aeMB_decode.v - wire rDWBWE; // From decode of aeMB_decode.v - wire [2:0] rFSM; // From control of aeMB_control.v - wire [15:0] rIMM; // From decode of aeMB_decode.v - wire rIWBSTB; // From fetch of aeMB_fetch.v - wire rLNK; // From decode of aeMB_decode.v - wire rMSR_IE; // From aslu of aeMB_aslu.v - wire [1:0] rMXALU; // From decode of aeMB_decode.v - wire [1:0] rMXLDST; // From decode of aeMB_decode.v - wire [1:0] rMXSRC; // From decode of aeMB_decode.v - wire [1:0] rMXTGT; // From decode of aeMB_decode.v - wire [5:0] rOPC; // From decode of aeMB_decode.v - wire [31:0] rPC; // From fetch of aeMB_fetch.v - wire [4:0] rRA; // From decode of aeMB_decode.v - wire [4:0] rRB; // From decode of aeMB_decode.v - wire [4:0] rRD; // From decode of aeMB_decode.v - wire [31:0] rREGA; // From regfile of aeMB_regfile.v - wire [31:0] rREGB; // From regfile of aeMB_regfile.v - wire [31:0] rRESULT; // From aslu of aeMB_aslu.v - wire rRWE; // From decode of aeMB_decode.v - wire [31:0] rSIMM; // From decode of aeMB_decode.v - wire [31:0] sDWBDAT; // From regfile of aeMB_regfile.v - // End of automatics // INSTANTIATIONS ///////////////////////////////////////////////////////////////// - - aeMB_regfile #(DSIZ) - regfile (/*AUTOINST*/ - // Outputs - .dwb_dat_o (dwb_dat_o[31:0]), - .rREGA (rREGA[31:0]), - .rREGB (rREGB[31:0]), - .sDWBDAT (sDWBDAT[31:0]), - // Inputs - .dwb_dat_i (dwb_dat_i[31:0]), - .rDWBSTB (rDWBSTB), - .rDWBWE (rDWBWE), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rRD (rRD[4:0]), - .rRESULT (rRESULT[31:0]), - .rFSM (rFSM[2:0]), - .rPC (rPC[31:0]), - .rOPC (rOPC[5:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rLNK (rLNK), - .rRWE (rRWE), - .nclk (nclk), - .prst (prst), - .drun (drun), - .prun (prun)); - aeMB_fetch #(ISIZ) - fetch (/*AUTOINST*/ - // Outputs - .iwb_adr_o (iwb_adr_o[ISIZ-1:0]), - .iwb_stb_o (iwb_stb_o), - .rPC (rPC[31:0]), - .rIWBSTB (rIWBSTB), - // Inputs - .iwb_dat_i (iwb_dat_i[31:0]), - .nclk (nclk), - .prst (prst), - .prun (prun), - .rFSM (rFSM[2:0]), - .rBRA (rBRA), - .rRESULT (rRESULT[31:0])); - - aeMB_control - control (/*AUTOINST*/ - // Outputs - .rFSM (rFSM[2:0]), - .nclk (nclk), - .prst (prst), - .prun (prun), - .frun (frun), - .drun (drun), - // Inputs - .sys_rst_i (sys_rst_i), - .sys_clk_i (sys_clk_i), - .sys_int_i (sys_int_i), - .rIWBSTB (rIWBSTB), - .iwb_ack_i (iwb_ack_i), - .rDWBSTB (rDWBSTB), - .dwb_ack_i (dwb_ack_i), - .rBRA (rBRA), - .rDLY (rDLY), - .rMSR_IE (rMSR_IE), - .rATOM (rATOM[1:0])); - - aeMB_aslu #(DSIZ) - aslu (/*AUTOINST*/ - // Outputs - .dwb_adr_o (dwb_adr_o[DSIZ-1:0]), - .dwb_sel_o (dwb_sel_o[3:0]), - .rRESULT (rRESULT[31:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rMSR_IE (rMSR_IE), - // Inputs - .sDWBDAT (sDWBDAT[31:0]), - .rBRA (rBRA), - .rDLY (rDLY), - .rREGA (rREGA[31:0]), - .rREGB (rREGB[31:0]), - .rSIMM (rSIMM[31:0]), - .rMXSRC (rMXSRC[1:0]), - .rMXTGT (rMXTGT[1:0]), - .rMXALU (rMXALU[1:0]), - .rOPC (rOPC[5:0]), - .rPC (rPC[31:0]), - .rIMM (rIMM[15:0]), - .rRD (rRD[4:0]), - .rRA (rRA[4:0]), - .rMXLDST (rMXLDST[1:0]), - .rFSM (rFSM[2:0]), - .nclk (nclk), - .prst (prst), - .drun (drun), - .prun (prun)); + /* + aeMB_edk32 AUTO_TEMPLATE ( + .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), + .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), + ); + */ - aeMB_decode - decode (/*AUTOINST*/ - // Outputs - .rSIMM (rSIMM[31:0]), - .rMXALU (rMXALU[1:0]), - .rMXSRC (rMXSRC[1:0]), - .rMXTGT (rMXTGT[1:0]), - .rRA (rRA[4:0]), - .rRB (rRB[4:0]), - .rRD (rRD[4:0]), - .rOPC (rOPC[5:0]), - .rIMM (rIMM[15:0]), - .rDWBSTB (rDWBSTB), - .rDWBWE (rDWBWE), - .rDLY (rDLY), - .rLNK (rLNK), - .rBRA (rBRA), - .rRWE (rRWE), - .rMXLDST (rMXLDST[1:0]), - .rATOM (rATOM[1:0]), - .dwb_stb_o (dwb_stb_o), - .dwb_we_o (dwb_we_o), - // Inputs - .sDWBDAT (sDWBDAT[31:0]), - .rDWBSEL (rDWBSEL[3:0]), - .rREGA (rREGA[31:0]), - .rRESULT (rRESULT[31:0]), - .rFSM (rFSM[2:0]), - .iwb_dat_i (iwb_dat_i[31:0]), - .nclk (nclk), - .prst (prst), - .drun (drun), - .frun (frun), - .prun (prun)); + aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF) + edk32 (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_dat_o (fsl_dat_o[31:0]), + .fsl_stb_o (fsl_stb_o), + .fsl_tag_o (fsl_tag_o[1:0]), + .fsl_wre_o (fsl_wre_o), + .iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated + .iwb_stb_o (iwb_stb_o), + // Inputs + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_ack_i (fsl_ack_i), + .fsl_dat_i (fsl_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_int_i (sys_int_i), + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i)); + endmodule // aeMB_core Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v =================================================================== --- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,4 +1,4 @@ -// $Id: aeMB_ctrl.v,v 1.8 2007/11/14 23:19:24 sybreon Exp $ +// $Id: aeMB_ctrl.v,v 1.9 2007/11/15 09:26:43 sybreon Exp $ // // AEMB CONTROL UNIT // @@ -20,6 +20,9 @@ // License along with AEMB. If not, see <http://www.gnu.org/licenses/>. // // $Log: aeMB_ctrl.v,v $ +// Revision 1.9 2007/11/15 09:26:43 sybreon +// Fixed minor typo causing synthesis failure. +// // Revision 1.8 2007/11/14 23:19:24 sybreon // Fixed minor typo. // @@ -286,9 +289,9 @@ // --- DATA WISHBONE ---------------------------------- + wire fDACK = !(dwb_stb_o ^ dwb_ack_i); + reg rDWBSTB, xDWBSTB; - wire fDACK = !(rDWBSTB ^ dwb_ack_i); - reg rDWBWRE, xDWBWRE; assign dwb_stb_o = rDWBSTB; @@ -323,9 +326,9 @@ // --- FSL WISHBONE ----------------------------------- + wire fFACK = !(fsl_stb_o ^ fsl_ack_i); + reg rFSLSTB, xFSLSTB; - wire fFACK = !(rFSLSTB ^ fsl_ack_i); - reg rFSLWRE, xFSLWRE; assign fsl_stb_o = rFSLSTB; Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_decode.v Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v =================================================================== --- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,4 +1,4 @@ -// $Id: aeMB_edk32.v,v 1.9 2007/11/14 23:19:24 sybreon Exp $ +// $Id: aeMB_edk32.v,v 1.10 2007/11/16 21:52:03 sybreon Exp $ // // AEMB EDK 3.2 Compatible Core // @@ -20,6 +20,9 @@ // License along with AEMB. If not, see <http://www.gnu.org/licenses/>. // // $Log: aeMB_edk32.v,v $ +// Revision 1.10 2007/11/16 21:52:03 sybreon +// Added fsl_tag_o to FSL bus (tag either address or data). +// // Revision 1.9 2007/11/14 23:19:24 sybreon // Fixed minor typo. // @@ -54,8 +57,8 @@ module aeMB_edk32 (/*AUTOARG*/ // Outputs - iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o, - dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, // Inputs sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i, dwb_ack_i, sys_clk_i, sys_rst_i @@ -75,9 +78,10 @@ output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v output dwb_stb_o; // From ctrl of aeMB_ctrl.v output dwb_wre_o; // From ctrl of aeMB_ctrl.v - output [14:2] fsl_adr_o; // From xecu of aeMB_xecu.v + output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v output [31:0] fsl_dat_o; // From regf of aeMB_regf.v output fsl_stb_o; // From ctrl of aeMB_ctrl.v + output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v output fsl_wre_o; // From ctrl of aeMB_ctrl.v output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v output iwb_stb_o; // From ibuf of aeMB_ibuf.v @@ -234,7 +238,8 @@ // Outputs .dwb_adr_o (dwb_adr_o[DW-1:2]), .dwb_sel_o (dwb_sel_o[3:0]), - .fsl_adr_o (fsl_adr_o[14:2]), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_tag_o (fsl_tag_o[1:0]), .rRESULT (rRESULT[31:0]), .rDWBSEL (rDWBSEL[3:0]), .rMSR_IE (rMSR_IE), Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_fetch.v Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v =================================================================== --- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,4 +1,4 @@ -// $Id: aeMB_ibuf.v,v 1.6 2007/11/14 23:39:51 sybreon Exp $ +// $Id: aeMB_ibuf.v,v 1.7 2007/11/22 15:11:15 sybreon Exp $ // // AEMB INSTRUCTION BUFFER // @@ -20,6 +20,9 @@ // License along with AEMB. If not, see <http://www.gnu.org/licenses/>. // // $Log: aeMB_ibuf.v,v $ +// Revision 1.7 2007/11/22 15:11:15 sybreon +// Change interrupt to positive level triggered interrupts. +// // Revision 1.6 2007/11/14 23:39:51 sybreon // Fixed interrupt signal synchronisation. // @@ -87,24 +90,22 @@ reg [31:0] rSIMM, xSIMM; - wire [31:0] wXCEOP = 32'hB9CE0008; - wire [31:0] wINTOP = 32'hB9CE0010; - wire [31:0] wBRKOP = 32'hB9CE0018; - wire [31:0] wBRAOP = 32'h88000000; + wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08 + wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 + wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18 + wire [31:0] wBRAOP = 32'h88000000; // NOP for branches wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT}; reg [31:0] xIREG; // --- INTERRUPT LATCH -------------------------------------- - // Debounce and latch onto the positive edge. This is independent + // Debounce and latch onto the positive level. This is independent // of the pipeline so that stalls do not affect it. reg rFINT; reg [1:0] rDINT; - //wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i; - //wire wSHOT = !rDINT[0] & sys_int_i; - wire wSHOT = (rDINT == 2'o1); + wire wSHOT = rDINT[0]; always @(posedge gclk) if (grst) begin @@ -133,7 +134,6 @@ end always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin - //xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} : {rIMM, wIDAT[15:0]}; xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} : {rIMM, wIDAT[15:0]}; end Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_regfile.v Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_scon.v Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ucore.v Deleted: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_wbbus.v Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v =================================================================== --- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,4 +1,4 @@ -// $Id: aeMB_xecu.v,v 1.7 2007/11/14 22:14:34 sybreon Exp $ +// $Id: aeMB_xecu.v,v 1.8 2007/11/16 21:52:03 sybreon Exp $ // // AEMB MAIN EXECUTION ALU // @@ -20,6 +20,9 @@ // License along with AEMB. If not, see <http://www.gnu.org/licenses/>. // // $Log: aeMB_xecu.v,v $ +// Revision 1.8 2007/11/16 21:52:03 sybreon +// Added fsl_tag_o to FSL bus (tag either address or data). +// // Revision 1.7 2007/11/14 22:14:34 sybreon // Changed interrupt handling system (reported by M. Ettus). // @@ -48,8 +51,8 @@ module aeMB_xecu (/*AUTOARG*/ // Outputs - dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE, - rMSR_BIP, + dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL, + rMSR_IE, rMSR_BIP, // Inputs rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena @@ -64,7 +67,8 @@ output [3:0] dwb_sel_o; // FSL WISHBONE - output [14:2] fsl_adr_o; + output [6:2] fsl_adr_o; + output [1:0] fsl_tag_o; // INTERNAL output [31:0] rRESULT; @@ -341,7 +345,7 @@ reg [14:2] rFSLADR, xFSLADR; - assign fsl_adr_o = rFSLADR[14:2]; + assign {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2]; always @(/*AUTOSENSE*/rALT or rRB) begin xFSLADR <= {rALT, rRB[3:2]}; Modified: usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sim/CVS/Entries 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,3 +1,3 @@ D/verilog//// -/cversim/1.3/Sun Nov 11 19:45:41 2007// -/iversim/1.3/Sun Nov 11 19:45:41 2007// +/cversim/1.3/Sat Nov 24 05:11:13 2007// +/iversim/1.3/Sat Nov 24 05:11:13 2007// Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/CVS/Entries 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,4 +1,2 @@ -/utestbench.v/1.1/Fri Apr 13 13:02:34 2007// -/testbench.v/1.6/Sat Nov 3 19:53:44 2007// -/edk32.v/1.7/Wed Nov 14 23:37:06 2007// +/edk32.v/1.9/Mon Nov 26 06:53:03 2007// D Modified: usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sim/verilog/edk32.v 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,4 +1,4 @@ -// $Id: edk32.v,v 1.7 2007/11/14 22:11:41 sybreon Exp $ +// $Id: edk32.v,v 1.9 2007/11/20 18:36:00 sybreon Exp $ // // AEMB EDK 3.2 Compatible Core TEST // @@ -20,6 +20,12 @@ // License along with AEMB. If not, see <http://www.gnu.org/licenses/>. // // $Log: edk32.v,v $ +// Revision 1.9 2007/11/20 18:36:00 sybreon +// Removed unnecessary byte acrobatics with VMEM data. +// +// Revision 1.8 2007/11/18 19:41:45 sybreon +// Minor simulation fixes. +// // Revision 1.7 2007/11/14 22:11:41 sybreon // Added posedge/negedge bus interface. // Modified interrupt test system. @@ -63,7 +69,6 @@ initial begin //$dumpfile("dump.vcd"); //$dumpvars(1,dut); - //$dumpvars(1,dut.scon); end initial begin @@ -88,11 +93,11 @@ // FAKE MEMORY //////////////////////////////////////////////////////// - wire [14:2] fsl_adr_o; wire fsl_stb_o; wire fsl_wre_o; wire [31:0] fsl_dat_o; wire [31:0] fsl_dat_i; + wire [6:2] fsl_adr_o; wire [15:2] iwb_adr_o; wire iwb_stb_o; @@ -117,10 +122,9 @@ fsl_ack_i = 0; end - assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr]; - assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr]; - assign {dwb_dat_t} = ram[dwb_adr_o]; - + assign dwb_dat_t = ram[dwb_adr_o]; + assign iwb_dat_i = ram[iadr]; + assign dwb_dat_i = ram[dadr]; assign fsl_dat_i = fsl_adr_o; //`define POSEDGE @@ -146,13 +150,13 @@ if (dwb_we_o & dwb_stb_o) begin case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]}; + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; endcase // case (dwb_sel_o) end // if (dwb_we_o & dwb_stb_o) end // always @ (negedge sys_clk_i) @@ -179,13 +183,13 @@ if (dwb_we_o & dwb_stb_o) begin case (dwb_sel_o) - 4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]}; - 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]}; - 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]}; - 4'h8: ram[dwb_adr_o] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]}; - 4'h3: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]}; - 4'hC: ram[dwb_adr_o] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]}; - 4'hF: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]}; + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; endcase // case (dwb_sel_o) end // if (dwb_we_o & dwb_stb_o) end // always @ (negedge sys_clk_i) @@ -198,7 +202,7 @@ for (i=0;i<65535;i=i+1) begin ram[i] <= $random; end - #1 $readmemh("aeMB.rom",ram); + #1 $readmemh("dump.rom",ram); end // DISPLAY OUTPUTS /////////////////////////////////////////////////// @@ -251,12 +255,6 @@ // DECODE $writeh ("\t"); - /* - case (dut.bpcu.rATOM) - 2'o2, 2'o1: $write("/"); - 2'o0, 2'o3: $write("\\"); - endcase // case (dut.bpcu.rATOM) - */ case ({dut.rBRA, dut.rDLY}) 2'b00: $write(" "); Deleted: usrp2/trunk/fpga/opencores/aemb/sim/verilog/testbench.v Deleted: usrp2/trunk/fpga/opencores/aemb/sim/verilog/utestbench.v Modified: usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sw/CVS/Entries 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,2 +1,2 @@ D/c//// -/gccrom/1.8/Sun Nov 11 19:47:07 2007// +/gccrom/1.10/Mon Nov 26 06:53:03 2007// Modified: usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sw/c/CVS/Entries 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,2 +1,2 @@ -/aeMB_testbench.c/1.11/Wed Nov 14 23:39:58 2007// +/aeMB_testbench.c/1.12/Mon Nov 26 06:53:03 2007// D Modified: usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sw/c/aeMB_testbench.c 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,5 +1,5 @@ /* - * $Id: aeMB_testbench.c,v 1.11 2007/11/14 23:41:06 sybreon Exp $ + * $Id: aeMB_testbench.c,v 1.12 2007/11/18 19:41:45 sybreon Exp $ * * AEMB Function Verification C Testbench * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <[EMAIL PROTECTED]> @@ -25,6 +25,9 @@ * * HISTORY * $Log: aeMB_testbench.c,v $ + * Revision 1.12 2007/11/18 19:41:45 sybreon + * Minor simulation fixes. + * * Revision 1.11 2007/11/14 23:41:06 sybreon * Fixed minor interrupt test typo. * @@ -68,32 +71,35 @@ - Pointer addressing - Interrupt handling */ -// void int_service (void) __attribute__((save_volatiles)); + void int_handler (void) __attribute__ ((interrupt_handler)); -int service; +volatile int service = 0xDEADDEAD; + void int_enable() { int tmp; - service = 0; - asm ("mfs %0, rmsr;" : "=r" (tmp)); - tmp = tmp | 0x02; - asm ("mts rmsr, %0;" :: "r" (tmp)); + asm volatile ("mfs %0, rmsr;" + "ori %1, %0, 0x02;" + "mts rmsr, %1;" + : "=r" (tmp) + : "r" (tmp)); } void int_disable() { int tmp; - service = 1; - asm ("mfs %0, rmsr;" : "=r" (tmp)); - tmp = tmp & 0xFD; - asm ("mts rmsr, %0;" :: "r" (tmp)); + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, 0xFD;" + "mts rmsr, %1;" + : "=r" (tmp) + : "r" (tmp)); } void int_service() { int* pio = (int*)0xFFFFFFFC; *pio = 0x52544E49; // "INTR" - service = -1; + service = 0; } void int_handler() @@ -107,11 +113,11 @@ int int_test () { // Delay loop until hardware interrupt triggers - int i; - for (i=0; i < 777; i++) { - asm volatile ("nop;"); - } - return (service == 0) ? -1 : 1; + for (volatile int i=0; i < 999; i++) { + if (service == 0) return 0; + }; + + return -1; } /** @@ -306,12 +312,12 @@ asm ("PUT %0, RFSL1" :: "r"(FSL)); asm ("GET %0, RFSL1" : "=r"(FSL)); - if (FSL != 0x04) return -1; + if (FSL != 0x01) return -1; asm ("PUT %0, RFSL31" :: "r"(FSL)); asm ("GET %0, RFSL31" : "=r"(FSL)); - if (FSL != 0x7C) return -1; + if (FSL != 0x1F) return -1; return 0; } Modified: usrp2/trunk/fpga/opencores/aemb/sw/gccrom =================================================================== --- usrp2/trunk/fpga/opencores/aemb/sw/gccrom 2007-11-25 08:24:13 UTC (rev 7021) +++ usrp2/trunk/fpga/opencores/aemb/sw/gccrom 2007-11-26 07:00:56 UTC (rev 7022) @@ -1,6 +1,12 @@ #!/bin/sh -# $Id: gccrom,v 1.8 2007/11/09 20:52:37 sybreon Exp $ +# $Id: gccrom,v 1.10 2007/11/20 18:35:34 sybreon Exp $ # $Log: gccrom,v $ +# Revision 1.10 2007/11/20 18:35:34 sybreon +# Generate VMEM instead of HEX dumps of programme. +# +# Revision 1.9 2007/11/18 19:41:46 sybreon +# Minor simulation fixes. +# # Revision 1.8 2007/11/09 20:52:37 sybreon # Added some compilation optimisations. # @@ -27,11 +33,26 @@ # Revision 1.1 2007/03/09 17:41:56 sybreon # initial import # -#mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -mno-clearbss -msmall-divides -mno-memcpy -mno-xl-gp-opt -o rom.o $@ && \ -mb-gcc -g -mstats -mxl-soft-div -msoft-float -mno-memcpy -msmall-divides -o rom.o $@ && \ -#mb-run -v rom.o 2> rom.run && \ -mb-objcopy -O binary rom.o rom.bin && \ -hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \ -mb-objdump -DSC rom.o > rom.dump && \ -rm rom.bin && \ + +# Compile using C++ pre-processor +mb-g++ -g -mstats -mxl-soft-div -msoft-float -mno-memcpy -msmall-divides -o rom.elf $@ && \ + +# Create a text listing of the compiled code +mb-objdump -dSC rom.elf > rom.dump && \ + +# Convert the ELF file to an SREC file +mb-objcopy -O srec rom.elf rom.srec && \ + +# Generate a Verilog VMEM file from the SREC file +srec_cat rom.srec -o ../sim/dump.rom -vmem 32 && \ + +#mb-run -v rom.elf 2> rom.run && \ +#mb-objcopy -O binary rom.elf rom.bin && \ +#hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \ +#rm rom.bin && \ + +# Cleanup code +rm rom.srec && \ + +# Say Cheeze! echo "ROM generated" _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
