Author: matt
Date: 2007-12-03 14:34:01 -0700 (Mon, 03 Dec 2007)
New Revision: 7065
Modified:
usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
Log:
declare all signals
Modified: usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
===================================================================
--- usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
2007-12-03 21:33:33 UTC (rev 7064)
+++ usrp2/trunk/fpga/opencores/uart16550/rtl/verilog/uart_regs.v
2007-12-03 21:34:01 UTC (rev 7065)
@@ -399,6 +399,7 @@
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
+ wire rf_push_pulse, rf_overrun;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset,
lsr_mask, rstate, rf_push_pulse);
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