Author: matt Date: 2007-12-06 01:04:21 -0700 (Thu, 06 Dec 2007) New Revision: 7077
Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj Log: who knows what changed... its binary Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise =================================================================== (Binary files differ) Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj =================================================================== --- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj 2007-12-06 08:03:20 UTC (rev 7076) +++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj 2007-12-06 08:04:21 UTC (rev 7077) @@ -1,8 +1,10 @@ verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v" +verilog work "../../control_lib/ram_2port.v" verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v" verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v" verilog work "../../eth/rtl/verilog/TECH/duram.v" -verilog work "../../control_lib/ram_2port.v" +verilog work "../../control_lib/shortfifo.v" +verilog work "../../control_lib/longfifo.v" verilog work "../../sdr_lib/sign_extend.v" verilog work "../../sdr_lib/cordic_stage.v" verilog work "../../sdr_lib/cic_int_shifter.v" @@ -22,7 +24,6 @@ verilog work "../../eth/rtl/verilog/TECH/eth_clk_switch.v" verilog work "../../eth/rtl/verilog/TECH/eth_clk_div2.v" verilog work "../../eth/rtl/verilog/Reg_int.v" -verilog work "../../eth/rtl/verilog/RMON/RMON_dpram.v" verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v" verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" verilog work "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" @@ -36,8 +37,14 @@ verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" -verilog work "../../control_lib/shortfifo.v" -verilog work "../../control_lib/longfifo.v" +verilog work "../../control_lib/ss_rcvr.v" +verilog work "../../control_lib/cascadefifo2.v" +verilog work "../../control_lib/cascadefifo.v" +verilog work "../../control_lib/CRC16_D16.v" +verilog work "../../serdes/serdes_tx.v" +verilog work "../../serdes/serdes_rx.v" +verilog work "../../serdes/serdes_fc_tx.v" +verilog work "../../serdes/serdes_fc_rx.v" verilog work "../../sdr_lib/round.v" verilog work "../../sdr_lib/cordic.v" verilog work "../../sdr_lib/cic_interp.v" @@ -56,16 +63,15 @@ verilog work "../../eth/rtl/verilog/MAC_rx.v" verilog work "../../eth/rtl/verilog/Clk_ctrl.v" verilog work "../../control_lib/strobe_gen.v" -verilog work "../../control_lib/ss_rcvr.v" verilog work "../../control_lib/setting_reg.v" verilog work "../../control_lib/mux8.v" verilog work "../../control_lib/mux4.v" verilog work "../../control_lib/icache.v" verilog work "../../control_lib/dpram32.v" verilog work "../../control_lib/decoder_3_8.v" -verilog work "../../control_lib/cascadefifo.v" +verilog work "../../control_lib/dcache.v" verilog work "../../control_lib/buffer_int.v" -verilog work "../../control_lib/CRC16_D16.v" +verilog work "../../serdes/serdes.v" verilog work "../../sdr_lib/tx_control.v" verilog work "../../sdr_lib/rx_control.v" verilog work "../../sdr_lib/dsp_core_tx.v" @@ -83,11 +89,10 @@ verilog work "../../control_lib/timer.v" verilog work "../../control_lib/system_control.v" verilog work "../../control_lib/settings_bus.v" -verilog work "../../control_lib/serdes_tx.v" -verilog work "../../control_lib/serdes_rx.v" verilog work "../../control_lib/ram_loader.v" verilog work "../../control_lib/ram_harv_cache.v" verilog work "../../control_lib/nsgpio.v" verilog work "../../control_lib/buffer_pool.v" +verilog work "../../control_lib/atr_controller.v" verilog work "../u2_basic/u2_basic.v" verilog work "u2_fpga_top.v" _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
