Author: matt
Date: 2007-12-09 19:17:52 -0700 (Sun, 09 Dec 2007)
New Revision: 7091
Modified:
usrp2/trunk/fpga/models/M24LC024B.v
Log:
remove the speedup, so this is accurate again
Modified: usrp2/trunk/fpga/models/M24LC024B.v
===================================================================
--- usrp2/trunk/fpga/models/M24LC024B.v 2007-12-09 21:33:26 UTC (rev 7090)
+++ usrp2/trunk/fpga/models/M24LC024B.v 2007-12-10 02:17:52 UTC (rev 7091)
@@ -130,8 +130,8 @@
//
*******************************************************************************************************
initial tAA = 900; // SCL to SDA output
delay
- //initial tWC = 5000000; // memory write cycle
time
- initial tWC = 50000; // memory write cycle
time
+ initial tWC = 5000000; // memory write cycle
time
+ //initial tWC = 50000; // shortened memory
write cycle time to speed up sims
initial begin
SDA_DO = 0;
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