Author: matt
Date: 2007-12-12 16:03:50 -0700 (Wed, 12 Dec 2007)
New Revision: 7134
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
Log:
Fix the computation of the amount of space in the fifo. Math is hard.
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-12 22:37:56 UTC
(rev 7133)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-12 23:03:50 UTC
(rev 7134)
@@ -338,8 +338,8 @@
assign Fifo_full = Almost_full;
- wire [RX_FF_DEPTH-1:0] Fifo_space_int = (Add_rd_ungray - Add_wr);
- assign Fifo_space =
{{(16-RX_FF_DEPTH){1'b0}},Fifo_space_int};
+ wire [RX_FF_DEPTH-1:0] fullness = Add_wr - Add_rd_ungray;
+ wire [15:0] Fifo_space = (1<<RX_FF_DEPTH) -
{{(16-RX_FF_DEPTH){1'b0}},fullness};
always @( posedge Clk_MAC or posedge Reset )
if ( Reset )
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