Author: matt
Date: 2007-12-16 22:36:36 -0700 (Sun, 16 Dec 2007)
New Revision: 7210
Modified:
usrp2/trunk/fpga/sdr_lib/round.v
Log:
order of operations is important...
Modified: usrp2/trunk/fpga/sdr_lib/round.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/round.v 2007-12-17 05:20:42 UTC (rev 7209)
+++ usrp2/trunk/fpga/sdr_lib/round.v 2007-12-17 05:36:36 UTC (rev 7210)
@@ -27,7 +27,7 @@
parameter bits_out=0)
(input [bits_in-1:0] in,
output [bits_out-1:0] out);
+
+ assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] &
|in[bits_in-bits_out-1:0]);
- assign out = in[bits_in-1:bits_in-bits_out] + in[bits_in-1] &
|in[bits_in-bits_out-1:0];
-
endmodule // round
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