[Commit-gnuradio] r7223 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx

[matt]

Author: matt
Date: 2007-12-17 17:53:30 -0700 (Mon, 17 Dec 2007)
New Revision: 7223

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
Log:
registered fifo_space calculation to help timing.  We are now 1 cycle behind, 
but this is not a problem.


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-18 00:50:44 UTC 
(rev 7222)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-18 00:53:30 UTC 
(rev 7223)
@@ -74,7 +74,7 @@
      input         Fifo_data_err,
      input         Fifo_data_drop,
      input         Fifo_data_end,
-     output [15:0] Fifo_space,
+     output reg [15:0] Fifo_space,
      
      // CPU
      input         RX_APPEND_CRC,
@@ -339,7 +339,8 @@
   assign Fifo_full = Almost_full;
 
    wire [RX_FF_DEPTH-1:0] fullness = Add_wr - Add_rd_ungray;
-   assign                Fifo_space = (1<<RX_FF_DEPTH) - 
{{(16-RX_FF_DEPTH){1'b0}},fullness};
+   always @(posedge Clk_MAC)
+     Fifo_space <= (1<<RX_FF_DEPTH) - {{(16-RX_FF_DEPTH){1'b0}},fullness};
        
   always @( posedge Clk_MAC or posedge Reset )
     if ( Reset )



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