Author: matt Date: 2007-12-22 15:15:41 -0700 (Sat, 22 Dec 2007) New Revision: 7240
Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj Log: new timing files Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise =================================================================== (Binary files differ) Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj =================================================================== --- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj 2007-12-22 22:15:15 UTC (rev 7239) +++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj 2007-12-22 22:15:41 UTC (rev 7240) @@ -71,6 +71,8 @@ verilog work "../../control_lib/decoder_3_8.v" verilog work "../../control_lib/dcache.v" verilog work "../../control_lib/buffer_int.v" +verilog work "../../timing/timer.v" +verilog work "../../timing/pps.v" verilog work "../../serdes/serdes.v" verilog work "../../sdr_lib/tx_control.v" verilog work "../../sdr_lib/rx_control.v" @@ -86,7 +88,6 @@ verilog work "../../eth/mac_rxfifo_int.v" verilog work "../../control_lib/wb_readback_mux.v" verilog work "../../control_lib/wb_1master.v" -verilog work "../../control_lib/timer.v" verilog work "../../control_lib/system_control.v" verilog work "../../control_lib/settings_bus.v" verilog work "../../control_lib/ram_loader.v" _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
