Author: matt
Date: 2007-12-26 16:20:29 -0700 (Wed, 26 Dec 2007)
New Revision: 7271

Modified:
   usrp2/trunk/fpga/timing/time_sync.v
Log:
use proper clock domain for wb signal


Modified: usrp2/trunk/fpga/timing/time_sync.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sync.v 2007-12-26 19:56:43 UTC (rev 7270)
+++ usrp2/trunk/fpga/timing/time_sync.v 2007-12-26 23:20:29 UTC (rev 7271)
@@ -64,7 +64,7 @@
    always @(posedge wb_clk_i)
      pps_time_wb <= pps_time;
    
-   assign dat_o = pps_time;
+   assign dat_o = pps_time_wb;
    assign int_o = pps_int_enable & pps_internal;
 
    assign pps_internal = 



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