Author: matt
Date: 2008-01-08 12:43:25 -0700 (Tue, 08 Jan 2008)
New Revision: 7379
Modified:
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
Log:
Fix for barrel shifter pipeline control. Believed to be working, but not
heavily verified
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2008-01-08
19:41:44 UTC (rev 7378)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2008-01-08
19:43:25 UTC (rev 7379)
@@ -96,7 +96,7 @@
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^
fsl_ack_i) | !iwb_ack_i) & !rSTALL;
-
+ wire other_stall = (dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^
fsl_ack_i) | ~iwb_ack_i;
// --- INSTANTIATIONS -------------------------------------
aeMB_ibuf
@@ -121,7 +121,9 @@
.sys_int_i (sys_int_i),
.gclk (gclk),
.grst (grst),
- .gena (gena));
+ .gena (gena),
+ .other_stall (other_stall)
+ );
aeMB_ctrl
ctrl (/*AUTOINST*/
@@ -281,4 +283,4 @@
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
-*/
\ No newline at end of file
+*/
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v 2008-01-08
19:41:44 UTC (rev 7378)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v 2008-01-08
19:43:25 UTC (rev 7379)
@@ -24,7 +24,7 @@
rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
// Inputs
rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
- grst, gena
+ grst, gena, other_stall
);
// INTERNAL
output [15:0] rIMM;
@@ -50,7 +50,8 @@
// SYSTEM
input gclk, grst, gena;
-
+ input other_stall;
+
reg [15:0] rIMM;
reg [4:0] rRA, rRD;
reg [5:0] rOPC;
@@ -144,7 +145,8 @@
rSTALL <= 1'h0;
// End of automatics
end else begin
- rSTALL <= #1 !rSTALL & (fMUL | fBSF);
+ //rSTALL <= #1 (!rSTALL | other_stall) & (fMUL | fBSF);
+ rSTALL <= #1 (rSTALL & other_stall) | (!rSTALL & (fMUL | fBSF));
end
endmodule // aeMB_ibuf
@@ -178,4 +180,4 @@
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
-*/
\ No newline at end of file
+*/
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