Author: matt
Date: 2008-01-13 18:53:30 -0700 (Sun, 13 Jan 2008)
New Revision: 7425
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/RMON.v
Log:
possibly undo breakage from when we switched to distram from block ram
Modified: usrp2/trunk/fpga/eth/rtl/verilog/RMON.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/RMON.v 2008-01-14 01:52:46 UTC (rev
7424)
+++ usrp2/trunk/fpga/eth/rtl/verilog/RMON.v 2008-01-14 01:53:30 UTC (rev
7425)
@@ -169,10 +169,14 @@
);
reg [31:0] RMON_ram [0:63];
+ reg [31:0] Douta_reg;
always @(posedge Clk)
if(Wea)
RMON_ram[Addra] <= Dina;
- assign Douta = RMON_ram[Addra];
-
+ //assign Douta = RMON_ram[Addra];
+ always @(posedge Clk)
+ Douta_reg <= RMON_ram[Addra];
+ assign Douta = Douta_reg;
+
endmodule // RMON
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