[Commit-gnuradio] r7434 - usrp2/trunk/fpga/eth/rtl/verilog

[matt]

Author: matt
Date: 2008-01-14 02:25:27 -0700 (Mon, 14 Jan 2008)
New Revision: 7434

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
Log:
ise got confused, so I put back the reset


Modified: usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v  2008-01-14 07:39:47 UTC (rev 
7433)
+++ usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v  2008-01-14 09:25:27 UTC (rev 
7434)
@@ -181,6 +181,9 @@
       ACK_O <= Access;
 
   always @ ( posedge RST_I or posedge CLK_I )
+    if(RST_I)
+      DAT_O <= 0;
+    else
       begin
         DAT_O <=0;
         if ( Access & ~WE_I )



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