Author: matt Date: 2008-01-16 00:22:53 -0700 (Wed, 16 Jan 2008) New Revision: 7449
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v Log: cleanup to make it more readable, should be the same functionality Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v =================================================================== --- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-01-16 07:21:27 UTC (rev 7448) +++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-01-16 07:22:53 UTC (rev 7449) @@ -35,32 +35,7 @@ //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: MAC_rx_FF.v,v $ -// Revision 1.5 2006/06/25 04:58:56 maverickist -// no message -// -// Revision 1.4 2006/05/28 05:09:20 maverickist -// no message -// -// Revision 1.3 2006/01/19 14:07:54 maverickist -// verification is complete. -// -// Revision 1.3 2005/12/16 06:44:16 Administrator -// replaced tab with space. -// passed 9.6k length frame test. -// -// Revision 1.2 2005/12/13 12:15:37 Administrator -// no message -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -`include "header.vh" - module MAC_rx_FF #(parameter RX_FF_DEPTH = 9) (input Reset, @@ -111,7 +86,7 @@ localparam SYS_pause = 3'd1; localparam SYS_wait_end = 3'd2; localparam SYS_idle = 3'd3; - localparam FF_emtpy_err = 3'd4; + localparam SYS_empty_err = 3'd4; reg [RX_FF_DEPTH-1:0] Add_wr; reg [RX_FF_DEPTH-1:0] Add_wr_ungray; @@ -140,29 +115,18 @@ reg Full; reg Almost_full; -`ifdef MAC_TARGET_ALTERA - - reg Empty /* synthesis syn_keep=1 */ ; - reg [3:0] Current_state /* synthesis syn_keep=1 */ ; - reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */ ; - reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */ ; - -`else - reg Empty; reg [3:0] Current_state; reg [2:0] Current_state_SYS; reg [5:0] Packet_number_inFF; -`endif - reg [3:0] Next_state; reg [7:0] Fifo_data_byte1; reg [7:0] Fifo_data_byte2; reg [7:0] Fifo_data_byte3; reg Fifo_data_en_dl1; reg [7:0] Fifo_data_dl1; - reg Rx_mac_sop_tmp; + reg Rx_mac_sop_pre1, Rx_mac_sop_pre2; reg [2:0] Next_state_SYS; reg Packet_number_sub; @@ -174,10 +138,9 @@ reg Packet_number_add_tmp_dl1; reg Packet_number_add_tmp_dl2; - reg Rx_mac_sop_tmp_dl1; reg [35:0] Dout_dl1; reg [4:0] Fifo_data_count; - reg Rx_mac_pa_tmp; + reg Rx_mac_pa_pre; reg Add_wr_jump_tmp; reg Add_wr_jump_tmp_pl1; reg Add_wr_jump; @@ -477,7 +440,7 @@ Packet_number_add_tmp_dl2 <= Packet_number_add_tmp_dl1; end - // Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram. + // Packet_number_add delay to Din[35] is needed to make sure the data have been written to ram. // expand to two cycles long almost=16 ns // If the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles // CFH: TBD: piece of crap!!!!!!! @@ -489,222 +452,218 @@ else Packet_number_add <= 0; - //------------------------------------------------------------------------- - // Domain Clk_SYS,read data from dprom.b-port for read - //------------------------------------------------------------------------- - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Current_state_SYS <= SYS_idle; - else - Current_state_SYS <= Next_state_SYS; - - always @( Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty ) - case ( Current_state_SYS ) - SYS_idle: - if ( Rx_mac_rd && Rx_mac_ra && !Empty ) - Next_state_SYS = SYS_read; - else if( Rx_mac_rd && Rx_mac_ra && Empty ) - Next_state_SYS = FF_emtpy_err; - else - Next_state_SYS = Current_state_SYS; - - SYS_read: - if ( !Rx_mac_rd ) - Next_state_SYS = SYS_pause; - else if ( Dout[35] ) - Next_state_SYS = SYS_wait_end; - else if ( Empty ) - Next_state_SYS = FF_emtpy_err; - else - Next_state_SYS = Current_state_SYS; - - SYS_pause: - if ( Rx_mac_rd ) - Next_state_SYS = SYS_read; - else - Next_state_SYS = Current_state_SYS; - - FF_emtpy_err: - if ( !Empty ) - Next_state_SYS = SYS_read; - else - Next_state_SYS = Current_state_SYS; - - SYS_wait_end: - if ( !Rx_mac_rd ) - Next_state_SYS = SYS_idle; - else - Next_state_SYS = Current_state_SYS; - - default: - Next_state_SYS = SYS_idle; - endcase - - // Gen Rx_mac_ra - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - begin - Packet_number_add_dl1 <= 0; - Packet_number_add_dl2 <= 0; - end - else - begin - Packet_number_add_dl1 <= Packet_number_add; - Packet_number_add_dl2 <= Packet_number_add_dl1; - end - - assign Packet_number_add_edge = Packet_number_add_dl1 & !Packet_number_add_dl2; - - always @( Current_state_SYS or Next_state_SYS ) - if ( (Current_state_SYS==SYS_read) && (Next_state_SYS==SYS_wait_end) ) - Packet_number_sub = 1; - else - Packet_number_sub = 0; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Packet_number_inFF <= 0; - else if ( Packet_number_add_edge && !Packet_number_sub ) - Packet_number_inFF <= Packet_number_inFF + 1; - else if ( !Packet_number_add_edge && Packet_number_sub && (Packet_number_inFF!=0) ) - Packet_number_inFF <= Packet_number_inFF - 1; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Fifo_data_count <= 0; - else - Fifo_data_count <= - Add_wr_ungray[RX_FF_DEPTH-1:RX_FF_DEPTH-5] - - Add_rd[RX_FF_DEPTH-1:RX_FF_DEPTH-5]; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - begin - Rx_Hwmark_pl <=0; - Rx_Lwmark_pl <=0; - end - else - begin - Rx_Hwmark_pl <= Rx_Hwmark; - Rx_Lwmark_pl <= Rx_Lwmark; - end - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Rx_mac_ra <= 0; - else if ( (Packet_number_inFF==0) && (Fifo_data_count <= Rx_Lwmark_pl) ) - Rx_mac_ra <=0; - else if ( (Packet_number_inFF >= 1) || (Fifo_data_count >= Rx_Hwmark_pl) ) - Rx_mac_ra <= 1; - - // Control Add_rd signal - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Add_rd <= 0; - else if ( (Current_state_SYS==SYS_read) && !Dout[35] ) - Add_rd <= Add_rd + 1; - - // - always @( posedge Reset or posedge Clk_SYS ) - if ( Reset ) - Add_rd_gray <= 0; - else - begin : Add_rd_gray_loop - integer i; - Add_rd_gray[RX_FF_DEPTH-1] <= Add_rd[RX_FF_DEPTH-1]; + //------------------------------------------------------------------------- + // Domain Clk_SYS,read data from dprom.b-port for read + //------------------------------------------------------------------------- + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Current_state_SYS <= SYS_idle; + else + Current_state_SYS <= Next_state_SYS; + + always @* + case ( Current_state_SYS ) + SYS_idle: + if ( Rx_mac_rd && Rx_mac_ra && !Empty ) + Next_state_SYS = SYS_read; + else if( Rx_mac_rd && Rx_mac_ra && Empty ) + Next_state_SYS = SYS_empty_err; + else + Next_state_SYS = Current_state_SYS; + + SYS_read: + if ( !Rx_mac_rd ) + Next_state_SYS = SYS_pause; + else if ( Dout[35] ) + Next_state_SYS = SYS_wait_end; + else if ( Empty ) + Next_state_SYS = SYS_empty_err; + else + Next_state_SYS = Current_state_SYS; + + SYS_pause: + if ( Rx_mac_rd ) + Next_state_SYS = SYS_read; + else + Next_state_SYS = Current_state_SYS; + + SYS_empty_err: + if ( !Empty ) + Next_state_SYS = SYS_read; + else + Next_state_SYS = Current_state_SYS; + + SYS_wait_end: + if ( !Rx_mac_rd ) + Next_state_SYS = SYS_idle; + else + Next_state_SYS = Current_state_SYS; + + default: + Next_state_SYS = SYS_idle; + endcase + + // Gen Rx_mac_ra + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + begin + Packet_number_add_dl1 <= 0; + Packet_number_add_dl2 <= 0; + end + else + begin + Packet_number_add_dl1 <= Packet_number_add; + Packet_number_add_dl2 <= Packet_number_add_dl1; + end + + assign Packet_number_add_edge = Packet_number_add_dl1 & !Packet_number_add_dl2; + + always @( Current_state_SYS or Next_state_SYS ) + if ( (Current_state_SYS==SYS_read) && (Next_state_SYS==SYS_wait_end) ) + Packet_number_sub = 1; + else + Packet_number_sub = 0; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Packet_number_inFF <= 0; + else if ( Packet_number_add_edge && !Packet_number_sub ) + Packet_number_inFF <= Packet_number_inFF + 1; + else if ( !Packet_number_add_edge && Packet_number_sub && (Packet_number_inFF!=0) ) + Packet_number_inFF <= Packet_number_inFF - 1; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Fifo_data_count <= 0; + else + Fifo_data_count <= + Add_wr_ungray[RX_FF_DEPTH-1:RX_FF_DEPTH-5] - + Add_rd[RX_FF_DEPTH-1:RX_FF_DEPTH-5]; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + begin + Rx_Hwmark_pl <=0; + Rx_Lwmark_pl <=0; + end + else + begin + Rx_Hwmark_pl <= Rx_Hwmark; + Rx_Lwmark_pl <= Rx_Lwmark; + end + + // Control Add_rd signal + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Add_rd <= 0; + else if ( (Current_state_SYS==SYS_read) && !Dout[35] ) + Add_rd <= Add_rd + 1; + + // + always @( posedge Reset or posedge Clk_SYS ) + if ( Reset ) + Add_rd_gray <= 0; + else + begin : Add_rd_gray_loop + integer i; + Add_rd_gray[RX_FF_DEPTH-1] <= Add_rd[RX_FF_DEPTH-1]; + for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 ) + Add_rd_gray[i] <= Add_rd[i+1] ^ Add_rd[i]; + end + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + begin + Add_wr_gray_dl1 <= 0; + Add_wr_jump_rd_pl1 <= 0; + end + else + begin + Add_wr_gray_dl1 <= Add_wr_gray; + Add_wr_jump_rd_pl1 <= Add_wr_jump; + end + + // CFH: Rewritten to not depend on simulation order - extremely dangerous coding style!!! + always @( * ) + begin : Add_wr_ungray_loop + integer i; + Add_wr_ungray_next[RX_FF_DEPTH-1] = Add_wr_gray_dl1[RX_FF_DEPTH-1]; for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 ) - Add_rd_gray[i] <= Add_rd[i+1] ^ Add_rd[i]; - end - - // - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - begin - Add_wr_gray_dl1 <= 0; - Add_wr_jump_rd_pl1 <= 0; - end - else - begin - Add_wr_gray_dl1 <= Add_wr_gray; - Add_wr_jump_rd_pl1 <= Add_wr_jump; - end - - // CFH: Rewritten to not depend on simulation order - extremely dangerous coding style!!! - always @( * ) - begin : Add_wr_ungray_loop - integer i; - Add_wr_ungray_next[RX_FF_DEPTH-1] = Add_wr_gray_dl1[RX_FF_DEPTH-1]; - for ( i=RX_FF_DEPTH-2; i>=0; i=i-1 ) Add_wr_ungray_next[i] = Add_wr_ungray_next[i+1] ^ Add_wr_gray_dl1[i]; - end + end + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Add_wr_ungray <= 0; + else if ( !Add_wr_jump_rd_pl1 ) + Add_wr_ungray <= Add_wr_ungray_next; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Empty <=1; + else if ( Add_rd==Add_wr_ungray ) + Empty <= 1; + else + Empty <= 0; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Dout_dl1 <= 0; + else + Dout_dl1 <= Dout; + + assign Rx_mac_data = Dout_dl1[31:0]; // No need for --> | {32{Rx_mac_err}}; + assign Rx_mac_BE = Dout_dl1[33:32]; + assign Rx_mac_err = Dout_dl1[34]; + assign Rx_mac_eop = Dout_dl1[35]; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Rx_mac_ra <= 0; + else if ( (Packet_number_inFF==0) && (Fifo_data_count <= Rx_Lwmark_pl) ) + Rx_mac_ra <=0; + else if ( (Packet_number_inFF >= 1) || (Fifo_data_count >= Rx_Hwmark_pl) ) + Rx_mac_ra <= 1; + + // Aligned to Addr_rd + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Rx_mac_pa_pre <= 0; + else if ( (Current_state_SYS==SYS_read) && !Dout[35] ) + Rx_mac_pa_pre <= 1; + else + Rx_mac_pa_pre <= 0; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Rx_mac_pa <= 0; + else + Rx_mac_pa <= Rx_mac_pa_pre; + + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + Rx_mac_sop_pre2 <= 0; + else if ( (Current_state_SYS==SYS_idle) && (Next_state_SYS==SYS_read) ) + Rx_mac_sop_pre2 <= 1; + else + Rx_mac_sop_pre2 <= 0; - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Add_wr_ungray <= 0; - else if ( !Add_wr_jump_rd_pl1 ) - Add_wr_ungray <= Add_wr_ungray_next; - - // Empty signal gen - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Empty <=1; - else if ( Add_rd==Add_wr_ungray ) - Empty <= 1; - else - Empty <= 0; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Dout_dl1 <= 0; - else - Dout_dl1 <= Dout; - - - assign Rx_mac_data = Dout_dl1[31:0] | {32{Rx_mac_err}}; - assign Rx_mac_BE = Dout_dl1[33:32]; - assign Rx_mac_err = Dout_dl1[34]; - assign Rx_mac_eop = Dout_dl1[35]; - - // Aligned to Addr_rd - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Rx_mac_pa_tmp <= 0; - else if ( (Current_state_SYS==SYS_read) && !Dout[35] ) - Rx_mac_pa_tmp <= 1; - else - Rx_mac_pa_tmp <= 0; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Rx_mac_pa <= 0; - else - Rx_mac_pa <= Rx_mac_pa_tmp; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - Rx_mac_sop_tmp <= 0; - else if ( (Current_state_SYS==SYS_idle) && (Next_state_SYS==SYS_read) ) - Rx_mac_sop_tmp <= 1; - else - Rx_mac_sop_tmp <= 0; - - always @( posedge Clk_SYS or posedge Reset ) - if ( Reset ) - begin - Rx_mac_sop_tmp_dl1 <= 0; - Rx_mac_sop <= 0; - end - else - begin - Rx_mac_sop_tmp_dl1 <= Rx_mac_sop_tmp; - Rx_mac_sop <= Rx_mac_sop_tmp_dl1; - end - + always @( posedge Clk_SYS or posedge Reset ) + if ( Reset ) + begin + Rx_mac_sop_pre1 <= 0; + Rx_mac_sop <= 0; + end + else + begin + Rx_mac_sop_pre1 <= Rx_mac_sop_pre2; + Rx_mac_sop <= Rx_mac_sop_pre1; + end + // Instantiation of dual-ported RAM ram_2port #(.DWIDTH(36),.AWIDTH(RX_FF_DEPTH)) mac_rx_ff_ram (.clka(Clk_MAC),.ena(1'b1),.wea(Wr_en),.addra(Add_wr),.dia(Din),.doa(), .clkb(Clk_SYS),.enb(1'b1),.web(1'b0),.addrb(Add_rd),.dib(36'b0),.dob(Dout) ); - + endmodule // MAC_rx_FF - _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
