Author: matt Date: 2008-01-31 12:37:41 -0700 (Thu, 31 Jan 2008) New Revision: 7532
Added: usrp2/trunk/fpga/control_lib/bin2gray.v usrp2/trunk/fpga/control_lib/fifo_2clock.v usrp2/trunk/fpga/control_lib/gray2bin.v usrp2/trunk/fpga/control_lib/gray_send.v Log: my own fifo Added: usrp2/trunk/fpga/control_lib/bin2gray.v =================================================================== --- usrp2/trunk/fpga/control_lib/bin2gray.v (rev 0) +++ usrp2/trunk/fpga/control_lib/bin2gray.v 2008-01-31 19:37:41 UTC (rev 7532) @@ -0,0 +1,10 @@ + + +module bin2gray + #(parameter WIDTH=8) + (input [WIDTH-1:0] bin, + output [WIDTH-1:0] gray); + + assign gray = (bin >> 1) ^ bin; + +endmodule // bin2gray Added: usrp2/trunk/fpga/control_lib/fifo_2clock.v =================================================================== --- usrp2/trunk/fpga/control_lib/fifo_2clock.v (rev 0) +++ usrp2/trunk/fpga/control_lib/fifo_2clock.v 2008-01-31 19:37:41 UTC (rev 7532) @@ -0,0 +1,64 @@ + +module fifo_2clock + #(parameter DWIDTH=32, AWIDTH=9) + (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk, + input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk, + input arst); + + reg [AWIDTH-1:0] wr_addr, rd_addr; + wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk; + wire [AWIDTH-1:0] next_rd_addr; + wire enb_read; + + // Write side management + wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1; + always @(posedge wclk or posedge arst) + if(arst) + wr_addr <= 0; + else if(write) + wr_addr <= next_wr_addr; + assign full = (next_wr_addr == rd_addr_wclk); + + // RAM for data storage. Data out is registered, complicating the + // read side logic + ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram + (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(), + .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) ); + + // Read side management + reg data_valid; + assign empty = ~data_valid; + assign next_rd_addr = rd_addr + data_valid; + assign enb_read = read | ~data_valid; + + always @(posedge rclk or posedge arst) + if(arst) + rd_addr <= 0; + else if(read) + rd_addr <= rd_addr + 1; + + always @(posedge rclk or posedge arst) + if(arst) + data_valid <= 0; + else + if(read & (next_rd_addr == wr_addr_rclk)) + data_valid <= 0; + else if(next_rd_addr != wr_addr_rclk) + data_valid <= 1; + + // Send pointers across clock domains via gray code + gray_send #(.WIDTH(AWIDTH)) send_wr_addr + (.clk_in(wclk),.addr_in(wr_addr), + .clk_out(rclk),.addr_out(wr_addr_rclk) ); + + gray_send #(.WIDTH(AWIDTH)) send_rd_addr + (.clk_in(rclk),.addr_in(rd_addr), + .clk_out(wclk),.addr_out(rd_addr_wclk) ); + + // Generate fullness info, these are approximate + // and are only for higher-level flow control. + // Only full and empty are guaranteed exact. + assign level_wclk = wr_addr - rd_addr_wclk; + assign level_rclk = wr_addr_rclk - rd_addr; + +endmodule // fifo_2clock Added: usrp2/trunk/fpga/control_lib/gray2bin.v =================================================================== --- usrp2/trunk/fpga/control_lib/gray2bin.v (rev 0) +++ usrp2/trunk/fpga/control_lib/gray2bin.v 2008-01-31 19:37:41 UTC (rev 7532) @@ -0,0 +1,13 @@ + + +module gray2bin + #(parameter WIDTH=8) + (input [WIDTH-1:0] gray, + output reg [WIDTH-1:0] bin); + + integer i; + always @(gray) + for(i = 0;i<WIDTH;i=i+1) + bin[i] = ^(gray>>i); + +endmodule // gray2bin Added: usrp2/trunk/fpga/control_lib/gray_send.v =================================================================== --- usrp2/trunk/fpga/control_lib/gray_send.v (rev 0) +++ usrp2/trunk/fpga/control_lib/gray_send.v 2008-01-31 19:37:41 UTC (rev 7532) @@ -0,0 +1,26 @@ + + + +module gray_send + #(parameter WIDTH = 8) + (input clk_in, input [WIDTH-1:0] addr_in, + input clk_out, output reg [WIDTH-1:0] addr_out); + + reg [WIDTH-1:0] gray_clkin, gray_clkout; + wire [WIDTH-1:0] gray, bin; + + bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); + + always @(posedge clk_in) + gray_clkin <= gray; + + always @(posedge clk_out) + gray_clkout <= gray_clkin; + + gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout), .bin(bin) ); + + // FIXME we may not need the next register, but it may help timing + always @(posedge clk_out) + addr_out <= bin; + +endmodule // gray_send _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
