Author: matt
Date: 2008-02-04 10:22:58 -0700 (Mon, 04 Feb 2008)
New Revision: 7554
Modified:
usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
Log:
fixed debug port
Modified: usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
===================================================================
--- usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
2008-02-04 17:13:24 UTC (rev 7553)
+++ usrp2/branches/developers/matt/newfifo/fpga/eth/rtl/verilog/MAC_rx.v
2008-02-04 17:22:58 UTC (rev 7554)
@@ -166,7 +166,7 @@
.RX_MIN_LENGTH (RX_MIN_LENGTH )
);
- assign debug = {'d0, Fifo_data_en, Fifo_data_err,
Fifo_data_end,Fifo_full};
+ assign debug = {28'd0, Fifo_data_en, Fifo_data_err,
Fifo_data_end,Fifo_full};
MAC_rx_FF #(.RX_FF_DEPTH(RX_FF_DEPTH)) U_MAC_rx_FF (
.Reset (Reset ),
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