Author: matt
Date: 2008-02-05 11:56:57 -0700 (Tue, 05 Feb 2008)
New Revision: 7571
Modified:
usrp2/branches/developers/matt/newfifo/fpga/control_lib/gray_send.v
Log:
Delayed gray coded signal in an attempt to fix our fifo, but it still glitches
Modified: usrp2/branches/developers/matt/newfifo/fpga/control_lib/gray_send.v
===================================================================
--- usrp2/branches/developers/matt/newfifo/fpga/control_lib/gray_send.v
2008-02-05 18:55:56 UTC (rev 7570)
+++ usrp2/branches/developers/matt/newfifo/fpga/control_lib/gray_send.v
2008-02-05 18:56:57 UTC (rev 7571)
@@ -6,7 +6,7 @@
(input clk_in, input [WIDTH-1:0] addr_in,
input clk_out, output reg [WIDTH-1:0] addr_out);
- reg [WIDTH-1:0] gray_clkin, gray_clkout;
+ reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
wire [WIDTH-1:0] gray, bin;
bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );
@@ -16,8 +16,11 @@
always @(posedge clk_out)
gray_clkout <= gray_clkin;
+
+ always @(posedge clk_out)
+ gray_clkout_d1 <= gray_clkout;
- gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout), .bin(bin) );
+ gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );
// FIXME we may not need the next register, but it may help timing
always @(posedge clk_out)
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