Author: matt Date: 2008-02-14 11:40:52 -0700 (Thu, 14 Feb 2008) New Revision: 7678
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v Log: debug pins and spelling and comment fixes Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v =================================================================== --- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-02-14 18:37:51 UTC (rev 7677) +++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-02-14 18:40:52 UTC (rev 7678) @@ -35,20 +35,6 @@ //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: MAC_top.v,v $ -// Revision 1.3 2006/01/19 14:07:52 maverickist -// verification is complete. -// -// Revision 1.2 2005/12/16 06:44:13 Administrator -// replaced tab with space. -// passed 9.6k length frame test. -// -// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator -// no message -// module MAC_top #(parameter TX_FF_DEPTH = 9, @@ -109,6 +95,8 @@ ); wire [31:0] debug_rx; + wire [31:0] debug_tx0; + wire [31:0] debug_tx1; //------------------------------------------------------------------------- // Local declarations @@ -302,7 +290,9 @@ .xoff_gen ( xoff_gen ), .xon_gen ( xon_gen ), .xoff_gen_complete ( xoff_gen_complete ), - .xon_gen_complete ( xon_gen_complete ) + .xon_gen_complete ( xon_gen_complete ), + .debug0(debug_tx0), + .debug1(debug_tx1) ); // Flow control outbound -- when other side sends PAUSE, we wait @@ -505,8 +495,9 @@ .UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg ) ); - assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete}, - {1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]}, - {rx_fifo_space}}; - assign debug1 = 32'd0; + //assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete}, +// {1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]}, + // {rx_fifo_space}}; + assign debug0 = debug_tx0; + assign debug1 = debug_tx1; endmodule Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v =================================================================== --- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-02-14 18:37:51 UTC (rev 7677) +++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-02-14 18:40:52 UTC (rev 7678) @@ -35,32 +35,7 @@ //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: MAC_tx_FF.v,v $ -// Revision 1.5 2006/06/25 04:58:56 maverickist -// no message -// -// Revision 1.4 2006/05/28 05:09:20 maverickist -// no message -// -// Revision 1.3 2006/01/19 14:07:54 maverickist -// verification is complete. -// -// Revision 1.3 2005/12/16 06:44:18 Administrator -// replaced tab with space. -// passed 9.6k length frame test. -// -// Revision 1.2 2005/12/13 12:15:39 Administrator -// no message -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -`include "header.vh" - module MAC_tx_FF #(parameter TX_FF_DEPTH = 9) (input Reset , @@ -86,8 +61,11 @@ //host interface input FullDuplex , input [4:0] Tx_Hwmark , - input [4:0] Tx_Lwmark ); - + input [4:0] Tx_Lwmark , + output [31:0] debug0, + output [31:0] debug1 + ); + //****************************************************************************** //internal signals //****************************************************************************** @@ -714,5 +692,17 @@ ram_2port #(.DWIDTH(36),.AWIDTH(TX_FF_DEPTH)) mac_tx_ff_ram (.clka(Clk_SYS),.ena(1'b1),.wea(Wr_en),.addra(Add_wr),.dia(Din),.doa(), .clkb(Clk_MAC),.enb(1'b1),.web(1'b0),.addrb(Add_rd),.dib(36'b0),.dob(Dout) ); + + assign debug0 = + { { 5'd0, Empty, Full, AlmostFull }, + { Current_state_SYS, Current_state_MAC }, + { Fifo_rd, Fifo_rd_finish, Fifo_rd_retry, Fifo_eop, Fifo_da, Fifo_ra, Fifo_data_err_empty, Fifo_data_err_full }, + { 2'b0, Dout_BE, Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop} }; + + assign debug1 = + { { 8'd0 }, + { 8'd0 }, + { 8'd0 }, + { 8'd0 } }; endmodule // MAC_tx_FF Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v =================================================================== --- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v 2008-02-14 18:37:51 UTC (rev 7677) +++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v 2008-02-14 18:40:52 UTC (rev 7678) @@ -1,6 +1,6 @@ ////////////////////////////////////////////////////////////////////// //// //// -//// Randon_gen.v //// +//// Random_gen.v //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// @@ -35,22 +35,8 @@ //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: Randon_gen.v,v $ -// Revision 1.3 2006/01/19 14:07:54 maverickist -// verification is complete. -// -// Revision 1.2 2005/12/16 06:44:19 Administrator -// replaced tab with space. -// passed 9.6k length frame test. -// -// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator -// no message -// -module Randon_gen( +module Random_gen( Reset , Clk , Init , Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v =================================================================== --- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v 2008-02-14 18:37:51 UTC (rev 7677) +++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v 2008-02-14 18:40:52 UTC (rev 7678) @@ -92,7 +92,9 @@ input xoff_gen, input xon_gen, output xoff_gen_complete, -output xon_gen_complete +output xon_gen_complete, + output [31:0] debug0, + output [31:0] debug1 ); // ****************************************************************************** @@ -105,7 +107,7 @@ wire CRC_rd ; wire CRC_end ; wire[7:0] CRC_out ; - //Ramdon_gen interface + //Random_gen interface wire Random_init ; wire[3:0] RetryCnt ; wire Random_time_meet ;//levle hight indicate random time passed away @@ -138,7 +140,7 @@ .CRC_rd (CRC_rd ), .CRC_end (CRC_end ), .CRC_out (CRC_out ), - //Ramdon_gen interfac (//Ramdon_gen interfac ), + //Random_gen interfac (//Random_gen interfac ), .Random_init (Random_init ), .RetryCnt (RetryCnt ), .Random_time_meet (Random_time_meet ), @@ -227,10 +229,12 @@ //host interface (//host interface ), .FullDuplex (FullDuplex ), .Tx_Hwmark (Tx_Hwmark ), -.Tx_Lwmark (Tx_Lwmark ) +.Tx_Lwmark (Tx_Lwmark ), +.debug0(debug0), +.debug1(debug1) ); -Ramdon_gen U_Ramdon_gen( +Random_gen U_Random_gen( .Reset (Reset ), .Clk (Clk ), .Init (Random_init ), _______________________________________________ Commit-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/commit-gnuradio
