Hello community,
here is the log from the commit of package gcc7 for openSUSE:Factory checked in
at 2020-12-05 20:35:58
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/gcc7 (Old)
and /work/SRC/openSUSE:Factory/.gcc7.new.5913 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "gcc7"
Sat Dec 5 20:35:58 2020 rev:31 rq:852639 version:7.5.0+r278197
Changes:
--------
--- /work/SRC/openSUSE:Factory/gcc7/cross-aarch64-gcc7.changes 2020-11-23
18:42:59.304902072 +0100
+++ /work/SRC/openSUSE:Factory/.gcc7.new.5913/cross-aarch64-gcc7.changes
2020-12-05 20:36:28.798665997 +0100
@@ -1,0 +2,27 @@
+Thu Nov 26 17:17:44 UTC 2020 - Michael Matz <m...@suse.com>
+
+- Add gcc7-aarch64-sls-miti-1.patch, gcc7-aarch64-sls-miti-2.patch,
+ gcc7-aarch64-sls-miti-3.patch to backport aarch64 Straight Line
+ Speculation mitigation [bsc#1172798, CVE-2020-13844]
+- Add gcc7-fix-retrieval-of-testnames.patch to support usage in
+ testcases added by the above.
+
+-------------------------------------------------------------------
+Thu Nov 26 15:06:50 UTC 2020 - Richard Biener <rguent...@suse.com>
+
+- Enable fortran for the nvptx offload compiler.
+- Do not specify alternate offload compiler location at
+ configure time.
+- Update README.First-for.SuSE.packagers
+
+-------------------------------------------------------------------
+Thu Nov 26 07:58:17 UTC 2020 - Richard Biener <rguent...@suse.com>
+
+- Add gcc7-pr88522.patch to avoid assembler errors with AVX512
+ gather and scatter instructions when using -masm=intel.
+- Amend gcc7-remove-Wexpansion-to-defined-from-Wextra.patch to
+ reflect changes in option handling in the testsuite.
+- Add gcc7-testsuite-fixes.patch to fix PR98001 and PR98002 which
+ are broken testcases showing with malloc debugging enabled.
+
+-------------------------------------------------------------------
@@ -6 +33 @@
- default enabling. [jsc#SLE-12209]
+ default enabling. [jsc#SLE-12209, bsc#1167939]
cross-arm-gcc7.changes: same change
cross-arm-none-gcc7-bootstrap.changes: same change
cross-arm-none-gcc7.changes: same change
cross-avr-gcc7-bootstrap.changes: same change
cross-avr-gcc7.changes: same change
cross-epiphany-gcc7-bootstrap.changes: same change
cross-epiphany-gcc7.changes: same change
cross-hppa-gcc7.changes: same change
cross-i386-gcc7.changes: same change
cross-m68k-gcc7.changes: same change
cross-mips-gcc7.changes: same change
cross-nvptx-gcc7.changes: same change
cross-ppc64-gcc7.changes: same change
cross-ppc64le-gcc7.changes: same change
cross-rx-gcc7-bootstrap.changes: same change
cross-rx-gcc7.changes: same change
cross-s390x-gcc7.changes: same change
cross-sparc-gcc7.changes: same change
cross-sparc64-gcc7.changes: same change
cross-x86_64-gcc7.changes: same change
gcc7-testresults.changes: same change
gcc7.changes: same change
New:
----
gcc7-aarch64-sls-miti-1.patch
gcc7-aarch64-sls-miti-2.patch
gcc7-aarch64-sls-miti-3.patch
gcc7-fix-retrieval-of-testnames.patch
gcc7-pr88522.patch
gcc7-testsuite-fixes.patch
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ cross-aarch64-gcc7.spec ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:38.282675622 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:38.282675622 +0100
@@ -36,7 +36,7 @@
%define build_libjava 0
%define build_java 0
-%define build_fortran 0
+%define build_fortran 0%{?gcc_accel:1}
%define build_objc 0
%define build_objcp 0
%define build_go 0
@@ -135,6 +135,8 @@
Patch26: gcc7-pr93888.patch
Patch27: gcc7-pr94148.patch
Patch29: gcc7-pr97535.patch
+Patch30: gcc7-pr88522.patch
+Patch31: gcc7-testsuite-fixes.patch
# A set of patches from the RH srpm
Patch51: gcc41-ppc32-retaddr.patch
# Some patches taken from Debian
@@ -142,6 +144,10 @@
Patch61: gcc44-rename-info-files.patch
# Feature backports
Patch100: gcc7-aarch64-moutline-atomics.patch
+Patch101: gcc7-fix-retrieval-of-testnames.patch
+Patch102: gcc7-aarch64-sls-miti-1.patch
+Patch103: gcc7-aarch64-sls-miti-2.patch
+Patch104: gcc7-aarch64-sls-miti-3.patch
# Define the canonical target and host architecture
# %%gcc_target_arch is supposed to be the full target triple
@@ -292,11 +298,17 @@
%patch26 -p1
%patch27 -p1
%patch29
+%patch30 -p1
+%patch31 -p1
%patch51
%patch60
%patch61
%patch100 -p1
%patch23 -p1
+%patch101 -p1
+%patch102 -p1
+%patch103 -p1
+%patch104 -p1
#test patching end
@@ -399,7 +411,7 @@
hsa,\
%endif
%if %{build_nvptx}
-nvptx-none=%{_prefix}/nvptx-none, \
+nvptx-none, \
%endif
%endif
%if %{build_nvptx}
cross-arm-gcc7.spec: same change
cross-arm-none-gcc7-bootstrap.spec: same change
cross-arm-none-gcc7.spec: same change
cross-avr-gcc7-bootstrap.spec: same change
cross-avr-gcc7.spec: same change
cross-epiphany-gcc7-bootstrap.spec: same change
cross-epiphany-gcc7.spec: same change
cross-hppa-gcc7.spec: same change
cross-i386-gcc7.spec: same change
cross-m68k-gcc7.spec: same change
cross-mips-gcc7.spec: same change
cross-nvptx-gcc7.spec: same change
cross-ppc64-gcc7.spec: same change
cross-ppc64le-gcc7.spec: same change
cross-rx-gcc7-bootstrap.spec: same change
cross-rx-gcc7.spec: same change
cross-s390x-gcc7.spec: same change
cross-sparc-gcc7.spec: same change
cross-sparc64-gcc7.spec: same change
cross-x86_64-gcc7.spec: same change
++++++ gcc7-testresults.spec ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:38.894676244 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:38.898676247 +0100
@@ -218,6 +218,10 @@
BuildRequires: dejagnu
BuildRequires: expect
BuildRequires: gdb
+%if %{build_nvptx}
+BuildRequires: cross-nvptx-gcc7
+BuildRequires: cross-nvptx-newlib7-devel
+%endif
%endif
#!BuildIgnore: gcc-PIE
@@ -328,6 +332,8 @@
Patch26: gcc7-pr93888.patch
Patch27: gcc7-pr94148.patch
Patch29: gcc7-pr97535.patch
+Patch30: gcc7-pr88522.patch
+Patch31: gcc7-testsuite-fixes.patch
# A set of patches from the RH srpm
Patch51: gcc41-ppc32-retaddr.patch
# Some patches taken from Debian
@@ -335,6 +341,10 @@
Patch61: gcc44-rename-info-files.patch
# Feature backports
Patch100: gcc7-aarch64-moutline-atomics.patch
+Patch101: gcc7-fix-retrieval-of-testnames.patch
+Patch102: gcc7-aarch64-sls-miti-1.patch
+Patch103: gcc7-aarch64-sls-miti-2.patch
+Patch104: gcc7-aarch64-sls-miti-3.patch
Summary: Testsuite results
License: SUSE-Public-Domain
@@ -469,11 +479,17 @@
%patch26 -p1
%patch27 -p1
%patch29
+%patch30 -p1
+%patch31 -p1
%patch51
%patch60
%patch61
%patch100 -p1
%patch23 -p1
+%patch101 -p1
+%patch102 -p1
+%patch103 -p1
+%patch104 -p1
#test patching end
@@ -576,7 +592,7 @@
hsa,\
%endif
%if %{build_nvptx}
-nvptx-none=%{_prefix}/nvptx-none, \
+nvptx-none, \
%endif
%endif
%if %{build_nvptx}
++++++ gcc7.spec ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:38.918676268 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:38.918676268 +0100
@@ -200,6 +200,10 @@
BuildRequires: dejagnu
BuildRequires: expect
BuildRequires: gdb
+%if %{build_nvptx}
+BuildRequires: cross-nvptx-gcc7
+BuildRequires: cross-nvptx-newlib7-devel
+%endif
%endif
#!BuildIgnore: gcc-PIE
@@ -310,6 +314,8 @@
Patch26: gcc7-pr93888.patch
Patch27: gcc7-pr94148.patch
Patch29: gcc7-pr97535.patch
+Patch30: gcc7-pr88522.patch
+Patch31: gcc7-testsuite-fixes.patch
# A set of patches from the RH srpm
Patch51: gcc41-ppc32-retaddr.patch
# Some patches taken from Debian
@@ -317,6 +323,10 @@
Patch61: gcc44-rename-info-files.patch
# Feature backports
Patch100: gcc7-aarch64-moutline-atomics.patch
+Patch101: gcc7-fix-retrieval-of-testnames.patch
+Patch102: gcc7-aarch64-sls-miti-1.patch
+Patch103: gcc7-aarch64-sls-miti-2.patch
+Patch104: gcc7-aarch64-sls-miti-3.patch
Summary: The GNU C Compiler and Support Files
License: GPL-3.0-or-later
@@ -1773,11 +1783,17 @@
%patch26 -p1
%patch27 -p1
%patch29
+%patch30 -p1
+%patch31 -p1
%patch51
%patch60
%patch61
%patch100 -p1
%patch23 -p1
+%patch101 -p1
+%patch102 -p1
+%patch103 -p1
+%patch104 -p1
#test patching end
@@ -1880,7 +1896,7 @@
hsa,\
%endif
%if %{build_nvptx}
-nvptx-none=%{_prefix}/nvptx-none, \
+nvptx-none, \
%endif
%endif
%if %{build_nvptx}
++++++ README.First-for.SuSE.packagers ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:38.954676305 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:38.958676308 +0100
@@ -1,29 +1,35 @@
-IMPORTANT: Please change gcc.spec.in and then run ./pre_checkin.sh!
-Do not change gcc.spec directly!
+IMPORTANT: Please change gcc.spec.in or cross.spec.in and then
+run ./pre_checkin.sh! Do not change any .spec directly!
Since GCC comes with a testsuite that runs for quite a long time and
that test suite also contains some known failures, we should run the
testsuite of GCC whenever the compiler is changed to ensure a high
quality compiler.
-The package is now split into multiple parts, gcc$VER,
-gcc$VER-testresults and libffi$VER (plus various spec files for
-cross and icecream cross compilers). The testsuite is run from
-gcc$VER-testresults, a dummy package with the testresults, gcc$VER-testresults,
-is generated from it which contains testing logfiles and summary.
+The package is now split into two parts, gcc$VER and gcc$VER-testresults
+(plus various spec files for cross and offload). The testsuite is run from
+gcc$VER-testresults.spec, a dummy source package with the actual testresults,
+gcc$VER-testresults, generated from it which contains testing logfiles and
+a summary.
Before checking in a new compiler, please do the following steps as QA
measure to check that the new compiler does not introduce any new
failures:
-- Run mbuild for all archs for at least the gcc$VER and the gcc$VER-testresults
- subpackages
+- In your branch project make sure at least gcc$VER and gcc$VER-testresults
+ are built for all relevant architectures of the product
-- When mbuild is finished, call
- /suse/rguenther/bin/compare-testresults.sh mbuild-directory
- (for the gcc$VER-testresults build).
- The output of that script should not show any failures. If it does,
- please fix them or discuss this with the gcc package maintainers.
+- When the build finished, call
+ /suse/rguenther/bin/compare-testresults-bs.sh \
+ gcc$VER-testresults gcc$VER-testresults \
+ SUSE:SLE-15:Update standard .1234 \
+ home:user:branches:gcc standard
+ It will compare testresults of the base (shipped in the product already,
+ look for the magic .1234 suffix as to the latest released update) to
+ your proposed update. The differences will be recorded in a temporary
+ directory which is printed as output, they should not contain any new
+ failures. If they do, please fix them or discuss this with the gcc
+ package maintainers.
- Do not remove this file.
++++++ cross.spec.in ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:39.058676410 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:39.058676410 +0100
@@ -15,7 +15,7 @@
%define build_libjava 0
%define build_java 0
-%define build_fortran 0
+%define build_fortran 0%{?gcc_accel:1}
%define build_objc 0
%define build_objcp 0
%define build_go 0
++++++ gcc.spec.in ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:39.094676446 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:39.094676446 +0100
@@ -203,6 +203,10 @@
BuildRequires: dejagnu
BuildRequires: expect
BuildRequires: gdb
+%if %{build_nvptx}
+BuildRequires: cross-nvptx-gcc@base_ver@
+BuildRequires: cross-nvptx-newlib@base_ver@-devel
+%endif
%endif
#!BuildIgnore: gcc-PIE
@@ -316,6 +320,8 @@
Patch26: gcc7-pr93888.patch
Patch27: gcc7-pr94148.patch
Patch29: gcc7-pr97535.patch
+Patch30: gcc7-pr88522.patch
+Patch31: gcc7-testsuite-fixes.patch
# A set of patches from the RH srpm
Patch51: gcc41-ppc32-retaddr.patch
# Some patches taken from Debian
@@ -323,6 +329,10 @@
Patch61: gcc44-rename-info-files.patch
# Feature backports
Patch100: gcc7-aarch64-moutline-atomics.patch
+Patch101: gcc7-fix-retrieval-of-testnames.patch
+Patch102: gcc7-aarch64-sls-miti-1.patch
+Patch103: gcc7-aarch64-sls-miti-2.patch
+Patch104: gcc7-aarch64-sls-miti-3.patch
# GCC-TESTSUITE-DELETE-BEGIN
@@ -1083,11 +1093,17 @@
%patch26 -p1
%patch27 -p1
%patch29
+%patch30 -p1
+%patch31 -p1
%patch51
%patch60
%patch61
%patch100 -p1
%patch23 -p1
+%patch101 -p1
+%patch102 -p1
+%patch103 -p1
+%patch104 -p1
#test patching end
@@ -1190,7 +1206,7 @@
hsa,\
%endif
%if %{build_nvptx}
-nvptx-none=%{_prefix}/nvptx-none, \
+nvptx-none, \
%endif
%endif
%if %{build_nvptx}
++++++ gcc7-aarch64-sls-miti-1.patch ++++++
Backport to gcc7 of the below commit for bsc#1172798
commit 20da13e395bde597d8337167c712039c8f923c3b
Author: Matthew Malcomson <matthew.malcom...@arm.com>
Date: Thu Jul 9 09:11:58 2020 +0100
aarch64: New Straight Line Speculation (SLS) mitigation flags
Here we introduce the flags that will be used for straight line speculation.
The new flag introduced is `-mharden-sls=`.
This flag can take arguments of `none`, `all`, or a comma seperated list
of one or more of `retbr` or `blr`.
`none` indicates no special mitigation of the straight line speculation
vulnerability.
`all` requests all mitigations currently implemented.
`retbr` requests that the RET and BR instructions have a speculation
barrier inserted after them.
`blr` requests that BLR instructions are replaced by a BL to a function
stub using a BR with a speculation barrier after it.
Setting this on a per-function basis using attributes or the like is not
enabled, but may be in the future.
(cherry picked from commit a9ba2a9b77bec7eacaf066801f22d1c366a2bc86)
gcc/ChangeLog:
2020-06-02 Matthew Malcomson <matthew.malcom...@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_harden_sls_retbr_p):
New.
(aarch64_harden_sls_blr_p): New.
* config/aarch64/aarch64.c (enum aarch64_sls_hardening_type):
New.
(aarch64_harden_sls_retbr_p): New.
(aarch64_harden_sls_blr_p): New.
(aarch64_validate_sls_mitigation): New.
(aarch64_override_options): Parse options for SLS mitigation.
* config/aarch64/aarch64.opt (-mharden-sls): New option.
* doc/invoke.texi: Document new option.
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64-protos.h
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64-protos.h
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64-protos.h
@@ -485,4 +485,7 @@ extern const atomic_ool_names aarch64_oo
extern const atomic_ool_names aarch64_ool_ldclr_names;
extern const atomic_ool_names aarch64_ool_ldeor_names;
+extern bool aarch64_harden_sls_retbr_p (void);
+extern bool aarch64_harden_sls_blr_p (void);
+
#endif /* GCC_AARCH64_PROTOS_H */
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.c
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64.c
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.c
@@ -8814,6 +8814,79 @@ aarch64_validate_mcpu (const char *str,
return false;
}
+/* Straight line speculation indicators. */
+enum aarch64_sls_hardening_type
+{
+ SLS_NONE = 0,
+ SLS_RETBR = 1,
+ SLS_BLR = 2,
+ SLS_ALL = 3,
+};
+static enum aarch64_sls_hardening_type aarch64_sls_hardening;
+
+/* Return whether we should mitigatate Straight Line Speculation for the RET
+ and BR instructions. */
+bool
+aarch64_harden_sls_retbr_p (void)
+{
+ return aarch64_sls_hardening & SLS_RETBR;
+}
+
+/* Return whether we should mitigatate Straight Line Speculation for the BLR
+ instruction. */
+bool
+aarch64_harden_sls_blr_p (void)
+{
+ return aarch64_sls_hardening & SLS_BLR;
+}
+
+/* As of yet we only allow setting these options globally, in the future we may
+ allow setting them per function. */
+static void
+aarch64_validate_sls_mitigation (const char *const_str)
+{
+ char *token_save = NULL;
+ char *str = NULL;
+
+ if (strcmp (const_str, "none") == 0)
+ {
+ aarch64_sls_hardening = SLS_NONE;
+ return;
+ }
+ if (strcmp (const_str, "all") == 0)
+ {
+ aarch64_sls_hardening = SLS_ALL;
+ return;
+ }
+
+ char *str_root = xstrdup (const_str);
+ str = strtok_r (str_root, ",", &token_save);
+ if (!str)
+ error ("invalid argument given to %<-mharden-sls=%>");
+
+ int temp = SLS_NONE;
+ while (str)
+ {
+ if (strcmp (str, "blr") == 0)
+ temp |= SLS_BLR;
+ else if (strcmp (str, "retbr") == 0)
+ temp |= SLS_RETBR;
+ else if (strcmp (str, "none") == 0 || strcmp (str, "all") == 0)
+ {
+ error ("%<%s%> must be by itself for %<-mharden-sls=%>", str);
+ break;
+ }
+ else
+ {
+ error ("invalid argument %<%s%> for %<-mharden-sls=%>", str);
+ break;
+ }
+ str = strtok_r (NULL, ",", &token_save);
+ }
+ aarch64_sls_hardening = (aarch64_sls_hardening_type) temp;
+ free (str_root);
+}
+
/* Validate a command-line -march option. Parse the arch and extensions
(if any) specified in STR and throw errors if appropriate. Put the
results, if they are valid, in RES and ISA_FLAGS. Return whether the
@@ -8930,6 +9003,9 @@ aarch64_override_options (void)
selected_arch = NULL;
selected_tune = NULL;
+ if (aarch64_harden_sls_string)
+ aarch64_validate_sls_mitigation (aarch64_harden_sls_string);
+
/* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
If either of -march or -mtune is given, they override their
respective component of -mcpu. */
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.opt
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64.opt
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.opt
@@ -68,6 +68,10 @@ mgeneral-regs-only
Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save
Generate code which uses only the general registers.
+mharden-sls=
+Target RejectNegative Joined Var(aarch64_harden_sls_string)
+Generate code to mitigate against straight line speculation.
+
mfix-cortex-a53-835769
Target Report Var(aarch64_fix_a53_err835769) Init(2) Save
Workaround for ARM Cortex-A53 Erratum number 835769.
Index: gcc-7.5.0+r278197/gcc/doc/invoke.texi
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/doc/invoke.texi
+++ gcc-7.5.0+r278197/gcc/doc/invoke.texi
@@ -589,6 +589,7 @@ Objective-C and Objective-C++ Dialects}.
-mlow-precision-recip-sqrt -mno-low-precision-recip-sqrt@gol
-mlow-precision-sqrt -mno-low-precision-sqrt@gol
-mlow-precision-div -mno-low-precision-div @gol
+-mharden-sls=@var{opts} @gol
-march=@var{name} -mcpu=@var{name} -mtune=@var{name}}
@emph{Adapteva Epiphany Options}
@@ -14143,6 +14144,17 @@ Permissible values are @samp{none}, whic
functions, and @samp{all}, which enables pointer signing for all functions.
The
default value is @samp{none}.
+@item -mharden-sls=@var{opts}
+@opindex mharden-sls
+Enable compiler hardening against straight line speculation (SLS).
+@var{opts} is a comma-separated list of the following options:
+@table @samp
+@item retbr
+@item blr
+@end table
+In addition, @samp{-mharden-sls=all} enables all SLS hardening while
+@samp{-mharden-sls=none} disables all SLS hardening.
+
@end table
@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
++++++ gcc7-aarch64-sls-miti-2.patch ++++++
++++ 606 lines (skipped)
++++++ gcc7-aarch64-sls-miti-3.patch ++++++
Backport of below commit for bsc#1172798
commit 2155170525f93093b90a1a065e7ed71a925566e9
Author: Matthew Malcomson <matthew.malcom...@arm.com>
Date: Thu Jul 9 09:11:59 2020 +0100
aarch64: Mitigate SLS for BLR instruction
This patch introduces the mitigation for Straight Line Speculation past
the BLR instruction.
This mitigation replaces BLR instructions with a BL to a stub which uses
a BR to jump to the original value. These function stubs are then
appended with a speculation barrier to ensure no straight line
speculation happens after these jumps.
When optimising for speed we use a set of stubs for each function since
this should help the branch predictor make more accurate predictions
about where a stub should branch.
When optimising for size we use one set of stubs for all functions.
This set of stubs can have human readable names, and we are using
`__call_indirect_x<N>` for register x<N>.
When BTI branch protection is enabled the BLR instruction can jump to a
`BTI c` instruction using any register, while the BR instruction can
only jump to a `BTI c` instruction using the x16 or x17 registers.
Hence, in order to ensure this transformation is safe we mov the value
of the original register into x16 and use x16 for the BR.
As an example when optimising for size:
a
BLR x0
instruction would get transformed to something like
BL __call_indirect_x0
where __call_indirect_x0 labels a thunk that contains
__call_indirect_x0:
MOV X16, X0
BR X16
<speculation barrier>
The first version of this patch used local symbols specific to a
compilation unit to try and avoid relocations.
This was mistaken since functions coming from the same compilation unit
can still be in different sections, and the assembler will insert
relocations at jumps between sections.
On any relocation the linker is permitted to emit a veneer to handle
jumps between symbols that are very far apart. The registers x16 and
x17 may be clobbered by these veneers.
Hence the function stubs cannot rely on the values of x16 and x17 being
the same as just before the function stub is called.
Similar can be said for the hot/cold partitioning of single functions,
so function-local stubs have the same restriction.
This updated version of the patch never emits function stubs for x16 and
x17, and instead forces other registers to be used.
Given the above, there is now no benefit to local symbols (since they
are not enough to avoid dealing with linker intricacies). This patch
now uses global symbols with hidden visibility each stored in their own
COMDAT section. This means stubs can be shared between compilation
units while still avoiding the PLT indirection.
This patch also removes the `__call_indirect_x30` stub (and
function-local equivalent) which would simply jump back to the original
location.
The function-local stubs are emitted to the assembly output file in one
chunk, which means we need not add the speculation barrier directly
after each one.
This is because we know for certain that the instructions directly after
the BR in all but the last function stub will be from another one of
these stubs and hence will not contain a speculation gadget.
Instead we add a speculation barrier at the end of the sequence of
stubs.
The global stubs are emitted in COMDAT/.linkonce sections by
themselves so that the linker can remove duplicates from multiple object
files. This means they are not emitted in one chunk, and each one must
include the speculation barrier.
Another difference is that since the global stubs are shared across
compilation units we do not know that all functions will be targeting an
architecture supporting the SB instruction.
Rather than provide multiple stubs for each architecture, we provide a
stub that will work for all architectures -- using the DSB+ISB barrier.
This mitigation does not apply for BLR instructions in the following
places:
- Some accesses to thread-local variables use a code sequence with a BLR
instruction. This code sequence is part of the binary interface between
compiler and linker. If this BLR instruction needs to be mitigated, it'd
probably be best to do so in the linker. It seems that the code sequence
for thread-local variable access is unlikely to lead to a Spectre
Revalation
Gadget.
- PLT stubs are produced by the linker and each contain a BLR instruction.
It seems that at most only after the last PLT stub a Spectre Revalation
Gadget might appear.
Testing:
Bootstrap and regtest on AArch64
(with BOOT_CFLAGS="-mharden-sls=retbr,blr")
Used a temporary hack(1) in gcc-dg.exp to use these options on every
test in the testsuite, a slight modification to emit the speculation
barrier after every function stub, and a script to check that the
output never emitted a BLR, or unmitigated BR or RET instruction.
Similar on an aarch64-none-elf cross-compiler.
1) Temporary hack emitted a speculation barrier at the end of every stub
function, and used a script to ensure that:
a) Every RET or BR is immediately followed by a speculation barrier.
b) No BLR instruction is emitted by compiler.
(cherry picked from 96b7f495f9269d5448822e4fc28882edb35a58d7)
gcc/ChangeLog:
* config/aarch64/aarch64-protos.h (aarch64_indirect_call_asm):
New declaration.
* config/aarch64/aarch64.c (aarch64_regno_regclass): Handle new
stub registers class.
(aarch64_class_max_nregs): Likewise.
(aarch64_register_move_cost): Likewise.
(aarch64_sls_shared_thunks): Global array to store stub labels.
(aarch64_sls_emit_function_stub): New.
(aarch64_create_blr_label): New.
(aarch64_sls_emit_blr_function_thunks): New.
(aarch64_sls_emit_shared_blr_thunks): New.
(aarch64_asm_file_end): New.
(aarch64_indirect_call_asm): New.
(TARGET_ASM_FILE_END): Use aarch64_asm_file_end.
(TARGET_ASM_FUNCTION_EPILOGUE): Use
aarch64_sls_emit_blr_function_thunks.
* config/aarch64/aarch64.h (STB_REGNUM_P): New.
(enum reg_class): Add STUB_REGS class.
(machine_function): Introduce `call_via` array for
function-local stub labels.
* config/aarch64/aarch64.md (*call_insn, *call_value_insn): Use
aarch64_indirect_call_asm to emit code when hardening BLR
instructions.
* config/aarch64/constraints.md (Ucr): New constraint
representing registers for indirect calls. Is GENERAL_REGS
usually, and STUB_REGS when hardening BLR instruction against
SLS.
* config/aarch64/predicates.md (aarch64_general_reg): STUB_REGS
class
is also a general register.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sls-mitigation/sls-miti-blr-bti.c: New test.
* gcc.target/aarch64/sls-mitigation/sls-miti-blr.c: New test.
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64-protos.h
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64-protos.h
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64-protos.h
@@ -486,6 +486,7 @@ extern const atomic_ool_names aarch64_oo
extern const atomic_ool_names aarch64_ool_ldeor_names;
const char *aarch64_sls_barrier (int);
+const char *aarch64_indirect_call_asm (rtx);
extern bool aarch64_harden_sls_retbr_p (void);
extern bool aarch64_harden_sls_blr_p (void);
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.c
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64.c
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.c
@@ -5471,6 +5471,9 @@ aarch64_label_mentioned_p (rtx x)
enum reg_class
aarch64_regno_regclass (unsigned regno)
{
+ if (STUB_REGNUM_P (regno))
+ return STUB_REGS;
+
if (GP_REGNUM_P (regno))
return GENERAL_REGS;
@@ -5799,6 +5802,7 @@ aarch64_class_max_nregs (reg_class_t reg
{
switch (regclass)
{
+ case STUB_REGS:
case TAILCALL_ADDR_REGS:
case POINTER_REGS:
case GENERAL_REGS:
@@ -7880,10 +7884,12 @@ aarch64_register_move_cost (machine_mode
= aarch64_tune_params.regmove_cost;
/* Caller save and pointer regs are equivalent to GENERAL_REGS. */
- if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS)
+ if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS
+ || to == STUB_REGS)
to = GENERAL_REGS;
- if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS)
+ if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS
+ || from == STUB_REGS)
from = GENERAL_REGS;
/* Moving between GPR and stack cost is the same as GP2GP. */
@@ -14699,6 +14705,215 @@ aarch64_sls_barrier (int mitigation_requ
: "";
}
+static GTY (()) tree aarch64_sls_shared_thunks[30];
+static GTY (()) bool aarch64_sls_shared_thunks_needed = false;
+const char *indirect_symbol_names[30] = {
+ "__call_indirect_x0",
+ "__call_indirect_x1",
+ "__call_indirect_x2",
+ "__call_indirect_x3",
+ "__call_indirect_x4",
+ "__call_indirect_x5",
+ "__call_indirect_x6",
+ "__call_indirect_x7",
+ "__call_indirect_x8",
+ "__call_indirect_x9",
+ "__call_indirect_x10",
+ "__call_indirect_x11",
+ "__call_indirect_x12",
+ "__call_indirect_x13",
+ "__call_indirect_x14",
+ "__call_indirect_x15",
+ "", /* "__call_indirect_x16", */
+ "", /* "__call_indirect_x17", */
+ "__call_indirect_x18",
+ "__call_indirect_x19",
+ "__call_indirect_x20",
+ "__call_indirect_x21",
+ "__call_indirect_x22",
+ "__call_indirect_x23",
+ "__call_indirect_x24",
+ "__call_indirect_x25",
+ "__call_indirect_x26",
+ "__call_indirect_x27",
+ "__call_indirect_x28",
+ "__call_indirect_x29",
+};
+
+/* Function to create a BLR thunk. This thunk is used to mitigate straight
+ line speculation. Instead of a simple BLR that can be speculated past,
+ we emit a BL to this thunk, and this thunk contains a BR to the relevant
+ register. These thunks have the relevant speculation barries put after
+ their indirect branch so that speculation is blocked.
+
+ We use such a thunk so the speculation barriers are kept off the
+ architecturally executed path in order to reduce the performance overhead.
+
+ When optimizing for size we use stubs shared by the linked object.
+ When optimizing for performance we emit stubs for each function in the hope
+ that the branch predictor can better train on jumps specific for a given
+ function. */
+rtx
+aarch64_sls_create_blr_label (int regnum)
+{
+ gcc_assert (STUB_REGNUM_P (regnum));
+ if (optimize_function_for_size_p (cfun))
+ {
+ /* For the thunks shared between different functions in this compilation
+ unit we use a named symbol -- this is just for users to more easily
+ understand the generated assembly. */
+ aarch64_sls_shared_thunks_needed = true;
+ const char *thunk_name = indirect_symbol_names[regnum];
+ if (aarch64_sls_shared_thunks[regnum] == NULL)
+ {
+ /* Build a decl representing this function stub and record it for
+ later. We build a decl here so we can use the GCC machinery for
+ handling sections automatically (through `get_named_section` and
+ `make_decl_one_only`). That saves us a lot of trouble handling
+ the specifics of different output file formats. */
+ tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
+ get_identifier (thunk_name),
+ build_function_type_list (void_type_node,
+ NULL_TREE));
+ DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
+ NULL_TREE, void_type_node);
+ TREE_PUBLIC (decl) = 1;
+ TREE_STATIC (decl) = 1;
+ DECL_IGNORED_P (decl) = 1;
+ DECL_ARTIFICIAL (decl) = 1;
+ make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
+ resolve_unique_section (decl, 0, false);
+ aarch64_sls_shared_thunks[regnum] = decl;
+ }
+
+ return gen_rtx_SYMBOL_REF (Pmode, thunk_name);
+ }
+
+ if (cfun->machine->call_via[regnum] == NULL)
+ cfun->machine->call_via[regnum]
+ = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
+ return cfun->machine->call_via[regnum];
+}
+
+/* Helper function for aarch64_sls_emit_blr_function_thunks and
+ aarch64_sls_emit_shared_blr_thunks below. */
+static void
+aarch64_sls_emit_function_stub (FILE *out_file, int regnum)
+{
+ /* Save in x16 and branch to that function so this transformation does
+ not prevent jumping to `BTI c` instructions. */
+ asm_fprintf (out_file, "\tmov\tx16, x%d\n", regnum);
+ asm_fprintf (out_file, "\tbr\tx16\n");
+}
+
+/* Emit all BLR stubs for this particular function.
+ Here we emit all the BLR stubs needed for the current function. Since we
+ emit these stubs in a consecutive block we know there will be no speculation
+ gadgets between each stub, and hence we only emit a speculation barrier at
+ the end of the stub sequences.
+
+ This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook. */
+void
+aarch64_sls_emit_blr_function_thunks (FILE *out_file, HOST_WIDE_INT)
+{
+ if (! aarch64_harden_sls_blr_p ())
+ return;
+
+ bool any_functions_emitted = false;
+ /* We must save and restore the current function section since this assembly
+ is emitted at the end of the function. This means it can be emitted *just
+ after* the cold section of a function. That cold part would be emitted in
+ a different section. That switch would trigger a `.cfi_endproc` directive
+ to be emitted in the original section and a `.cfi_startproc` directive to
+ be emitted in the new section. Switching to the original section without
+ restoring would mean that the `.cfi_endproc` emitted as a function ends
+ would happen in a different section -- leaving an unmatched
+ `.cfi_startproc` in the cold text section and an unmatched `.cfi_endproc`
+ in the standard text section. */
+ section *save_text_section = in_section;
+ switch_to_section (function_section (current_function_decl));
+ for (int regnum = 0; regnum < 30; ++regnum)
+ {
+ rtx specu_label = cfun->machine->call_via[regnum];
+ if (specu_label == NULL)
+ continue;
+
+ targetm.asm_out.print_operand (out_file, specu_label, 0);
+ asm_fprintf (out_file, ":\n");
+ aarch64_sls_emit_function_stub (out_file, regnum);
+ any_functions_emitted = true;
+ }
+ if (any_functions_emitted)
+ /* Can use the SB if needs be here, since this stub will only be used
+ by the current function, and hence for the current target. */
+ asm_fprintf (out_file, "\t%s\n", aarch64_sls_barrier (true));
+ switch_to_section (save_text_section);
+}
+
+/* Emit shared BLR stubs for the current compilation unit.
+ Over the course of compiling this unit we may have converted some BLR
+ instructions to a BL to a shared stub function. This is where we emit those
+ stub functions.
+ This function is for the stubs shared between different functions in this
+ compilation unit. We share when optimizing for size instead of speed.
+
+ This function is called through the TARGET_ASM_FILE_END hook. */
+void
+aarch64_sls_emit_shared_blr_thunks (FILE *out_file)
+{
+ if (! aarch64_sls_shared_thunks_needed)
+ return;
+
+ for (int regnum = 0; regnum < 30; ++regnum)
+ {
+ tree decl = aarch64_sls_shared_thunks[regnum];
+ if (!decl)
+ continue;
+
+ const char *name = indirect_symbol_names[regnum];
+ switch_to_section (get_named_section (decl, NULL, 0));
+ ASM_OUTPUT_ALIGN (out_file, 2);
+ targetm.asm_out.globalize_label (out_file, name);
+ /* Only emits if the compiler is configured for an assembler that can
+ handle visibility directives. */
+ targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
+ ASM_OUTPUT_TYPE_DIRECTIVE (out_file, name, "function");
+ ASM_OUTPUT_LABEL (out_file, name);
+ aarch64_sls_emit_function_stub (out_file, regnum);
+ /* Use the most conservative target to ensure it can always be used by
any
+ function in the translation unit. */
+ asm_fprintf (out_file, "\tdsb\tsy\n\tisb\n");
+ ASM_DECLARE_FUNCTION_SIZE (out_file, name, decl);
+ }
+}
+
+/* Implement TARGET_ASM_FILE_END. */
+void
+aarch64_asm_file_end ()
+{
+ aarch64_sls_emit_shared_blr_thunks (asm_out_file);
+ /* Since this function will be called for the ASM_FILE_END hook, we ensure
+ that what would be called otherwise (e.g. `file_end_indicate_exec_stack`
+ for FreeBSD) still gets called. */
+#ifdef TARGET_ASM_FILE_END
+ TARGET_ASM_FILE_END ();
+#endif
+}
+
+const char *
+aarch64_indirect_call_asm (rtx addr)
+{
+ gcc_assert (REG_P (addr));
+ if (aarch64_harden_sls_blr_p ())
+ {
+ rtx stub_label = aarch64_sls_create_blr_label (REGNO (addr));
+ output_asm_insn ("bl\t%0", &stub_label);
+ }
+ else
+ output_asm_insn ("blr\t%0", &addr);
+ return "";
+}
+
/* Target-specific selftests. */
#if CHECKING_P
@@ -15132,6 +15347,12 @@ aarch64_libgcc_floating_mode_supported_p
#define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
#endif /* #if CHECKING_P */
+#undef TARGET_ASM_FILE_END
+#define TARGET_ASM_FILE_END aarch64_asm_file_end
+
+#undef TARGET_ASM_FUNCTION_EPILOGUE
+#define TARGET_ASM_FUNCTION_EPILOGUE aarch64_sls_emit_blr_function_thunks
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-aarch64.h"
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.h
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64.h
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.h
@@ -435,6 +435,16 @@ extern unsigned aarch64_architecture_ver
#define GP_REGNUM_P(REGNO) \
(((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
+/* Registers known to be preserved over a BL instruction. This consists of the
+ GENERAL_REGS without x16, x17, and x30. The x30 register is changed by the
+ BL instruction itself, while the x16 and x17 registers may be used by
+ veneers which can be inserted by the linker. */
+#define STUB_REGNUM_P(REGNO) \
+ (GP_REGNUM_P (REGNO) \
+ && (REGNO) != R16_REGNUM \
+ && (REGNO) != R17_REGNUM \
+ && (REGNO) != R30_REGNUM) \
+
#define FP_REGNUM_P(REGNO) \
(((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
@@ -448,6 +458,7 @@ enum reg_class
{
NO_REGS,
TAILCALL_ADDR_REGS,
+ STUB_REGS,
GENERAL_REGS,
STACK_REG,
POINTER_REGS,
@@ -463,6 +474,7 @@ enum reg_class
{ \
"NO_REGS", \
"TAILCALL_ADDR_REGS", \
+ "STUB_REGS", \
"GENERAL_REGS", \
"STACK_REG", \
"POINTER_REGS", \
@@ -475,6 +487,7 @@ enum reg_class
{ \
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
{ 0x0004ffff, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\
+ { 0x3ffcffff, 0x00000000, 0x00000000 }, /* STUB_REGS */ \
{ 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
{ 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
{ 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \
@@ -609,6 +622,8 @@ typedef struct GTY (()) machine_function
struct aarch64_frame frame;
/* One entry for each hard register. */
bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
+ /* One entry for each general purpose register. */
+ rtx call_via[SP_REGNUM];
} machine_function;
#endif
Index: gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.md
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/aarch64.md
+++ gcc-7.5.0+r278197/gcc/config/aarch64/aarch64.md
@@ -778,12 +778,12 @@
)
(define_insn "*call_reg"
- [(call (mem:DI (match_operand:DI 0 "register_operand" "r"))
+ [(call (mem:DI (match_operand:DI 0 "register_operand" "Ucr"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))]
""
- "blr\\t%0"
+ "* return aarch64_indirect_call_asm (operands[0]);"
[(set_attr "type" "call")]
)
@@ -840,12 +840,12 @@
(define_insn "*call_value_reg"
[(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "register_operand" "r"))
+ (call (mem:DI (match_operand:DI 1 "register_operand" "Ucr"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))]
""
- "blr\\t%1"
+ "* return aarch64_indirect_call_asm (operands[1]);"
[(set_attr "type" "call")]
)
Index: gcc-7.5.0+r278197/gcc/config/aarch64/constraints.md
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/config/aarch64/constraints.md
+++ gcc-7.5.0+r278197/gcc/config/aarch64/constraints.md
@@ -24,6 +24,15 @@
(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
"@internal Registers suitable for an indirect tail call")
+(define_register_constraint "Ucr"
+ "aarch64_harden_sls_blr_p () ? STUB_REGS : GENERAL_REGS"
+ "@internal Registers to be used for an indirect call.
+ This is usually the general registers, but when we are hardening against
+ Straight Line Speculation we disallow x16, x17, and x30 so we can use
+ indirection stubs. These indirection stubs cannot use the above registers
+ since they will be reached by a BL that may have to go through a linker
+ veneer.")
+
(define_register_constraint "w" "FP_REGS"
"Floating point and SIMD vector registers.")
Index:
gcc-7.5.0+r278197/gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-miti-blr.c
===================================================================
--- /dev/null
+++
gcc-7.5.0+r278197/gcc/testsuite/gcc.target/aarch64/sls-mitigation/sls-miti-blr.c
@@ -0,0 +1,33 @@
+/* { dg-additional-options "-mharden-sls=blr -save-temps" } */
+/* Ensure that the SLS hardening of BLR leaves no BLR instructions.
+ We only test that all BLR instructions have been removed, not that the
+ resulting code makes sense. */
+typedef int (foo) (int, int);
+typedef void (bar) (int, int);
+struct sls_testclass {
+ foo *x;
+ bar *y;
+ int left;
+ int right;
+};
+
+/* We test both RTL patterns for a call which returns a value and a call which
+ does not. */
+int blr_call_value (struct sls_testclass x)
+{
+ int retval = x.x(x.left, x.right);
+ if (retval % 10)
+ return 100;
+ return 9;
+}
+
+int blr_call (struct sls_testclass x)
+{
+ x.y(x.left, x.right);
+ if (x.left % 10)
+ return 100;
+ return 9;
+}
+
+/* { dg-final { scan-assembler-not {\tblr\t} } } */
+/* { dg-final { scan-assembler {\tbr\tx[0-9][0-9]?} } } */
++++++ gcc7-fix-retrieval-of-testnames.patch ++++++
Backport of the below
commit db489777bb0185e64cf4b9b8c7afed4dcc6669bd
Author: Thomas Preud'homme <thomas.preudho...@arm.com>
Date: Fri Nov 10 09:42:45 2017 +0000
[testsuite] Fix retrieval of testname
When gcc-dg-runtest is used to run a test the test is run several times
with different options. For clarity of the log, the test infrastructure
then append the options to the testname. This means that all the code
that must deal with the testcase itself (eg. removing the output files
after the test has run) needs to remove the option name.
There is already a pattern (see below) for this in several place of the
testsuite framework but it is also missing in many places. This patch
fixes all of these places. The pattern is as follows:
set testcase [testname-for-summary]
; The name might include a list of options; extract the file name.
set testcase [lindex $testcase 0]
2017-11-10 Thomas Preud'homme <thomas.preudho...@arm.com>
gcc/testsuite/
* lib/scanasm.exp (scan-assembler): Extract filename from testname used
in summary.
(scan-assembler-not): Likewise.
(scan-hidden): Likewise.
(scan-not-hidden): Likewise.
(scan-stack-usage): Likewise.
(scan-stack-usage-not): Likewise.
(scan-assembler-times): Likewise.
(scan-assembler-dem): Likewise.
(scan-assembler-dem-not): Likewise.
(object-size): Likewise.
(scan-lto-assembler): Likewise.
* lib/scandump.exp (scan-dump): Likewise.
(scan-dump-times): Likewise.
(scan-dump-not): Likewise.
(scan-dump-dem): Likewise.
(scan-dump-dem-not): Likewise
From-SVN: r254622
Index: gcc-7.5.0+r278197/gcc/testsuite/lib/scanasm.exp
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/testsuite/lib/scanasm.exp
+++ gcc-7.5.0+r278197/gcc/testsuite/lib/scanasm.exp
@@ -78,7 +78,9 @@ proc dg-scan { name positive testcase ou
proc scan-assembler { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].s"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].s"
dg-scan "scan-assembler" 1 $testcase $output_file $args
}
@@ -89,7 +91,9 @@ force_conventional_output_for scan-assem
proc scan-assembler-not { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].s"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].s"
dg-scan "scan-assembler-not" 0 $testcase $output_file $args
}
@@ -117,7 +121,9 @@ proc hidden-scan-for { symbol } {
proc scan-hidden { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].s"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].s"
set symbol [lindex $args 0]
@@ -133,7 +139,9 @@ proc scan-hidden { args } {
proc scan-not-hidden { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].s"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].s"
set symbol [lindex $args 0]
set hidden_scan [hidden-scan-for $symbol]
@@ -163,7 +171,9 @@ proc scan-file-not { output_file args }
proc scan-stack-usage { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].su"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].su"
dg-scan "scan-file" 1 $testcase $output_file $args
}
@@ -173,7 +183,9 @@ proc scan-stack-usage { args } {
proc scan-stack-usage-not { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].su"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].su"
dg-scan "scan-file-not" 0 $testcase $output_file $args
}
@@ -230,11 +242,13 @@ proc scan-assembler-times { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set pattern [lindex $args 0]
set pp_pattern [make_pattern_printable $pattern]
# This must match the rule in gcc-dg.exp.
- set output_file "[file rootname [file tail $testcase]].s"
+ set output_file "[file rootname [file tail $filename]].s"
set files [glob -nocomplain $output_file]
if { $files == "" } {
@@ -290,9 +304,11 @@ proc scan-assembler-dem { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set pattern [lindex $args 0]
set pp_pattern [make_pattern_printable $pattern]
- set output_file "[file rootname [file tail $testcase]].s"
+ set output_file "[file rootname [file tail $filename]].s"
set files [glob -nocomplain $output_file]
if { $files == "" } {
@@ -344,9 +360,11 @@ proc scan-assembler-dem-not { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set pattern [lindex $args 0]
set pp_pattern [make_pattern_printable $pattern]
- set output_file "[file rootname [file tail $testcase]].s"
+ set output_file "[file rootname [file tail $filename]].s"
set files [glob -nocomplain $output_file]
if { $files == "" } {
@@ -399,6 +417,8 @@ proc object-size { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set what [lindex $args 0]
set where [lsearch { text data bss total } $what]
if { $where == -1 } {
@@ -416,7 +436,7 @@ proc object-size { args } {
return
}
- set output_file "[file rootname [file tail $testcase]].o"
+ set output_file "[file rootname [file tail $filename]].o"
if ![file_on_host exists $output_file] {
verbose -log "$testcase: $output_file does not exist"
unresolved "$testcase object-size $what $cmp $with"
@@ -510,7 +530,9 @@ proc dg-function-on-line { args } {
proc scan-lto-assembler { args } {
set testcase [testname-for-summary]
- set output_file "[file rootname [file tail $testcase]].exe.ltrans0.s"
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
+ set output_file "[file rootname [file tail $filename]].exe.ltrans0.s"
verbose "output_file: $output_file"
dg-scan "scan-assembler" 1 $testcase $output_file $args
}
Index: gcc-7.5.0+r278197/gcc/testsuite/lib/scandump.exp
===================================================================
--- gcc-7.5.0+r278197.orig/gcc/testsuite/lib/scandump.exp
+++ gcc-7.5.0+r278197/gcc/testsuite/lib/scandump.exp
@@ -45,11 +45,13 @@ proc scan-dump { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set printable_pattern [make_pattern_printable [lindex $args 1]]
set suf [dump-suffix [lindex $args 2]]
set testname "$testcase scan-[lindex $args 0]-dump $suf
\"$printable_pattern\""
- set src [file tail [lindex $testcase 0]]
+ set src [file tail $filename]
set output_file "[glob -nocomplain $src.[lindex $args 2]]"
if { $output_file == "" } {
verbose -log "$testcase: dump file does not exist"
@@ -86,10 +88,12 @@ proc scan-dump-times { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set suf [dump-suffix [lindex $args 3]]
set printable_pattern [make_pattern_printable [lindex $args 1]]
set testname "$testcase scan-[lindex $args 0]-dump-times $suf
\"$printable_pattern\" [lindex $args 2]"
- set src [file tail [lindex $testcase 0]]
+ set src [file tail $filename]
set output_file "[glob -nocomplain $src.[lindex $args 3]]"
if { $output_file == "" } {
verbose -log "$testcase: dump file does not exist"
@@ -126,10 +130,12 @@ proc scan-dump-not { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set printable_pattern [make_pattern_printable [lindex $args 1]]
set suf [dump-suffix [lindex $args 2]]
set testname "$testcase scan-[lindex $args 0]-dump-not $suf
\"$printable_pattern\""
- set src [file tail [lindex $testcase 0]]
+ set src [file tail $filename]
set output_file "[glob -nocomplain $src.[lindex $args 2]]"
if { $output_file == "" } {
verbose -log "$testcase: dump file does not exist"
@@ -179,10 +185,12 @@ proc scan-dump-dem { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set printable_pattern [make_pattern_printable [lindex $args 1]]
set suf [dump-suffix [lindex $args 2]]
set testname "$testcase scan-[lindex $args 0]-dump-dem $suf
\"$printable_pattern\""
- set src [file tail [lindex $testcase 0]]
+ set src [file tail $filename]
set output_file "[glob -nocomplain $src.[lindex $args 2]]"
if { $output_file == "" } {
verbose -log "$testcase: dump file does not exist"
@@ -231,10 +239,12 @@ proc scan-dump-dem-not { args } {
}
set testcase [testname-for-summary]
+ # The name might include a list of options; extract the file name.
+ set filename [lindex $testcase 0]
set printable_pattern [make_pattern_printable [lindex $args 1]
set suf [dump-suffix [lindex $args 2]]
set testname "$testcase scan-[lindex $args 0]-dump-dem-not $suf
\"$printable_pattern\""
- set src [file tail [lindex $testcase 0]]
+ set src [file tail $filename]
set output_file "[glob -nocomplain $src.[lindex $args 2]]"
if { $output_file == "" } {
verbose -log "$testcase: dump file does not exist"
++++++ gcc7-pr88522.patch ++++++
backport: re PR target/88522 (Error: operand size mismatch for `vpgatherqq')
Backported from mainline
2018-12-21 Jakub Jelinek <ja...@redhat.com>
PR target/88522
* config/i386/sse.md (*avx512pf_gatherpf<mode>sf_mask,
*avx512pf_gatherpf<mode>df_mask, *avx512pf_scatterpf<mode>sf_mask,
*avx512pf_scatterpf<mode>df_mask): Use %X5 instead of %5 for
-masm=intel.
(gatherq_mode): Remove mode iterator.
(*avx512f_gathersi<mode>, *avx512f_gathersi<mode>_2): Use X instead
of <xtg_mode>.
(*avx512f_gatherdi<mode>): Use X instead of <gatherq_mode>.
(*avx512f_gatherdi<mode>_2, *avx512f_scattersi<mode>,
*avx512f_scatterdi<mode>): Use %X5 for -masm=intel.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c8b314abaa6..aecd98851a5 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16039,9 +16039,9 @@
switch (INTVAL (operands[4]))
{
case 3:
- return "%M2vgatherpf0<ssemodesuffix>ps\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vgatherpf0<ssemodesuffix>ps\t{%5%{%0%}|%X5%{%0%}}";
case 2:
- return "%M2vgatherpf1<ssemodesuffix>ps\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vgatherpf1<ssemodesuffix>ps\t{%5%{%0%}|%X5%{%0%}}";
default:
gcc_unreachable ();
}
@@ -16084,9 +16084,9 @@
switch (INTVAL (operands[4]))
{
case 3:
- return "%M2vgatherpf0<ssemodesuffix>pd\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vgatherpf0<ssemodesuffix>pd\t{%5%{%0%}|%X5%{%0%}}";
case 2:
- return "%M2vgatherpf1<ssemodesuffix>pd\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vgatherpf1<ssemodesuffix>pd\t{%5%{%0%}|%X5%{%0%}}";
default:
gcc_unreachable ();
}
@@ -16130,10 +16130,10 @@
{
case 3:
case 7:
- return "%M2vscatterpf0<ssemodesuffix>ps\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vscatterpf0<ssemodesuffix>ps\t{%5%{%0%}|%X5%{%0%}}";
case 2:
case 6:
- return "%M2vscatterpf1<ssemodesuffix>ps\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vscatterpf1<ssemodesuffix>ps\t{%5%{%0%}|%X5%{%0%}}";
default:
gcc_unreachable ();
}
@@ -16177,10 +16177,10 @@
{
case 3:
case 7:
- return "%M2vscatterpf0<ssemodesuffix>pd\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vscatterpf0<ssemodesuffix>pd\t{%5%{%0%}|%X5%{%0%}}";
case 2:
case 6:
- return "%M2vscatterpf1<ssemodesuffix>pd\t{%5%{%0%}|%5%{%0%}}";
+ return "%M2vscatterpf1<ssemodesuffix>pd\t{%5%{%0%}|%X5%{%0%}}";
default:
gcc_unreachable ();
}
@@ -19180,12 +19180,6 @@
(set_attr "prefix" "vex")
(set_attr "mode" "<sseinsnmode>")])
-;; Memory operand override for -masm=intel of the v*gatherq* patterns.
-(define_mode_attr gatherq_mode
- [(V4SI "q") (V2DI "x") (V4SF "q") (V2DF "x")
- (V8SI "x") (V4DI "t") (V8SF "x") (V4DF "t")
- (V16SI "t") (V8DI "g") (V16SF "t") (V8DF "g")])
-
(define_expand "<avx512>_gathersi<mode>"
[(parallel [(set (match_operand:VI48F 0 "register_operand")
(unspec:VI48F
@@ -19219,7 +19213,7 @@
UNSPEC_GATHER))
(clobber (match_scratch:<avx512fmaskmode> 2 "=&Yk"))]
"TARGET_AVX512F"
- "%M4v<sseintprefix>gatherd<ssemodesuffix>\t{%6, %0%{%2%}|%0%{%2%},
%<xtg_mode>6}"
+ "%M4v<sseintprefix>gatherd<ssemodesuffix>\t{%6, %0%{%2%}|%0%{%2%}, %X6}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -19238,7 +19232,7 @@
UNSPEC_GATHER))
(clobber (match_scratch:<avx512fmaskmode> 1 "=&Yk"))]
"TARGET_AVX512F"
- "%M3v<sseintprefix>gatherd<ssemodesuffix>\t{%5, %0%{%1%}|%0%{%1%},
%<xtg_mode>5}"
+ "%M3v<sseintprefix>gatherd<ssemodesuffix>\t{%5, %0%{%1%}|%0%{%1%}, %X5}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -19278,7 +19272,7 @@
(clobber (match_scratch:QI 2 "=&Yk"))]
"TARGET_AVX512F"
{
- return "%M4v<sseintprefix>gatherq<ssemodesuffix>\t{%6, %1%{%2%}|%1%{%2%},
%<gatherq_mode>6}";
+ return "%M4v<sseintprefix>gatherq<ssemodesuffix>\t{%6, %1%{%2%}|%1%{%2%},
%X6}";
}
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
@@ -19302,11 +19296,11 @@
if (<MODE>mode != <VEC_GATHER_SRCDI>mode)
{
if (<MODE_SIZE> != 64)
- return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5,
%x0%{%1%}|%x0%{%1%}, %<gatherq_mode>5}";
+ return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5,
%x0%{%1%}|%x0%{%1%}, %X5}";
else
- return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5,
%t0%{%1%}|%t0%{%1%}, %t5}";
+ return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5,
%t0%{%1%}|%t0%{%1%}, %X5}";
}
- return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5, %0%{%1%}|%0%{%1%},
%<gatherq_mode>5}";
+ return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5, %0%{%1%}|%0%{%1%},
%X5}";
}
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
@@ -19343,7 +19337,7 @@
UNSPEC_SCATTER))
(clobber (match_scratch:<avx512fmaskmode> 1 "=&Yk"))]
"TARGET_AVX512F"
- "%M0v<sseintprefix>scatterd<ssemodesuffix>\t{%3, %5%{%1%}|%5%{%1%}, %3}"
+ "%M0v<sseintprefix>scatterd<ssemodesuffix>\t{%3, %5%{%1%}|%X5%{%1%}, %3}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -19379,11 +19373,7 @@
UNSPEC_SCATTER))
(clobber (match_scratch:QI 1 "=&Yk"))]
"TARGET_AVX512F"
-{
- if (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 8)
- return "%M0v<sseintprefix>scatterq<ssemodesuffix>\t{%3, %5%{%1%}|%5%{%1%},
%3}";
- return "%M0v<sseintprefix>scatterq<ssemodesuffix>\t{%3, %5%{%1%}|%t5%{%1%},
%3}";
-}
+ "%M0v<sseintprefix>scatterq<ssemodesuffix>\t{%3, %5%{%1%}|%X5%{%1%}, %3}"
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
++++++ gcc7-remove-Wexpansion-to-defined-from-Wextra.patch ++++++
--- /var/tmp/diff_new_pack.Hp1dVw/_old 2020-12-05 20:36:39.206676560 +0100
+++ /var/tmp/diff_new_pack.Hp1dVw/_new 2020-12-05 20:36:39.210676564 +0100
@@ -11,3 +11,16 @@
Warn if \"defined\" is used outside #if.
Wimplicit-function-declaration
+diff --git gcc/testsuite/gcc.dg/cpp/defined-Wextra.c
gcc/testsuite/gcc.dg/cpp/defined-Wextra.c
+index 460a1cb43b2..b4de2b72d97 100644
+--- gcc/testsuite/gcc.dg/cpp/defined-Wextra.c
++++ gcc/testsuite/gcc.dg/cpp/defined-Wextra.c
+@@ -1,7 +1,7 @@
+ /* Copyright (C) 2000 Free Software Foundation, Inc. */
+
+ /* { dg-do preprocess } */
+-/* { dg-options "-Wextra" } */
++/* { dg-options "-Wextra -Wexpansion-to-defined" } */
+
+ /* Use of defined in different contexts. */
+
++++++ gcc7-testsuite-fixes.patch ++++++
diff --git a/gcc/testsuite/gcc.dg/strncmp-2.c b/gcc/testsuite/gcc.dg/strncmp-2.c
index ed6c5fa0880..db46d0af4e0 100644
--- a/gcc/testsuite/gcc.dg/strncmp-2.c
+++ b/gcc/testsuite/gcc.dg/strncmp-2.c
@@ -40,6 +40,7 @@ static void test_driver_strncmp (void (test_strncmp)(const
char *, const char *,
e = lib_memcmp(buf1,p2,sz);
(*test_memcmp)(buf1,p2,e);
}
+ mprotect (buf2+pgsz,pgsz,PROT_READ|PROT_WRITE);
free(buf2);
}
diff --git a/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
b/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
index ba566f869c6..ca51d6d1a78 100644
--- a/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
+++ b/libstdc++-v3/testsuite/ext/stdio_filebuf/char/79820.cc
@@ -26,10 +26,12 @@ void
test01()
{
FILE* f = std::fopen("79820.txt", "w");
+ {
+ errno = 127;
+ __gnu_cxx::stdio_filebuf<char> b(f, std::ios::out, BUFSIZ);
+ VERIFY(errno == 127); // PR libstdc++/79820
+ }
std::fclose(f);
- errno = 127;
- __gnu_cxx::stdio_filebuf<char> b(f, std::ios::out, BUFSIZ);
- VERIFY(errno == 127); // PR libstdc++/79820
}
int
diff --git a/gcc/testsuite/gcc.target/i386/xop-hsubX.c
b/gcc/testsuite/gcc.target/i386/xop-hsubX.c
index f0fa9b312f2..dc7944d8bb7 100644
--- a/gcc/testsuite/gcc.target/i386/xop-hsubX.c
+++ b/gcc/testsuite/gcc.target/i386/xop-hsubX.c
@@ -58,6 +58,7 @@ check_sbyte2word ()
check_fails++;
}
}
+ return check_fails;
}
static int
@@ -75,6 +76,7 @@ check_sword2dword ()
check_fails++;
}
}
+ return check_fails;
}
static int
@@ -92,6 +94,7 @@ check_dword2qword ()
check_fails++;
}
}
+ return check_fails;
}
static void
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