Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package gdb for openSUSE:Factory checked in at 2025-03-16 18:58:09 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/gdb (Old) and /work/SRC/openSUSE:Factory/.gdb.new.19136 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "gdb" Sun Mar 16 18:58:09 2025 rev:184 rq:1252754 version:15.2 Changes: -------- --- /work/SRC/openSUSE:Factory/gdb/gdb.changes 2025-02-18 19:09:22.473167908 +0100 +++ /work/SRC/openSUSE:Factory/.gdb.new.19136/gdb.changes 2025-03-16 18:58:23.135964796 +0100 @@ -1,0 +2,41 @@ +Thu Mar 13 10:51:28 UTC 2025 - Tom de Vries <tdevr...@suse.com> + +- Patches added: + * gdb-record-fix-out-of-bounds-write-in-aarch64_record.patch + * gdb-tdep-backport-i386_canonicalize_syscall-rewrite-.patch +- Maintenance script qa.sh: + * Remove PR32770 kfail. + * Move PR32678 from kfail_i586 to kfail_factory. + +------------------------------------------------------------------- +Tue Mar 11 06:17:54 UTC 2025 - Tom de Vries <tdevr...@suse.com> + +- Maintenance script qa.sh: + * Add PR32688 and PR32770 kfails. +- Patches added: + * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-for-amd.patch + * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-glibc-2-41.patch +- Patches dropped: + * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-amd-case.patch + +------------------------------------------------------------------- +Fri Mar 7 21:55:47 UTC 2025 - Tom de Vries <tdevr...@suse.com> + +- Drop "BuildRequires: libgo23". + +------------------------------------------------------------------- +Fri Mar 7 14:01:38 UTC 2025 - Tom de Vries <tdevr...@suse.com> + +- Patches added (jsc#PED-10305): + * s390-align-opcodes-to-lower-case.patch + * s390-simplify-dis-assembly-of-insn-operands-with-con.patch + * s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch + * s390-add-arch15-instructions.patch + * opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch + * s390-add-arch15-instruction-names.patch + * s390-add-arch15-concurrent-functions-facility-insns.patch + * s390-fix-disassembly-of-optional-addressing-operands.patch + * s390-treat-addressing-operand-sequence-as-one-in-dis.patch + * gdb-testsuite-add-gdb.arch-s390-disassemble.exp.patch + +------------------------------------------------------------------- Old: ---- gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-amd-case.patch New: ---- gdb-record-fix-out-of-bounds-write-in-aarch64_record.patch gdb-tdep-backport-i386_canonicalize_syscall-rewrite-.patch gdb-testsuite-add-gdb.arch-s390-disassemble.exp.patch gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-glibc-2-41.patch gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-for-amd.patch opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch s390-add-arch15-concurrent-functions-facility-insns.patch s390-add-arch15-instruction-names.patch s390-add-arch15-instructions.patch s390-align-opcodes-to-lower-case.patch s390-fix-disassembly-of-optional-addressing-operands.patch s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch s390-simplify-dis-assembly-of-insn-operands-with-con.patch s390-treat-addressing-operand-sequence-as-one-in-dis.patch BETA DEBUG BEGIN: Old:- Patches dropped: * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-amd-case.patch BETA DEBUG END: BETA DEBUG BEGIN: New:- Patches added: * gdb-record-fix-out-of-bounds-write-in-aarch64_record.patch * gdb-tdep-backport-i386_canonicalize_syscall-rewrite-.patch New: * gdb-record-fix-out-of-bounds-write-in-aarch64_record.patch * gdb-tdep-backport-i386_canonicalize_syscall-rewrite-.patch - Maintenance script qa.sh: New: * s390-treat-addressing-operand-sequence-as-one-in-dis.patch * gdb-testsuite-add-gdb.arch-s390-disassemble.exp.patch New: * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-for-amd.patch * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-glibc-2-41.patch - Patches dropped: New:- Patches added: * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-for-amd.patch * gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-glibc-2-41.patch New: * s390-add-arch15-instructions.patch * opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch * s390-add-arch15-instruction-names.patch New: * s390-add-arch15-instruction-names.patch * s390-add-arch15-concurrent-functions-facility-insns.patch * s390-fix-disassembly-of-optional-addressing-operands.patch New: * opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch * s390-add-arch15-instruction-names.patch * s390-add-arch15-concurrent-functions-facility-insns.patch New: * s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch * s390-add-arch15-instructions.patch * opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch New:- Patches added (jsc#PED-10305): * s390-align-opcodes-to-lower-case.patch * s390-simplify-dis-assembly-of-insn-operands-with-con.patch New: * s390-add-arch15-concurrent-functions-facility-insns.patch * s390-fix-disassembly-of-optional-addressing-operands.patch * s390-treat-addressing-operand-sequence-as-one-in-dis.patch New: * s390-simplify-dis-assembly-of-insn-operands-with-con.patch * s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch * s390-add-arch15-instructions.patch New: * s390-align-opcodes-to-lower-case.patch * s390-simplify-dis-assembly-of-insn-operands-with-con.patch * s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch New: * s390-fix-disassembly-of-optional-addressing-operands.patch * s390-treat-addressing-operand-sequence-as-one-in-dis.patch * gdb-testsuite-add-gdb.arch-s390-disassemble.exp.patch BETA DEBUG END: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ gdb.spec ++++++ --- /var/tmp/diff_new_pack.esd5Vf/_old 2025-03-16 18:58:25.652070052 +0100 +++ /var/tmp/diff_new_pack.esd5Vf/_new 2025-03-16 18:58:25.656070220 +0100 @@ -1,5 +1,5 @@ # -# spec file +# spec file for package gdb # # Copyright (c) 2025 SUSE LLC # Copyright (c) 2012 RedHat @@ -218,10 +218,6 @@ # Fixes: # FAIL: gdb.mi/new-ui-mi-sync.exp: sync-command=run: add-inferior (timeout) Patch1504: fix-gdb.mi-new-ui-mi-sync.exp.patch -# Fixes: -# FAIL: gdb.base/step-over-syscall.exp: fork: displaced=off: \ -# pc after stepi matches insn addr after syscall -Patch1505: gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-amd-case.patch # https://sourceware.org/bugzilla/show_bug.cgi?id=32590 Patch1506: gdb-cli-print-at_hwcap3-and-at_hwcap4.patch # Work around SCM_UNPACK Werror=sequence-point in libguile v2.0.9 (SLE-12). @@ -265,6 +261,7 @@ Patch2031: gdb-prune-inferior-after-switching-inferior.patch Patch2032: gdb-testsuite-fix-timeout-in-gdb.mi-mi-multi-command.patch Patch2033: gdb-testsuite-fix-regexp-in-gdb.threads-stepi-over-c.patch +Patch2034: gdb-record-fix-out-of-bounds-write-in-aarch64_record.patch # Backports from master, available in GDB 17. @@ -291,6 +288,9 @@ Patch2120: gdb-testsuite-require-can_spawn_for_attach-in-gdb.ba.patch Patch2121: gdb-testsuite-fix-gdb.ada-big_packed_array.exp-on-s3.patch Patch2122: gdb-testsuite-fix-gdb.ada-convvar_comp.exp-on-s390x-.patch +Patch2123: gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-for-amd.patch +Patch2124: gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-glibc-2-41.patch +Patch2125: gdb-tdep-backport-i386_canonicalize_syscall-rewrite-.patch # Backport from gdb-patches @@ -310,6 +310,20 @@ Patch3006: gdb-symtab-recurse-into-c-dw_tag_subprogram-dies-for.patch # https://sourceware.org/bugzilla/show_bug.cgi?id=30380#c1 Patch3007: gdb-testsuite-use-c-flag-in-c-test-cases.patch +# https://sourceware.org/pipermail/gdb-patches/2025-March/216050.html +Patch3008: gdb-testsuite-add-gdb.arch-s390-disassemble.exp.patch + +# s390x libopcodes backports, available in GDB 16. + +Patch4000: s390-align-opcodes-to-lower-case.patch +Patch4001: s390-simplify-dis-assembly-of-insn-operands-with-con.patch +Patch4002: s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch +Patch4003: s390-add-arch15-instructions.patch +Patch4004: opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch +Patch4005: s390-add-arch15-instruction-names.patch +Patch4006: s390-add-arch15-concurrent-functions-facility-insns.patch +Patch4007: s390-fix-disassembly-of-optional-addressing-operands.patch +Patch4008: s390-treat-addressing-operand-sequence-as-one-in-dis.patch # Debug patches. @@ -497,13 +511,6 @@ # gcc-go package (bsc#1096677), so we only require it for known fixed # versions. BuildRequires: gcc-go - -%if 0%{?suse_version} > 1600 -# Fix: unresolvable: -# have choice for libgo.so.23()(64bit) needed by gcc14-go: libgo23 libgo23-gcc14 -# have choice for libgo23 >= 14.2.1+git10750-37.2 needed by gcc14-go: libgo23 libgo23-gcc14 -BuildRequires: libgo23 -%endif %endif %if %{with fpc} && 0%{?is_opensuse} @@ -657,7 +664,6 @@ %patch -P 1501 -p1 %patch -P 1503 -p1 %patch -P 1504 -p1 -%patch -P 1505 -p1 %patch -P 1506 -p1 %patch -P 1507 -p1 %patch -P 1508 -p1 @@ -696,6 +702,7 @@ %patch -P 2031 -p1 %patch -P 2032 -p1 %patch -P 2033 -p1 +%patch -P 2034 -p1 %patch -P 2100 -p1 %patch -P 2101 -p1 @@ -720,6 +727,9 @@ %patch -P 2120 -p1 %patch -P 2121 -p1 %patch -P 2122 -p1 +%patch -P 2123 -p1 +%patch -P 2124 -p1 +%patch -P 2125 -p1 %patch -P 3000 -p1 %patch -P 3001 -p1 @@ -729,6 +739,17 @@ %patch -P 3005 -p1 %patch -P 3006 -p1 %patch -P 3007 -p1 +%patch -P 3008 -p1 + +%patch -P 4000 -p1 +%patch -P 4001 -p1 +%patch -P 4002 -p1 +%patch -P 4003 -p1 +%patch -P 4004 -p1 +%patch -P 4005 -p1 +%patch -P 4006 -p1 +%patch -P 4007 -p1 +%patch -P 4008 -p1 #unpack libipt %if 0%{have_libipt} ++++++ gdb-record-fix-out-of-bounds-write-in-aarch64_record.patch ++++++ >From 9b1fc55c1887675923d4ddeda4b38ab05e6bb44c Mon Sep 17 00:00:00 2001 From: Tom de Vries <tdevr...@suse.de> Date: Thu, 13 Mar 2025 11:15:05 +0100 Subject: [PATCH 1/2] [gdb/record] Fix out-of-bounds write in aarch64_record_asimd_load_store After compiling gdb with -fstack-protector-all, and running test-case gdb.reverse/getrandom.exp on aarch64-linux, we run into "Stack smashing detected" in function aarch64_record_asimd_load_store. This is reported in PR record/32784. This happens due to an out-of-bounds write to local array record_buf_mem: ... uint64_t record_buf_mem[24]; ... when recording insn: ... B+>0xfffff7ff4d10 st1 {v0.16b-v3.16b}, [x0] ... We can fix this by increasing the array size to 128, but rather than again hardcoding a size, reimplement record_buf_mem as std::vector. Tested on aarch64-linux. Approved-By: Guinevere Larsen <guinev...@redhat.com> Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32784 (cherry picked from commit 51729ea0905d1f688b7fd2ea769e69b29daa1b7c) --- gdb/aarch64-tdep.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index e4bca6c6632..92daaa75b1c 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -5030,9 +5030,9 @@ aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) CORE_ADDR address; uint64_t addr_offset = 0; uint32_t record_buf[24]; - uint64_t record_buf_mem[24]; + std::vector<uint64_t> record_buf_mem; uint32_t reg_rn, reg_rt; - uint32_t reg_index = 0, mem_index = 0; + uint32_t reg_index = 0; uint8_t opcode_bits, size_bits; reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); @@ -5095,8 +5095,8 @@ aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; else { - record_buf_mem[mem_index++] = esize / 8; - record_buf_mem[mem_index++] = address + addr_offset; + record_buf_mem.push_back (esize / 8); + record_buf_mem.push_back (address + addr_offset); } addr_offset = addr_offset + (esize / 8); reg_rt = (reg_rt + 1) % 32; @@ -5167,8 +5167,8 @@ aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; else { - record_buf_mem[mem_index++] = esize / 8; - record_buf_mem[mem_index++] = address + addr_offset; + record_buf_mem.push_back (esize / 8); + record_buf_mem.push_back (address + addr_offset); } addr_offset = addr_offset + (esize / 8); reg_tt = (reg_tt + 1) % 32; @@ -5180,9 +5180,9 @@ aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) record_buf[reg_index++] = reg_rn; aarch64_insn_r->reg_rec_count = reg_index; - aarch64_insn_r->mem_rec_count = mem_index / 2; + aarch64_insn_r->mem_rec_count = record_buf_mem.size () / 2; MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, - record_buf_mem); + record_buf_mem.data ()); REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, record_buf); return AARCH64_RECORD_SUCCESS; base-commit: 96a340e789f714156bbac7f78f340e06659b5e70 -- 2.43.0 ++++++ gdb-tdep-backport-i386_canonicalize_syscall-rewrite-.patch ++++++ >From 32c2e500525b91b2771022252f79e1c5c29ddf48 Mon Sep 17 00:00:00 2001 From: Tom de Vries <tdevr...@suse.de> Date: Thu, 13 Mar 2025 09:39:51 +0100 Subject: [PATCH 2/2] [gdb/tdep] Backport i386_canonicalize_syscall rewrite to gdb-16-branch Commit fbfb29b304e ("[gdb/tdep] Rewrite i386_canonicalize_syscall") fixes PR32770, which reproduces on the gdb-16-branch, but the commit is not ideal for backporting because it completely rewrites i386_canonicalize_syscall. Instead, this is a version of the patch that adds a single line entry for each syscall value for which i386_canonicalize_syscall gives a different result with and without the patch. Consequently, the two versions give identical results. I've checked this for syscalls 0 to 466. Tested on x86_64-linux with target board unix/-m32, on top of gdb-16-branch. PR tdep/32770 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32770 --- gdb/i386-linux-tdep.c | 153 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 152 insertions(+), 1 deletion(-) diff --git a/gdb/i386-linux-tdep.c b/gdb/i386-linux-tdep.c index a78f03fac8d..b0ca8694ba5 100644 --- a/gdb/i386-linux-tdep.c +++ b/gdb/i386-linux-tdep.c @@ -376,7 +376,158 @@ i386_all_but_ip_registers_record (struct regcache *regcache) static enum gdb_syscall i386_canonicalize_syscall (int syscall) { - enum { i386_syscall_max = 499 }; + enum { i386_syscall_max = 466 }; + + switch (syscall) + { + case 359 /* socket */: return gdb_sys_socket; + case 360 /* socketpair */: return gdb_sys_socketpair; + case 361 /* bind */: return gdb_sys_bind; + case 362 /* connect */: return gdb_sys_connect; + case 363 /* listen */: return gdb_sys_listen; + case 365 /* getsockopt */: return gdb_sys_getsockopt; + case 366 /* setsockopt */: return gdb_sys_setsockopt; + case 367 /* getsockname */: return gdb_sys_getsockname; + case 368 /* getpeername */: return gdb_sys_getpeername; + case 369 /* sendto */: return gdb_sys_sendto; + case 370 /* sendmsg */: return gdb_sys_sendmsg; + case 371 /* recvfrom */: return gdb_sys_recvfrom; + case 372 /* recvmsg */: return gdb_sys_recvmsg; + case 373 /* shutdown */: return gdb_sys_shutdown; + case 393 /* semget */: return gdb_sys_semget; + case 394 /* semctl */: return gdb_sys_semctl; + case 395 /* shmget */: return gdb_sys_shmget; + case 396 /* shmctl */: return gdb_sys_shmctl; + case 397 /* shmat */: return gdb_sys_shmat; + case 398 /* shmdt */: return gdb_sys_shmdt; + case 399 /* msgget */: return gdb_sys_msgget; + case 400 /* msgsnd */: return gdb_sys_msgsnd; + case 401 /* msgrcv */: return gdb_sys_msgrcv; + case 402 /* msgctl */: return gdb_sys_msgctl; + case 420 /* semtimedop_time64 */: return gdb_sys_semtimedop; + + case 320 /* utimensat */: return gdb_sys_no_syscall; + case 321 /* signalfd */: return gdb_sys_no_syscall; + case 322 /* timerfd_create */: return gdb_sys_no_syscall; + case 323 /* eventfd */: return gdb_sys_no_syscall; + case 325 /* timerfd_settime */: return gdb_sys_no_syscall; + case 326 /* timerfd_gettime */: return gdb_sys_no_syscall; + case 327 /* signalfd4 */: return gdb_sys_no_syscall; + case 333 /* preadv */: return gdb_sys_no_syscall; + case 334 /* pwritev */: return gdb_sys_no_syscall; + case 335 /* rt_tgsigqueueinfo */: return gdb_sys_no_syscall; + case 336 /* perf_event_open */: return gdb_sys_no_syscall; + case 337 /* recvmmsg */: return gdb_sys_no_syscall; + case 338 /* fanotify_init */: return gdb_sys_no_syscall; + case 339 /* fanotify_mark */: return gdb_sys_no_syscall; + case 340 /* prlimit64 */: return gdb_sys_no_syscall; + case 341 /* name_to_handle_at */: return gdb_sys_no_syscall; + case 342 /* open_by_handle_at */: return gdb_sys_no_syscall; + case 343 /* clock_adjtime */: return gdb_sys_no_syscall; + case 344 /* syncfs */: return gdb_sys_no_syscall; + case 345 /* sendmmsg */: return gdb_sys_no_syscall; + case 346 /* setns */: return gdb_sys_no_syscall; + case 347 /* process_vm_readv */: return gdb_sys_no_syscall; + case 348 /* process_vm_writev */: return gdb_sys_no_syscall; + case 349 /* kcmp */: return gdb_sys_no_syscall; + case 350 /* finit_module */: return gdb_sys_no_syscall; + case 351 /* sched_setattr */: return gdb_sys_no_syscall; + case 352 /* sched_getattr */: return gdb_sys_no_syscall; + case 353 /* renameat2 */: return gdb_sys_no_syscall; + case 354 /* seccomp */: return gdb_sys_no_syscall; + case 356 /* memfd_create */: return gdb_sys_no_syscall; + case 357 /* bpf */: return gdb_sys_no_syscall; + case 358 /* execveat */: return gdb_sys_no_syscall; + case 364 /* accept4 */: return gdb_sys_no_syscall; + case 374 /* userfaultfd */: return gdb_sys_no_syscall; + case 375 /* membarrier */: return gdb_sys_no_syscall; + case 376 /* mlock2 */: return gdb_sys_no_syscall; + case 377 /* copy_file_range */: return gdb_sys_no_syscall; + case 378 /* preadv2 */: return gdb_sys_no_syscall; + case 379 /* pwritev2 */: return gdb_sys_no_syscall; + case 380 /* pkey_mprotect */: return gdb_sys_no_syscall; + case 381 /* pkey_alloc */: return gdb_sys_no_syscall; + case 382 /* pkey_free */: return gdb_sys_no_syscall; + case 384 /* arch_prctl */: return gdb_sys_no_syscall; + case 385 /* io_pgetevents */: return gdb_sys_no_syscall; + case 386 /* rseq */: return gdb_sys_no_syscall; + case 404 /* clock_settime64 */: return gdb_sys_no_syscall; + case 405 /* clock_adjtime64 */: return gdb_sys_no_syscall; + case 406 /* clock_getres_time64 */: return gdb_sys_no_syscall; + case 407 /* clock_nanosleep_time64 */: return gdb_sys_no_syscall; + case 408 /* timer_gettime64 */: return gdb_sys_no_syscall; + case 409 /* timer_settime64 */: return gdb_sys_no_syscall; + case 410 /* timerfd_gettime64 */: return gdb_sys_no_syscall; + case 411 /* timerfd_settime64 */: return gdb_sys_no_syscall; + case 412 /* utimensat_time64 */: return gdb_sys_no_syscall; + case 413 /* pselect6_time64 */: return gdb_sys_no_syscall; + case 414 /* ppoll_time64 */: return gdb_sys_no_syscall; + case 416 /* io_pgetevents_time64 */: return gdb_sys_no_syscall; + case 417 /* recvmmsg_time64 */: return gdb_sys_no_syscall; + case 418 /* mq_timedsend_time64 */: return gdb_sys_no_syscall; + case 419 /* mq_timedreceive_time64 */: return gdb_sys_no_syscall; + case 421 /* rt_sigtimedwait_time64 */: return gdb_sys_no_syscall; + case 422 /* futex_time64 */: return gdb_sys_no_syscall; + case 423 /* sched_rr_get_interval_time64 */: return gdb_sys_no_syscall; + case 424 /* pidfd_send_signal */: return gdb_sys_no_syscall; + case 425 /* io_uring_setup */: return gdb_sys_no_syscall; + case 426 /* io_uring_enter */: return gdb_sys_no_syscall; + case 427 /* io_uring_register */: return gdb_sys_no_syscall; + case 428 /* open_tree */: return gdb_sys_no_syscall; + case 429 /* move_mount */: return gdb_sys_no_syscall; + case 430 /* fsopen */: return gdb_sys_no_syscall; + case 431 /* fsconfig */: return gdb_sys_no_syscall; + case 432 /* fsmount */: return gdb_sys_no_syscall; + case 433 /* fspick */: return gdb_sys_no_syscall; + case 434 /* pidfd_open */: return gdb_sys_no_syscall; + case 435 /* clone3 */: return gdb_sys_no_syscall; + case 436 /* close_range */: return gdb_sys_no_syscall; + case 437 /* openat2 */: return gdb_sys_no_syscall; + case 438 /* pidfd_getfd */: return gdb_sys_no_syscall; + case 439 /* faccessat2 */: return gdb_sys_no_syscall; + case 440 /* process_madvise */: return gdb_sys_no_syscall; + case 441 /* epoll_pwait2 */: return gdb_sys_no_syscall; + case 442 /* mount_setattr */: return gdb_sys_no_syscall; + case 443 /* quotactl_fd */: return gdb_sys_no_syscall; + case 444 /* landlock_create_ruleset */: return gdb_sys_no_syscall; + case 445 /* landlock_add_rule */: return gdb_sys_no_syscall; + case 446 /* landlock_restrict_self */: return gdb_sys_no_syscall; + case 447 /* memfd_secret */: return gdb_sys_no_syscall; + case 448 /* process_mrelease */: return gdb_sys_no_syscall; + case 449 /* futex_waitv */: return gdb_sys_no_syscall; + case 450 /* set_mempolicy_home_node */: return gdb_sys_no_syscall; + case 451 /* cachestat */: return gdb_sys_no_syscall; + case 452 /* fchmodat2 */: return gdb_sys_no_syscall; + case 453 /* map_shadow_stack */: return gdb_sys_no_syscall; + case 454 /* futex_wake */: return gdb_sys_no_syscall; + case 455 /* futex_wait */: return gdb_sys_no_syscall; + case 456 /* futex_requeue */: return gdb_sys_no_syscall; + case 457 /* statmount */: return gdb_sys_no_syscall; + case 458 /* listmount */: return gdb_sys_no_syscall; + case 459 /* lsm_get_self_attr */: return gdb_sys_no_syscall; + case 460 /* lsm_set_self_attr */: return gdb_sys_no_syscall; + case 461 /* lsm_list_modules */: return gdb_sys_no_syscall; + case 462 /* mseal */: return gdb_sys_no_syscall; + case 463 /* setxattrat */: return gdb_sys_no_syscall; + case 464 /* getxattrat */: return gdb_sys_no_syscall; + case 465 /* listxattrat */: return gdb_sys_no_syscall; + case 466 /* removexattrat */: return gdb_sys_no_syscall; + + case 222 /* unused */: return gdb_sys_no_syscall; + case 223 /* unused */: return gdb_sys_no_syscall; + case 251 /* unused */: return gdb_sys_no_syscall; + case 285 /* unused */: return gdb_sys_no_syscall; + case 387 /* unused */: return gdb_sys_no_syscall; + case 388 /* unused */: return gdb_sys_no_syscall; + case 389 /* unused */: return gdb_sys_no_syscall; + case 390 /* unused */: return gdb_sys_no_syscall; + case 391 /* unused */: return gdb_sys_no_syscall; + case 392 /* unused */: return gdb_sys_no_syscall; + case 415 /* unused */: return gdb_sys_no_syscall; + + default: + break; + } if (syscall <= i386_syscall_max) return (enum gdb_syscall) syscall; -- 2.43.0 ++++++ gdb-testsuite-add-gdb.arch-s390-disassemble.exp.patch ++++++ >From 29bcee2db6233ff0ea4fc9231910bb2da530308e Mon Sep 17 00:00:00 2001 From: Tom de Vries <tdevr...@suse.de> Date: Thu, 6 Mar 2025 21:19:39 +0100 Subject: [PATCH 10/10] [gdb/testsuite] Add gdb.arch/s390-disassemble.exp In commit a98a6fa2d8e ("s390: Add arch15 instructions"), support for new instructions was added to libopcodes, but the added tests only exercise this for gas. Add a test-case gdb.arch/s390-disassemble.exp that checks gdb's ability to disassemble one of these instructions. Tested on s390x-linux. --- gdb/testsuite/gdb.arch/s390-disassemble.c | 23 ++++++++++++++ gdb/testsuite/gdb.arch/s390-disassemble.exp | 35 +++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 gdb/testsuite/gdb.arch/s390-disassemble.c create mode 100644 gdb/testsuite/gdb.arch/s390-disassemble.exp diff --git a/gdb/testsuite/gdb.arch/s390-disassemble.c b/gdb/testsuite/gdb.arch/s390-disassemble.c new file mode 100644 index 00000000000..ee6469ddf98 --- /dev/null +++ b/gdb/testsuite/gdb.arch/s390-disassemble.c @@ -0,0 +1,23 @@ +/* This file is part of GDB, the GNU debugger. + + Copyright 2025 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +void +clzg (void) +{ + /* clzg %r0,%r3. */ + asm volatile (" .long 0xb9680003"); +} diff --git a/gdb/testsuite/gdb.arch/s390-disassemble.exp b/gdb/testsuite/gdb.arch/s390-disassemble.exp new file mode 100644 index 00000000000..0c187df3c11 --- /dev/null +++ b/gdb/testsuite/gdb.arch/s390-disassemble.exp @@ -0,0 +1,35 @@ +# Copyright 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. + +# Check that GDB is able to disassemble certain s390x instructions. + +require {istarget "s390x*-*-*"} + +standard_testfile +set objfile [standard_output_file ${testfile}.o] + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" $objfile object {}] != "" } { + return -1 +} + +clean_restart $objfile + +gdb_test "disassemble clzg" \ + [join \ + [list \ + ".*\t" \ + "clzg\t%r0,%r3" \ + "\r\n.*"] \ + ""] -- 2.43.0 ++++++ gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-glibc-2-41.patch ++++++ >From c663bffcf74ccf94f7ff3c78b98d20fa60a09d31 Mon Sep 17 00:00:00 2001 From: Tom de Vries <tdevr...@suse.de> Date: Tue, 11 Mar 2025 09:38:50 +0100 Subject: [PATCH 2/2] [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with glibc 2.41 On openSUSE Tumbleweed, with glibc 2.41, when running test-case gdb.base/step-over-syscall.exp I run into: ... (gdb) stepi^M 0x00007ffff7cfd09b in __abort_lock_rdlock () from /lib64/libc.so.6^M 1: x/i $pc^M => 0x7ffff7cfd09b <__abort_lock_rdlock+29>: syscall^M (gdb) p $eax^M $1 = 14^M (gdb) FAIL: $exp: fork: displaced=off: syscall number matches FAIL: $exp: fork: displaced=off: find syscall insn in fork (timeout) ... We're stepi-ing through fork trying to find the fork syscall, but encounter another syscall. The test-case attempts to handle this: ... gdb_test_multiple "stepi" "find syscall insn in $syscall" { -re ".*$syscall_insn.*$gdb_prompt $" { # Is the syscall number the correct one? if {[syscall_number_matches $syscall]} { pass $gdb_test_name } else { exp_continue } } -re "x/i .*=>.*\r\n$gdb_prompt $" { incr steps if {$steps == $max_steps} { fail $gdb_test_name } else { send_gdb "stepi\n" exp_continue } } } ... but fails to do so because it issues an exp_continue without issuing a new stepi command, and consequently the "find syscall insn in fork" test times out. Also, the call to syscall_number_matches produces a PASS or FAIL, so skipping one syscall would produce: ... FAIL: $exp: fork: displaced=off: syscall number matches PASS: $exp: fork: displaced=off: syscall number matches DUPLICATE: $exp: fork: displaced=off: syscall number matches ... Fix this by: - not producing PASS or FAIL in syscall_number_matches, and - issuing stepi when encountering another syscall. While we're at it, fix indentation in syscall_number_matches. Tested on x86_64-linux, specifically: - openSUSE Tumbleweed (glibc 2.41), and - openSUSE Leap 15.6 (glibc 2.38). PR testsuite/32780 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32780 --- gdb/testsuite/gdb.base/step-over-syscall.exp | 24 ++++++++++++++------ 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/gdb/testsuite/gdb.base/step-over-syscall.exp b/gdb/testsuite/gdb.base/step-over-syscall.exp index b3b02acc553..cd1683d3dde 100644 --- a/gdb/testsuite/gdb.base/step-over-syscall.exp +++ b/gdb/testsuite/gdb.base/step-over-syscall.exp @@ -62,14 +62,18 @@ proc_with_prefix check_pc_after_cross_syscall { displaced syscall syscall_insn_n # Verify the syscall number is the correct one. proc syscall_number_matches { syscall } { - global syscall_register syscall_number + global syscall_register syscall_number - if {[gdb_test "p \$$syscall_register" ".*= $syscall_number($syscall)" \ - "syscall number matches"] != 0} { - return 0 - } + set res 0 + gdb_test_multiple "p \$$syscall_register" "syscall number matches" { + -re -wrap ".*= $syscall_number($syscall)" { + set res 1 + } + -re -wrap "" { + } + } - return 1 + return $res } # Restart GDB and set up the test. Return a list in which the first one @@ -139,7 +143,13 @@ proc setup { syscall } { if {[syscall_number_matches $syscall]} { pass $gdb_test_name } else { - exp_continue + incr steps + if {$steps == $max_steps} { + fail $gdb_test_name + } else { + send_gdb "stepi\n" + exp_continue + } } } -re "x/i .*=>.*\r\n$gdb_prompt $" { -- 2.43.0 ++++++ gdb-testsuite-fix-gdb.base-step-over-syscall.exp-with-m32-for-amd.patch ++++++ >From 7be3afccde80f7c580226f08715c181fd3f48e43 Mon Sep 17 00:00:00 2001 From: Tom de Vries <tdevr...@suse.de> Date: Sat, 8 Mar 2025 09:52:08 +0100 Subject: [PATCH 1/2] [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32 for AMD When running test-case gdb.base/step-over-syscall.exp with target board unix/-m32 on an AMD processor, I run into: ... (gdb) x/2i $pc^M => 0xf7fc9575 <__kernel_vsyscall+5>: syscall^M 0xf7fc9577 <__kernel_vsyscall+7>: int $0x80^M (gdb) PASS: $exp: fork: displaced=off: pc before/after syscall instruction stepi^M [Detaching after fork from child process 65650]^M 0xf7fc9579 in __kernel_vsyscall ()^M 1: x/i $pc^M => 0xf7fc9579 <__kernel_vsyscall+9>: pop %ebp^M (gdb) $exp: fork: displaced=off: stepi fork insn print /x $pc^M $2 = 0xf7fc9579^M (gdb) PASS: gdb.base/step-over-syscall.exp: fork: displaced=off: pc after stepi FAIL: $exp: fork: displaced=off: pc after stepi matches insn addr after syscall ... The problem is that the syscall returns at the "pop %ebp" insn, while the test-case expects it to return at the "int $0x80" insn. This is similar to the problem I fixed in commit 14852123287 ("[gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32"), just that the syscall sequence used there used the "sysenter" insn instead of the "syscall" insn. Fix this by extending the fix for commit 14852123287 to also handle the "syscall" insn. Tested on x86_64-linux, both using an AMD and Intel processor. PR testsuite/32439 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32439 --- gdb/testsuite/gdb.base/step-over-syscall.exp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdb/testsuite/gdb.base/step-over-syscall.exp b/gdb/testsuite/gdb.base/step-over-syscall.exp index 8cacc0962c3..b3b02acc553 100644 --- a/gdb/testsuite/gdb.base/step-over-syscall.exp +++ b/gdb/testsuite/gdb.base/step-over-syscall.exp @@ -176,7 +176,7 @@ proc setup { syscall } { # 0xf7fd5159 <__kernel_vsyscall+9>: pop %ebp # then a stepi at sysenter will step over the int insn, so make sure # next_insn_addr points after the int insn. - if { $actual_syscall_insn == "sysenter" } { + if { $actual_syscall_insn == "sysenter" || $actual_syscall_insn == "syscall" } { set test "pc after sysenter instruction" set re_int_insn "\[ \t\]*int\[ \t\]\[^\r\n\]*" set re [multi_line \ base-commit: 5754dc6554eb0ffef484ce898537846a6247f4a9 -- 2.43.0 ++++++ opcodes-fix-std-gnu23-compatibility-wrt-static_asser.patch ++++++ >From 899cec1550fa94e4644a3d5be4a229eb89b856d3 Mon Sep 17 00:00:00 2001 From: Sam James <s...@gentoo.org> Date: Fri, 7 Mar 2025 13:06:52 +0100 Subject: [PATCH 05/10] opcodes: fix -std=gnu23 compatibility wrt static_assert static_assert is declared in C23 so we can't reuse that identifier: * Define our own static_assert conditionally; * Rename "static assert" hacks to _N as we do already in some places to avoid a conflict. ChangeLog: PR ld/32372 * i386-gen.c (static_assert): Define conditionally. * mips-formats.h (MAPPED_INT): Rename identifier. (MAPPED_REG): Rename identifier. (OPTIONAL_MAPPED_REG): Rename identifier. * s390-opc.c (static_assert): Define conditionally. (cherry picked from commit 8ebe62f3f0d) (cherry pick dropped: opcodes/i386-gen.c) (cherry pick dropped: opcodes/mips-formats.h) --- opcodes/s390-opc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 9d9f0973e55..49efd714157 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -36,7 +36,9 @@ /* Build-time checks are preferrable over runtime ones. Use this construct in preference where possible. */ +#ifndef static_assert #define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); })) +#endif #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -- 2.43.0 ++++++ qa.sh ++++++ --- /var/tmp/diff_new_pack.esd5Vf/_old 2025-03-16 18:58:26.232094316 +0100 +++ /var/tmp/diff_new_pack.esd5Vf/_new 2025-03-16 18:58:26.236094483 +0100 @@ -364,6 +364,9 @@ # https://sourceware.org/bugzilla/show_bug.cgi?id=32167 "FAIL: gdb.base/bp-cmds-continue-ctrl-c.exp: (attach|run): stop with control-c" + # https://sourceware.org/bugzilla/show_bug.cgi?id=32688 + "FAIL: gdb.threads/thread-specific-bp.exp: non_stop=on: continue to end" + ) # kfail kfail_sle12=( @@ -544,6 +547,9 @@ # https://sourceware.org/bugzilla/show_bug.cgi?id=31564 "FAIL: gdb.base/rtld-step.exp: runto: run to main" + # https://sourceware.org/bugzilla/show_bug.cgi?id=32678 + "FAIL: gdb.reverse/time-reverse.exp: mode=c:" + ) # kfail_factory kfail_aarch64=( @@ -768,8 +774,6 @@ "FAIL: gdb.base/valgrind-infcall-2.exp:" "FAIL: gdb.base/valgrind-infcall.exp:" - # https://sourceware.org/bugzilla/show_bug.cgi?id=32678 - "FAIL: gdb.reverse/time-reverse.exp: mode=c:" ) kfail_arm=( ++++++ s390-add-arch15-concurrent-functions-facility-insns.patch ++++++ >From e709a3a30769a61def5e0995e8b4b0d94815e6ea Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:53 +0100 Subject: [PATCH 07/10] s390: Add arch15 Concurrent-Functions Facility insns opcodes/ * s390-opc.txt: Add arch15 Concurrent-Functions Facility instructions. * s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF instruction format variant. gas/testsuite/ * gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions Facility instructions. * gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit 76445f36a2f) (cherry pick dropped: gas/testsuite/gas/s390/zarch-arch15.d) (cherry pick dropped: gas/testsuite/gas/s390/zarch-arch15.s) --- opcodes/s390-opc.c | 2 ++ opcodes/s390-opc.txt | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 49efd714157..23c1c3a24e5 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -468,6 +468,7 @@ unused_s390_operands_static_asserts (void) #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ +#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */ #define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */ @@ -700,6 +701,7 @@ unused_s390_operands_static_asserts (void) #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 82d6f06a992..68d8896bf4e 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -2190,3 +2190,11 @@ e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch + +# Concurrent-Functions Facility + +c806 cal SSF_RRDRD2 "compare and load 32" arch15 zarch +c807 calg SSF_RRDRD2 "compare and load 64" arch15 zarch +c80f calgf SSF_RRDRD2 "compare and load 64<32" arch15 zarch + +eb0000000016 pfcr RSY_RRRD "perform functions with concurrent results" arch15 zarch -- 2.43.0 ++++++ s390-add-arch15-instruction-names.patch ++++++ >From b813112665aa35b5d5f7f76f26b0f3035bc5a98b Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:52 +0100 Subject: [PATCH 06/10] s390: Add arch15 instruction names opcodes/ * s390-opc.txt: Add arch15 instruction names. Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit b0588b2173b) --- opcodes/s390-opc.txt | 220 ++++++++++++++++++++++--------------------- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index bbc00b10355..82d6f06a992 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -2076,109 +2076,117 @@ b28f qpaci S_RD "query processor activity counter information" arch14 zarch # arch15 instructions -e70000000089 vblend VRR_VVVU0V " " arch15 zarch -e70000000089 vblendb VRR_VVV0V " " arch15 zarch -e70001000089 vblendh VRR_VVV0V " " arch15 zarch -e70002000089 vblendf VRR_VVV0V " " arch15 zarch -e70003000089 vblendg VRR_VVV0V " " arch15 zarch -e70004000089 vblendq VRR_VVV0V " " arch15 zarch - -e70000000088 veval VRI_VVV0UV " " arch15 zarch - -e70000000054 vgem VRR_VV0U " " arch15 zarch -e70000000054 vgemb VRR_VV " " arch15 zarch -e70000001054 vgemh VRR_VV " " arch15 zarch -e70000002054 vgemf VRR_VV " " arch15 zarch -e70000003054 vgemg VRR_VV " " arch15 zarch -e70000004054 vgemq VRR_VV " " arch15 zarch - -e700000030d7 vuphg VRR_VV " " arch15 zarch -e700000030d5 vuplhg VRR_VV " " arch15 zarch -e700000030d6 vuplg VRR_VV " " arch15 zarch -e700000030d4 vupllg VRR_VV " " arch15 zarch - -e700000040f2 vavgq VRR_VVV " " arch15 zarch -e700000040f0 vavglq VRR_VVV " " arch15 zarch -e700000040db vecq VRR_VV " " arch15 zarch -e700000040d9 veclq VRR_VV " " arch15 zarch -e700000040f8 vceqq VRR_VVV " " arch15 zarch -e700001040f8 vceqqs VRR_VVV " " arch15 zarch -e700000040fb vchq VRR_VVV " " arch15 zarch -e700001040fb vchqs VRR_VVV " " arch15 zarch -e700000040f9 vchlq VRR_VVV " " arch15 zarch -e700001040f9 vchlqs VRR_VVV " " arch15 zarch -e70000004053 vclzq VRR_VV " " arch15 zarch -e70000004052 vctzq VRR_VV " " arch15 zarch -e700000040de vlcq VRR_VV " " arch15 zarch -e700000040df vlpq VRR_VV " " arch15 zarch -e700000040ff vmxq VRR_VVV " " arch15 zarch -e700000040fd vmxlq VRR_VVV " " arch15 zarch -e700000040fe vmnq VRR_VVV " " arch15 zarch -e700000040fc vmnlq VRR_VVV " " arch15 zarch -e700030000aa vmalg VRR_VVV0V " " arch15 zarch -e700040000aa vmalq VRR_VVV0V " " arch15 zarch -e700030000ab vmahg VRR_VVV0V " " arch15 zarch -e700040000ab vmahq VRR_VVV0V " " arch15 zarch -e700030000a9 vmalhg VRR_VVV0V " " arch15 zarch -e700040000a9 vmalhq VRR_VVV0V " " arch15 zarch -e700030000ae vmaeg VRR_VVV0V " " arch15 zarch -e700030000ac vmaleg VRR_VVV0V " " arch15 zarch -e700030000af vmaog VRR_VVV0V " " arch15 zarch -e700030000ad vmalog VRR_VVV0V " " arch15 zarch -e700000030a3 vmhg VRR_VVV " " arch15 zarch -e700000040a3 vmhq VRR_VVV " " arch15 zarch -e700000030a1 vmlhg VRR_VVV " " arch15 zarch -e700000040a1 vmlhq VRR_VVV " " arch15 zarch -e700000030a2 vmlg VRR_VVV " " arch15 zarch -e700000040a2 vmlq VRR_VVV " " arch15 zarch -e700000030a6 vmeg VRR_VVV " " arch15 zarch -e700000030a4 vmleg VRR_VVV " " arch15 zarch -e700000030a7 vmog VRR_VVV " " arch15 zarch -e700000030a5 vmlog VRR_VVV " " arch15 zarch - -e700000000b2 vd VRR_VVV0UU " " arch15 zarch -e700000020b2 vdf VRR_VVV0U02 " " arch15 zarch -e700000030b2 vdg VRR_VVV0U02 " " arch15 zarch -e700000040b2 vdq VRR_VVV0U02 " " arch15 zarch - -e700000000b0 vdl VRR_VVV0UU " " arch15 zarch -e700000020b0 vdlf VRR_VVV0U02 " " arch15 zarch -e700000030b0 vdlg VRR_VVV0U02 " " arch15 zarch -e700000040b0 vdlq VRR_VVV0U02 " " arch15 zarch - -e700000000b3 vr VRR_VVV0UU " " arch15 zarch -e700000020b3 vrf VRR_VVV0U02 " " arch15 zarch -e700000030b3 vrg VRR_VVV0U02 " " arch15 zarch -e700000040b3 vrq VRR_VVV0U02 " " arch15 zarch - -e700000000b1 vrl VRR_VVV0UU " " arch15 zarch -e700000020b1 vrlf VRR_VVV0U02 " " arch15 zarch -e700000030b1 vrlg VRR_VVV0U02 " " arch15 zarch -e700000040b1 vrlq VRR_VVV0U02 " " arch15 zarch - -b968 clzg RRE_RR " " arch15 zarch -b969 ctzg RRE_RR " " arch15 zarch - -e30000000060 lxab RXY_RRRD " " arch15 zarch -e30000000062 lxah RXY_RRRD " " arch15 zarch -e30000000064 lxaf RXY_RRRD " " arch15 zarch -e30000000066 lxag RXY_RRRD " " arch15 zarch -e30000000068 lxaq RXY_RRRD " " arch15 zarch - -e30000000061 llxab RXY_RRRD " " arch15 zarch -e30000000063 llxah RXY_RRRD " " arch15 zarch -e30000000065 llxaf RXY_RRRD " " arch15 zarch -e30000000067 llxag RXY_RRRD " " arch15 zarch -e30000000069 llxaq RXY_RRRD " " arch15 zarch - -b96c bextg RRF_R0RR2 " " arch15 zarch -b96d bdepg RRF_R0RR2 " " arch15 zarch - -b93e kimd RRF_U0RR " " arch15 zarch optparm -b93f klmd RRF_U0RR " " arch15 zarch optparm - -e6000000004e vcvbq VRR_VV0U2 " " arch15 zarch -e6000000004a vcvdq VRI_VV0UU " " arch15 zarch - -e6000000005f vtp VRR_0V0U " " arch15 zarch optparm -e6000000007f vtz VRR_0VVU " " arch15 zarch +# Vector-Enhancements Facility 3 + +e70000000089 vblend VRR_VVVU0V "vector blend" arch15 zarch +e70000000089 vblendb VRR_VVV0V "vector blend byte" arch15 zarch +e70001000089 vblendh VRR_VVV0V "vector blend halfword" arch15 zarch +e70002000089 vblendf VRR_VVV0V "vector blend word" arch15 zarch +e70003000089 vblendg VRR_VVV0V "vector blend doubleword" arch15 zarch +e70004000089 vblendq VRR_VVV0V "vector blend quadword" arch15 zarch + +e70000000088 veval VRI_VVV0UV "vector evaluate" arch15 zarch + +e70000000054 vgem VRR_VV0U "vector generate element masks" arch15 zarch +e70000000054 vgemb VRR_VV "vector generate element masks byte" arch15 zarch +e70000001054 vgemh VRR_VV "vector generate element masks halfword" arch15 zarch +e70000002054 vgemf VRR_VV "vector generate element masks word" arch15 zarch +e70000003054 vgemg VRR_VV "vector generate element masks doubleword" arch15 zarch +e70000004054 vgemq VRR_VV "vector generate element masks quadword" arch15 zarch + +e700000030d7 vuphg VRR_VV "vector unpack high doubleword" arch15 zarch +e700000030d5 vuplhg VRR_VV "vector unpack logical high doubleword" arch15 zarch +e700000030d6 vuplg VRR_VV "vector unpack low doubleword" arch15 zarch +e700000030d4 vupllg VRR_VV "vector unpack logical low doubleword" arch15 zarch + +e700000040f2 vavgq VRR_VVV "vector average quadword" arch15 zarch +e700000040f0 vavglq VRR_VVV "vector average logical quadword" arch15 zarch +e700000040db vecq VRR_VV "vector element compare quadword" arch15 zarch +e700000040d9 veclq VRR_VV "vector element compare logical quadword" arch15 zarch +e700000040f8 vceqq VRR_VVV "vector compare equal quadword" arch15 zarch +e700001040f8 vceqqs VRR_VVV "vector compare equal quadword" arch15 zarch +e700000040fb vchq VRR_VVV "vector compare high quadword" arch15 zarch +e700001040fb vchqs VRR_VVV "vector compare high quadword" arch15 zarch +e700000040f9 vchlq VRR_VVV "vector compare high logical quadword" arch15 zarch +e700001040f9 vchlqs VRR_VVV "vector compare high logical quadword" arch15 zarch +e70000004053 vclzq VRR_VV "vector count leading zeros quadword" arch15 zarch +e70000004052 vctzq VRR_VV "vector count trailing zeros quadword" arch15 zarch +e700000040de vlcq VRR_VV "vector load complement quadword" arch15 zarch +e700000040df vlpq VRR_VV "vector load positive quadword" arch15 zarch +e700000040ff vmxq VRR_VVV "vector maximum quadword" arch15 zarch +e700000040fd vmxlq VRR_VVV "vector maximum logical quadword" arch15 zarch +e700000040fe vmnq VRR_VVV "vector minimum quadword" arch15 zarch +e700000040fc vmnlq VRR_VVV "vector minimum logical quadword" arch15 zarch +e700030000aa vmalg VRR_VVV0V "vector multiply and add low doubleword" arch15 zarch +e700040000aa vmalq VRR_VVV0V "vector multiply and add low quadword" arch15 zarch +e700030000ab vmahg VRR_VVV0V "vector multiply and add high doubleword" arch15 zarch +e700040000ab vmahq VRR_VVV0V "vector multiply and add high quadword" arch15 zarch +e700030000a9 vmalhg VRR_VVV0V "vector multiply and add logical high doubleword" arch15 zarch +e700040000a9 vmalhq VRR_VVV0V "vector multiply and add logical high quadword" arch15 zarch +e700030000ae vmaeg VRR_VVV0V "vector multiply and add even doubleword" arch15 zarch +e700030000ac vmaleg VRR_VVV0V "vector multiply and add logical even doubleword" arch15 zarch +e700030000af vmaog VRR_VVV0V "vector multiply and add odd doubleword" arch15 zarch +e700030000ad vmalog VRR_VVV0V "vector multiply and add logical odd doubleword" arch15 zarch +e700000030a3 vmhg VRR_VVV "vector multiply high doubleword" arch15 zarch +e700000040a3 vmhq VRR_VVV "vector multiply high quadword" arch15 zarch +e700000030a1 vmlhg VRR_VVV "vector multiply logical high doubleword" arch15 zarch +e700000040a1 vmlhq VRR_VVV "vector multiply logical high quadword" arch15 zarch +e700000030a2 vmlg VRR_VVV "vector multiply low doubleword" arch15 zarch +e700000040a2 vmlq VRR_VVV "vector multiply low quadword" arch15 zarch +e700000030a6 vmeg VRR_VVV "vector multiply even doubleword" arch15 zarch +e700000030a4 vmleg VRR_VVV "vector multiply logical even doubleword" arch15 zarch +e700000030a7 vmog VRR_VVV "vector multiply odd doubleword" arch15 zarch +e700000030a5 vmlog VRR_VVV "vector multiply logical odd doubleword" arch15 zarch + +e700000000b2 vd VRR_VVV0UU "vector divide" arch15 zarch +e700000020b2 vdf VRR_VVV0U02 "vector divide word" arch15 zarch +e700000030b2 vdg VRR_VVV0U02 "vector divide doubleword" arch15 zarch +e700000040b2 vdq VRR_VVV0U02 "vector divide quadword" arch15 zarch + +e700000000b0 vdl VRR_VVV0UU "vector divide logical" arch15 zarch +e700000020b0 vdlf VRR_VVV0U02 "vector divide logical word" arch15 zarch +e700000030b0 vdlg VRR_VVV0U02 "vector divide logical doubleword" arch15 zarch +e700000040b0 vdlq VRR_VVV0U02 "vector divide logical quadword" arch15 zarch + +e700000000b3 vr VRR_VVV0UU "vector remainder" arch15 zarch +e700000020b3 vrf VRR_VVV0U02 "vector remainder word" arch15 zarch +e700000030b3 vrg VRR_VVV0U02 "vector remainder doubleword" arch15 zarch +e700000040b3 vrq VRR_VVV0U02 "vector remainder quadword" arch15 zarch + +e700000000b1 vrl VRR_VVV0UU "vector remainder logical" arch15 zarch +e700000020b1 vrlf VRR_VVV0U02 "vector remainder logical word" arch15 zarch +e700000030b1 vrlg VRR_VVV0U02 "vector remainder logical doubleword" arch15 zarch +e700000040b1 vrlq VRR_VVV0U02 "vector remainder logical quadword" arch15 zarch + +# Miscellaneous-Instruction-Extensions Facility 4 + +b968 clzg RRE_RR "count leading zeros" arch15 zarch +b969 ctzg RRE_RR "count trailing zeros" arch15 zarch + +e30000000060 lxab RXY_RRRD "load indexed address (shift left 0)" arch15 zarch +e30000000062 lxah RXY_RRRD "load indexed address (shift left 1)" arch15 zarch +e30000000064 lxaf RXY_RRRD "load indexed address (shift left 2)" arch15 zarch +e30000000066 lxag RXY_RRRD "load indexed address (shift left 3)" arch15 zarch +e30000000068 lxaq RXY_RRRD "load indexed address (shift left 4)" arch15 zarch + +e30000000061 llxab RXY_RRRD "load logical indexed address (shift left 0)" arch15 zarch +e30000000063 llxah RXY_RRRD "load logical indexed address (shift left 1)" arch15 zarch +e30000000065 llxaf RXY_RRRD "load logical indexed address (shift left 2)" arch15 zarch +e30000000067 llxag RXY_RRRD "load logical indexed address (shift left 3)" arch15 zarch +e30000000069 llxaq RXY_RRRD "load logical indexed address (shift left 4)" arch15 zarch + +b96c bextg RRF_R0RR2 "bit extract" arch15 zarch +b96d bdepg RRF_R0RR2 "bit deposit" arch15 zarch + +# Message-Security-Assist Extension 12 + +b93e kimd RRF_U0RR "compute intermediate message digest" arch15 zarch optparm +b93f klmd RRF_U0RR "compute last message digest" arch15 zarch optparm + +# Vector-Packed-Decimal-Enhancement Facility 3 + +e6000000004e vcvbq VRR_VV0U2 "vector convert to binary 128 bit" arch15 zarch +e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch + +e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm +e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch -- 2.43.0 ++++++ s390-add-arch15-instructions.patch ++++++ >From e6ae6b0fa91079a90643c04a57a9efdb2b97644c Mon Sep 17 00:00:00 2001 From: Andreas Krebbel <kreb...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:52 +0100 Subject: [PATCH 04/10] s390: Add arch15 instructions opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <kreb...@linux.ibm.com> Reviewed-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit a98a6fa2d8e) (cherry pick dropped: gas/config/tc-s390.c) (cherry pick dropped: gas/doc/as.texi) (cherry pick dropped: gas/doc/c-s390.texi) (cherry pick dropped: gas/testsuite/gas/s390/s390.exp) (cherry pick dropped: gas/testsuite/gas/s390/zarch-arch15.d) (cherry pick dropped: gas/testsuite/gas/s390/zarch-arch15.s) --- include/opcode/s390.h | 1 + opcodes/s390-mkopc.c | 2 + opcodes/s390-opc.c | 18 +++++-- opcodes/s390-opc.txt | 110 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 128 insertions(+), 3 deletions(-) diff --git a/include/opcode/s390.h b/include/opcode/s390.h index 8de03701172..8322882410e 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -45,6 +45,7 @@ enum s390_opcode_cpu_val S390_OPCODE_ARCH12, S390_OPCODE_ARCH13, S390_OPCODE_ARCH14, + S390_OPCODE_ARCH15, S390_OPCODE_MAXCPU }; diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c index 1f5729a3db0..825188407ee 100644 --- a/opcodes/s390-mkopc.c +++ b/opcodes/s390-mkopc.c @@ -443,6 +443,8 @@ main (void) else if (strcmp (cpu_string, "z16") == 0 || strcmp (cpu_string, "arch14") == 0) min_cpu = S390_OPCODE_ARCH14; + else if (strcmp (cpu_string, "arch15") == 0) + min_cpu = S390_OPCODE_ARCH15; else { print_error ("Mnemonic \"%s\": Couldn't parse CPU string: %s\n", mnemonic, cpu_string); diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index fe0299aa4e5..9d9f0973e55 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -228,7 +228,9 @@ const struct s390_operand s390_operands[] = { 12, 16, 0 }, #define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */ +#define U16_20 (U16_16 + 1) /* 16 bit unsigned value starting at 20 */ + { 16, 20, 0 }, +#define U16_32 (U16_20 + 1) /* 16 bit unsigned value starting at 32 */ { 16, 32, 0 }, #define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */ { 32, 16, 0 }, @@ -484,6 +486,8 @@ unused_s390_operands_static_asserts (void) #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ #define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ #define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ +#define INSTR_VRI_VV0UU 6, { V_8,V_12,U8_28,U4_24,0,0 } /* e.g. vcvdq */ +#define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ #define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ @@ -494,10 +498,10 @@ unused_s390_operands_static_asserts (void) #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ #define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ -#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ +#define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ #define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/ #define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/ #define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/ @@ -523,6 +527,9 @@ unused_s390_operands_static_asserts (void) #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ +#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ +#define INSTR_VRR_0V0U 6, { V_12,U16_20,0,0,0,0 } /* e.g. vtp */ +#define INSTR_VRR_0VVU 6, { V_12,V_16,U16_20,0,0,0 } /* e.g. vtz */ #define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ #define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ #define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */ @@ -711,6 +718,8 @@ unused_s390_operands_static_asserts (void) #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRI_VV0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0UV { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } @@ -721,10 +730,10 @@ unused_s390_operands_static_asserts (void) #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } #define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } -#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } +#define MASK_VRR_VVV0U02 { 0xff, 0x00, 0x0f, 0xf0, 0xf0, 0xff } #define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } #define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } #define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } @@ -750,6 +759,9 @@ unused_s390_operands_static_asserts (void) #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } +#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRR_0V0U { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff } +#define MASK_VRR_0VVU { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } #define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } #define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } #define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 4610a8fddd7..bbc00b10355 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -2072,3 +2072,113 @@ b201 stbear S_RD "store bear" arch14 zarch # Processor-Activity-Instrumentation Facility b28f qpaci S_RD "query processor activity counter information" arch14 zarch + + +# arch15 instructions + +e70000000089 vblend VRR_VVVU0V " " arch15 zarch +e70000000089 vblendb VRR_VVV0V " " arch15 zarch +e70001000089 vblendh VRR_VVV0V " " arch15 zarch +e70002000089 vblendf VRR_VVV0V " " arch15 zarch +e70003000089 vblendg VRR_VVV0V " " arch15 zarch +e70004000089 vblendq VRR_VVV0V " " arch15 zarch + +e70000000088 veval VRI_VVV0UV " " arch15 zarch + +e70000000054 vgem VRR_VV0U " " arch15 zarch +e70000000054 vgemb VRR_VV " " arch15 zarch +e70000001054 vgemh VRR_VV " " arch15 zarch +e70000002054 vgemf VRR_VV " " arch15 zarch +e70000003054 vgemg VRR_VV " " arch15 zarch +e70000004054 vgemq VRR_VV " " arch15 zarch + +e700000030d7 vuphg VRR_VV " " arch15 zarch +e700000030d5 vuplhg VRR_VV " " arch15 zarch +e700000030d6 vuplg VRR_VV " " arch15 zarch +e700000030d4 vupllg VRR_VV " " arch15 zarch + +e700000040f2 vavgq VRR_VVV " " arch15 zarch +e700000040f0 vavglq VRR_VVV " " arch15 zarch +e700000040db vecq VRR_VV " " arch15 zarch +e700000040d9 veclq VRR_VV " " arch15 zarch +e700000040f8 vceqq VRR_VVV " " arch15 zarch +e700001040f8 vceqqs VRR_VVV " " arch15 zarch +e700000040fb vchq VRR_VVV " " arch15 zarch +e700001040fb vchqs VRR_VVV " " arch15 zarch +e700000040f9 vchlq VRR_VVV " " arch15 zarch +e700001040f9 vchlqs VRR_VVV " " arch15 zarch +e70000004053 vclzq VRR_VV " " arch15 zarch +e70000004052 vctzq VRR_VV " " arch15 zarch +e700000040de vlcq VRR_VV " " arch15 zarch +e700000040df vlpq VRR_VV " " arch15 zarch +e700000040ff vmxq VRR_VVV " " arch15 zarch +e700000040fd vmxlq VRR_VVV " " arch15 zarch +e700000040fe vmnq VRR_VVV " " arch15 zarch +e700000040fc vmnlq VRR_VVV " " arch15 zarch +e700030000aa vmalg VRR_VVV0V " " arch15 zarch +e700040000aa vmalq VRR_VVV0V " " arch15 zarch +e700030000ab vmahg VRR_VVV0V " " arch15 zarch +e700040000ab vmahq VRR_VVV0V " " arch15 zarch +e700030000a9 vmalhg VRR_VVV0V " " arch15 zarch +e700040000a9 vmalhq VRR_VVV0V " " arch15 zarch +e700030000ae vmaeg VRR_VVV0V " " arch15 zarch +e700030000ac vmaleg VRR_VVV0V " " arch15 zarch +e700030000af vmaog VRR_VVV0V " " arch15 zarch +e700030000ad vmalog VRR_VVV0V " " arch15 zarch +e700000030a3 vmhg VRR_VVV " " arch15 zarch +e700000040a3 vmhq VRR_VVV " " arch15 zarch +e700000030a1 vmlhg VRR_VVV " " arch15 zarch +e700000040a1 vmlhq VRR_VVV " " arch15 zarch +e700000030a2 vmlg VRR_VVV " " arch15 zarch +e700000040a2 vmlq VRR_VVV " " arch15 zarch +e700000030a6 vmeg VRR_VVV " " arch15 zarch +e700000030a4 vmleg VRR_VVV " " arch15 zarch +e700000030a7 vmog VRR_VVV " " arch15 zarch +e700000030a5 vmlog VRR_VVV " " arch15 zarch + +e700000000b2 vd VRR_VVV0UU " " arch15 zarch +e700000020b2 vdf VRR_VVV0U02 " " arch15 zarch +e700000030b2 vdg VRR_VVV0U02 " " arch15 zarch +e700000040b2 vdq VRR_VVV0U02 " " arch15 zarch + +e700000000b0 vdl VRR_VVV0UU " " arch15 zarch +e700000020b0 vdlf VRR_VVV0U02 " " arch15 zarch +e700000030b0 vdlg VRR_VVV0U02 " " arch15 zarch +e700000040b0 vdlq VRR_VVV0U02 " " arch15 zarch + +e700000000b3 vr VRR_VVV0UU " " arch15 zarch +e700000020b3 vrf VRR_VVV0U02 " " arch15 zarch +e700000030b3 vrg VRR_VVV0U02 " " arch15 zarch +e700000040b3 vrq VRR_VVV0U02 " " arch15 zarch + +e700000000b1 vrl VRR_VVV0UU " " arch15 zarch +e700000020b1 vrlf VRR_VVV0U02 " " arch15 zarch +e700000030b1 vrlg VRR_VVV0U02 " " arch15 zarch +e700000040b1 vrlq VRR_VVV0U02 " " arch15 zarch + +b968 clzg RRE_RR " " arch15 zarch +b969 ctzg RRE_RR " " arch15 zarch + +e30000000060 lxab RXY_RRRD " " arch15 zarch +e30000000062 lxah RXY_RRRD " " arch15 zarch +e30000000064 lxaf RXY_RRRD " " arch15 zarch +e30000000066 lxag RXY_RRRD " " arch15 zarch +e30000000068 lxaq RXY_RRRD " " arch15 zarch + +e30000000061 llxab RXY_RRRD " " arch15 zarch +e30000000063 llxah RXY_RRRD " " arch15 zarch +e30000000065 llxaf RXY_RRRD " " arch15 zarch +e30000000067 llxag RXY_RRRD " " arch15 zarch +e30000000069 llxaq RXY_RRRD " " arch15 zarch + +b96c bextg RRF_R0RR2 " " arch15 zarch +b96d bdepg RRF_R0RR2 " " arch15 zarch + +b93e kimd RRF_U0RR " " arch15 zarch optparm +b93f klmd RRF_U0RR " " arch15 zarch optparm + +e6000000004e vcvbq VRR_VV0U2 " " arch15 zarch +e6000000004a vcvdq VRI_VV0UU " " arch15 zarch + +e6000000005f vtp VRR_0V0U " " arch15 zarch optparm +e6000000007f vtz VRR_0VVU " " arch15 zarch -- 2.43.0 ++++++ s390-align-opcodes-to-lower-case.patch ++++++ >From 1e4d5d4928d64022b8e17e20ffa8a7b2134842e1 Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:51 +0100 Subject: [PATCH 01/10] s390: Align opcodes to lower-case opcodes/ * s390-opc.txt (rdp): Change opcode to lower-case. Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit 1afe02759f1) --- opcodes/s390-opc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 1182e196059..4610a8fddd7 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -2061,7 +2061,7 @@ e60000000055 vcnf VRR_VV0UU2 "vector fp convert to nnp" arch14 zarch # Reset-DAT-Protection Facility -b98B rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm +b98b rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm # BEAR-Enhancement Facility base-commit: 31276843acc9aac2e5ce4a9181eecd33b0e0a6cc -- 2.43.0 ++++++ s390-fix-disassembly-of-optional-addressing-operands.patch ++++++ >From 708495beae38a6b5c265a3865f38d2be79414a63 Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:53 +0100 Subject: [PATCH 08/10] s390: Fix disassembly of optional addressing operands "nop D1(B1)" erroneously disassembled into "nop D1(B1" (missing closing parenthesis). "nop D1(X1,0)" and "nop D1(X1,)" erroneously disassembled into "nop D1(X1)" (missing zero base register) instead of "nop D1(X1,0)". Do not skip disassembly of optional operands if they are index (X) or base (B) registers or length (L) in an addressing operand sequence "D(X,B)", "D(B)", or "D(L,B). Index and base register operand values of zero are being handled separately, as they may not be omitted unconditionally. For instance a base register value of zero must be printed in above mentioned case, to distinguish the index from the base register. This also ensures proper formatting of addressing operand sequences. While at it add further test cases for instructions with optional operands. opcodes/ * s390-dis.c (s390_print_insn_with_opcode): Do not unconditionally skip disassembly of optional operands with a value of zero, if within an addressing operand sequence. gas/testsuite/ * gas/s390/zarch-optargs.d: Add further test cases for instructions with optional operands. * gas/s390/zarch-optargs.s: Likewise. Reported-by: Florian Krohm <flo2...@eich-krohm.de> Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit 7507fe37980) (cherry pick dropped: gas/testsuite/gas/s390/zarch-optargs.d) (cherry pick dropped: gas/testsuite/gas/s390/zarch-optargs.s) --- opcodes/s390-dis.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index 852d2f6ebb9..1a23afc8f40 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -214,20 +214,29 @@ s390_print_insn_with_opcode (bfd_vma memaddr, continue; } - /* For instructions with a last optional operand don't print it - if zero. */ - if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2)) - && val.u == 0 - && opindex[1] == 0) - break; - - if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2) - && val.u == 0 && opindex[1] != 0 && opindex[2] == 0) + /* Omit optional last operands with a value of zero, except if + within an addressing operand sequence D(X,B), D(B), and D(L,B). + Index and base register operands with a value of zero are + handled separately, as they may not be omitted unconditionally. */ + if (!(operand->flags & (S390_OPERAND_BASE + | S390_OPERAND_INDEX + | S390_OPERAND_LENGTH))) { - union operand_value next_op_val = - s390_extract_operand (buffer, s390_operands + opindex[1]); - if (next_op_val.u == 0) + if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2)) + && val.u == 0 + && opindex[1] == 0) break; + + if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2) + && val.u == 0 + && opindex[1] != 0 && opindex[2] == 0) + { + union operand_value next_op_val = + s390_extract_operand (buffer, s390_operands + opindex[1]); + + if (next_op_val.u == 0) + break; + } } if (flags & S390_OPERAND_GPR) @@ -312,6 +321,7 @@ s390_print_insn_with_opcode (bfd_vma memaddr, && val.u == 0 && opindex[1] == 0) break; + info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); style = ((flags & S390_OPERAND_DISP) -- 2.43.0 ++++++ s390-relax-risbg-n-z-risb-h-l-gz-rns-ros-rxs-bgt-ope.patch ++++++ >From 4ace867f88db894184062814e6ae71e0b9dfffd8 Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:51 +0100 Subject: [PATCH 03/10] s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints This leverages commit ("s390: Simplify (dis)assembly of insn operands with const bits") to relax the operand constraints of the immediate operand that contains the constant Z- or T-bit of the following extended mnemonics: risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt Previously those instructions were the only ones where the assembler on s390 restricted the specification of the subject I3/I4 operand values exactly according to their specification to an unsigned 6- or 5-bit unsigned integer. For any other instructions the assembler allows to specify any operand value allowed by the instruction format, regardless of whether the instruction specification is more restrictive. Allow to specify the subject I3/I4 operand as unsigned 8-bit integer with the constant operand bits being ORed during assembly. Relax the instructions subject significant operand bit masks to only consider the Z/T-bit as significant, so that the instructions get disassembled as their *z or *t flavor regardless of whether any reserved bits are set in addition to the Z/T-bit. Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set the T-bit in operand I3, as they otherwise get disassembled as their rnsbgt, rosbgt, and rxsbgt counterpart. This aligns GNU Assembler to LLVM Assembler. opcodes/ * s390-opc.c (U6_18, U5_27, U6_26): Remove. (INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define as INSTR_RIE_RRUUU while retaining insn fmt mask. (MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only Z/T-bit of I3/I4 operand as significant. gas/testsuite/ * gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit. Reported-by: Dominik Steenken <d...@de.ibm.com> Suggested-by: Ulrich Weigand <ulrich.weig...@de.ibm.com> Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit b8b60e2d0cb) (cherry pick dropped: gas/testsuite/gas/s390/zarch-z10.d) (cherry pick dropped: gas/testsuite/gas/s390/zarch-z10.s) --- opcodes/s390-opc.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 987004d7b07..fe0299aa4e5 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -216,15 +216,9 @@ const struct s390_operand s390_operands[] = { 4, 36, 0 }, #define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */ - { 6, 18, 0 }, -#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */ +#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */ - { 5, 27, 0 }, -#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */ - { 6, 26, 0 }, -#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */ +#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */ { 8, 24, 0 }, #define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */ { 8, 28, 0 }, @@ -288,7 +282,7 @@ unused_s390_operands_static_asserts (void) p - pc relative r - general purpose register re - gpr extended operand, a valid general purpose register pair - u - unsigned integer, 4, 6, 8, 16 or 32 bit + u - unsigned integer, 4, 8, 16 or 32 bit m - mode field, 4 bit 0 - operand skipped. The order of the letters reflects the layout of the format in @@ -324,9 +318,9 @@ unused_s390_operands_static_asserts (void) #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ -#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */ -#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */ -#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */ +#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */ +#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */ +#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */ #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ @@ -551,9 +545,9 @@ unused_s390_operands_static_asserts (void) #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff } -#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff } -#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff } +#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } +#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } +#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff } #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -- 2.43.0 ++++++ s390-simplify-dis-assembly-of-insn-operands-with-con.patch ++++++ >From 0a5b57ac3e464b3e4a1eaf4aba5d6bd8c98b7186 Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:51 +0100 Subject: [PATCH 02/10] s390: Simplify (dis)assembly of insn operands with const bits Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit a3f1e7c56a6) (cherry pick dropped: gas/config/tc-s390.c) --- include/opcode/s390.h | 4 ---- opcodes/s390-dis.c | 14 ++++++++------ opcodes/s390-opc.c | 26 +++++++++----------------- 3 files changed, 17 insertions(+), 27 deletions(-) diff --git a/include/opcode/s390.h b/include/opcode/s390.h index e5dfcb27570..8de03701172 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -193,8 +193,4 @@ extern const struct s390_operand s390_operands[]; #define S390_OPERAND_CP16 0x1000 -#define S390_OPERAND_OR1 0x2000 -#define S390_OPERAND_OR2 0x4000 -#define S390_OPERAND_OR8 0x8000 - #endif /* S390_H */ diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index ee2f2cb62ed..852d2f6ebb9 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -299,12 +299,14 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { enum disassembler_style style; - if (flags & S390_OPERAND_OR1) - val.u &= ~1; - if (flags & S390_OPERAND_OR2) - val.u &= ~2; - if (flags & S390_OPERAND_OR8) - val.u &= ~8; + if (!(flags & S390_OPERAND_LENGTH)) + { + union operand_value insn_opval; + + /* Mask any constant operand bits set in insn template. */ + insn_opval = s390_extract_operand (opcode->opcode, operand); + val.u &= ~insn_opval.u; + } if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) && val.u == 0 diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 10482fbc1e0..987004d7b07 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -208,17 +208,9 @@ const struct s390_operand s390_operands[] = { 4, 20, 0 }, #define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */ { 4, 24, 0 }, -#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */ - { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ -#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */ - { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ -#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */ - { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ -#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */ +#define U4_28 (U4_24+1) /* 4 bit unsigned value starting at 28 */ { 4, 28, 0 }, -#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */ - { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ -#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */ +#define U4_32 (U4_28+1) /* 4 bit unsigned value starting at 32 */ { 4, 32, 0 }, #define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */ { 4, 36, 0 }, @@ -512,23 +504,23 @@ unused_s390_operands_static_asserts (void) #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ -#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ -#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ -#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/ +#define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/ +#define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/ +#define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/ #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ #define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ #define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ -#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ +#define INSTR_VRR_VV0UU8 INSTR_VRR_VV0UU /* e.g. wcdgb */ #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ #define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ #define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ -#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/ -#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/ -#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/ +#define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB /* e.g. vstrcbs*/ +#define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB /* e.g. vstrczb*/ +#define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB /* e.g. vstrczbs*/ #define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ #define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ #define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ -- 2.43.0 ++++++ s390-treat-addressing-operand-sequence-as-one-in-dis.patch ++++++ >From 921996dc9f1d1322fcad32822125546a7c6a6e93 Mon Sep 17 00:00:00 2001 From: Jens Remus <jre...@linux.ibm.com> Date: Fri, 7 Mar 2025 13:06:53 +0100 Subject: [PATCH 09/10] s390: Treat addressing operand sequence as one in disassembler Reuse logic introduced with the preceding commit in the assembler to treat addressing operand sequences D(X,B), D(B), and D(L,B) as one with regards to optional last operands (i.e. optparm and optparm2). With this "nop" now disassembles into "nop" instead of "nop 0". opcodes/ * s390-dis.c (operand_count): New helper to count the remaining operands, treating D(X,B), D(B), and D(L,B) as one. (skip_optargs_p): New helper to test whether remaining operands are optional. (skip_optargs_zero_p): New helper to test whether remaining operands are optional and their values are zero. (s390_print_insn_with_opcode): Use skip_optargs_zero_p to skip optional last operands with a value of zero. gas/testsuite/ * gas/s390/zarch-optargs.d (nop): Adjust test case accordingly. Signed-off-by: Jens Remus <jre...@linux.ibm.com> (cherry picked from commit 36bbf8646c8) (cherry pick dropped: gas/testsuite/gas/s390/zarch-optargs.d) --- opcodes/s390-dis.c | 84 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 66 insertions(+), 18 deletions(-) diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index 1a23afc8f40..8e7b9838f81 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -180,6 +180,69 @@ s390_extract_operand (const bfd_byte *insn, return ret; } +/* Return remaining operand count. */ + +static unsigned int +operand_count (const unsigned char *opindex_ptr) +{ + unsigned int count = 0; + + for (; *opindex_ptr != 0; opindex_ptr++) + { + /* Count D(X,B), D(B), and D(L,B) as one operand. Assuming correct + instruction operand definitions simply do not count D, X, and L. */ + if (!(s390_operands[*opindex_ptr].flags & (S390_OPERAND_DISP + | S390_OPERAND_INDEX + | S390_OPERAND_LENGTH))) + count++; + } + + return count; +} + +/* Return true if all remaining instruction operands are optional. */ + +static bool +skip_optargs_p (unsigned int opcode_flags, const unsigned char *opindex_ptr) +{ + if ((opcode_flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))) + { + unsigned int opcount = operand_count (opindex_ptr); + + if (opcount == 1) + return true; + + if ((opcode_flags & S390_INSTR_FLAG_OPTPARM2) && opcount == 2) + return true; + } + + return false; +} + +/* Return true if all remaining instruction operands are optional + and their values are zero. */ + +static bool +skip_optargs_zero_p (const bfd_byte *buffer, unsigned int opcode_flags, + const unsigned char *opindex_ptr) +{ + /* Test if remaining operands are optional. */ + if (!skip_optargs_p (opcode_flags, opindex_ptr)) + return false; + + /* Test if remaining operand values are zero. */ + for (; *opindex_ptr != 0; opindex_ptr++) + { + const struct s390_operand *operand = &s390_operands[*opindex_ptr]; + union operand_value value = s390_extract_operand (buffer, operand); + + if (value.u != 0) + return false; + } + + return true; +} + /* Print the S390 instruction in BUFFER, assuming that it matches the given OPCODE. */ @@ -220,24 +283,9 @@ s390_print_insn_with_opcode (bfd_vma memaddr, handled separately, as they may not be omitted unconditionally. */ if (!(operand->flags & (S390_OPERAND_BASE | S390_OPERAND_INDEX - | S390_OPERAND_LENGTH))) - { - if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2)) - && val.u == 0 - && opindex[1] == 0) - break; - - if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2) - && val.u == 0 - && opindex[1] != 0 && opindex[2] == 0) - { - union operand_value next_op_val = - s390_extract_operand (buffer, s390_operands + opindex[1]); - - if (next_op_val.u == 0) - break; - } - } + | S390_OPERAND_LENGTH)) + && skip_optargs_zero_p (buffer, opcode->flags, opindex)) + break; if (flags & S390_OPERAND_GPR) { -- 2.43.0
