Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package CoreFreq for openSUSE:Leap:16.0 checked in at 2025-08-06 17:15:22 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Leap:16.0/CoreFreq (Old) and /work/SRC/openSUSE:Leap:16.0/.CoreFreq.new.1085 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq" Wed Aug 6 17:15:22 2025 rev:2 rq:1297960 version:2.0.8 Changes: -------- --- /work/SRC/openSUSE:Leap:16.0/CoreFreq/CoreFreq.changes 2025-03-19 11:37:55.767546176 +0100 +++ /work/SRC/openSUSE:Leap:16.0/.CoreFreq.new.1085/CoreFreq.changes 2025-08-06 17:15:27.049644958 +0200 @@ -1,0 +2,316 @@ +Wed Aug 6 13:03:56 UTC 2025 - Michael Pujos <[email protected]> + +- added fix-leap16-compilation.patch to fix compilation on x86_64 Leap 16.0 + +------------------------------------------------------------------- +Sat Aug 2 13:31:16 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.8 + * [Intel] + - [Emerald Rapids] Align MSR entries with Sapphire Rapids + - [Sapphire Rapids] Xeon Scalable 4th gen. startup fix (#560) + * [AMD] + - [Zen5] Introduced a UMC capabilities decoder for STX families + - [Zen5][STX/KRK/STXH] Avoid undefined COF and Power registers + - Switch Zen5/Strix families to the Raphael voltage decoder + - [Zen5/Strix Halo] Probe Memory Controller from DID 0x12b8 + - [Zen5][Strix Halo] Adding the RYZEN AI MAX 385 + - Add fallback TjMax for legacy CPU families + - Add missing DCU and XPROC_LEAK bitmasks on legacy processors + - [Excavator] Fix setting the scope of temperature to Package + * [aarch64] + - Temperature compilation based on CONFIG_THERMAL + - Getting temperature from the Generic Thermal Management + - Provide the state of WFI/WFE Low Power Methods + - Set the UI comment for PMULL instruction + - Registers requiring a safe access guard (TID3) + - Drop Experimental guard to safely read ID_AA64MMFR3_EL1 + - Display detected Interconnect Technology in UI + - Query Cache Coherent Network|Interconnect via DT + - Added multiple Processors and Architectures: + Cortex-A320, Cortex-A520, Cortex-A720AE, Cortex-A725, + Cortex-R82AE, Cortex-X925, Neoverse N3, Neoverse V3, + Neoverse V3AE * ARMv8.1-A, ARMv8.8-A, ARMv9.1-A, ARMv9.2-A, + ARMv9.3-A + - Assign DSU-RTL version according to detected ARM arch. + - Improve detection of Mesh interconnect via DT/ACPI + - Query CMN either from DeviceTree either from ACPI + - JSON export DSU, CMN, CCI, CCN + - Display the presence of the DynamIQ Shared Unit (DSU) + - Added SMT and big.LITTLE labels in the UI footer + * [UI] + - Rephrased string for the CPUID.80000001.ECX[27] feature + - Optimize POWERED() macro with branchless 3-state array lookup + - [aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state + - [CR] In _F4() cast complement mask to the type of bit argument + * [Build] + - [CI] Comment out the unreachable debian-10-buster + - Enforce targets are not built more than necessary + - Clarify Makefile help, info, and version targets + - Support building CoreFreq binaries individually or together + +------------------------------------------------------------------- +Thu Jun 5 19:47:58 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.7 + * [Kernel] + - Defer the cpufreq get_policy and asm/amd/nb.h changes to v6.16 + +------------------------------------------------------------------- +Wed Jun 4 19:05:58 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.6 + * [Kernel] + - Fix missing cpufreq_get_policy and asm/amd/nb.h in kernel 6.15 + - Use VM_DONTEXPAND in mmap() for stability and isolation + * [AMD] + - Decodes voltages of Phoenix families using Rembrandt SVI + - Attempt to read the SoC voltage in Raphael architecture + - Don't probe the HSMP on Raphael' Desktop/Mobile/Embedded + * [Intel] + - Added the Bartlett Lake/S entry + - Clearwater Forest architecture name fix + * [AArch64] [RISC-V] [PowerPC] + - Use exclusive load/store for selected shared variables + * [Doc] + - Obfuscate support email format in README and CLI usage + - Added command line usage instructions to the README + +------------------------------------------------------------------- +Sat May 24 11:52:27 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.5 + * [Code Review] + - Restrict module parameters to load-time only + * [AMD] + - [Genoa] + - Attempt SOC voltage reading + - Apply monitoring interval to RAM consumption calculation + - [Kernel] + - Use CONFIG_AMD_NB to call SMU if kernel version ≥ 6.0 + * [Intel] + - [Core Ultra] + - Updated register names and addresses + - [Alder Lake/N] + - Added "Twin Lake" and "Amston Lake" codenames + * [x86_64] + - Added lock prefix to bit operations for cross-package atomicity + * [AArch64] [RISC-V] [PowerPC] + - Improved CPU topology detection to identify the BSP (Boot Strap Processor) + +------------------------------------------------------------------- +Wed May 14 18:27:26 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.3 + * [UI] + - Increased length of L3 cache digits in header + - [MC] Renamed Disabled to Undefined channels + - [CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number + - Display N/A when Intel processor is not HDC capable + * [Code Review] + - Refactored variable names for inclusivity + - [Kernel] VT-d: request memory region before use + - uBench: Code clean-up + * [Doc] + - README for Rocky Linux and Clear Linux + * [Build] + - Prevent module loading if detected CPU count > CORE_COUNT (case of EPYC with 384 CPUs) + - Make static the PCI list to comply with kernel frame size + - Kernel 6.15 is switching to use hrtimer_setup() + - [CI] Bump to uraimo version 3 + - of_root defined since Kernel 3.19 + - Replaced inline C functions with static or macro + - Kernel 6.14 node_to_amd_nb() workaround + - Added CONFIG_ACPI_CPPC_LIB to conditionally build EPP + - Changed some inline function prototypes + * [AMD] + - [Zen] + - Count DIMM ranks from the enabled chip select + - Now conducts Datafabric calls through Kernel PCI + - [HSMP] Provides its own lock rather than SMN' lock + - [HSMP] arguments index fix in CONFIG_AMD_NB build mode + - [HSMP] Check mailbox protocol is correctly functioning using the arithmetic addition 2 + 1 = 3 + - Replaced package thermal with a pointer function + - Specifications of some Zen registers + - Adding "Strix Halo" and "Krackan Point" architectures + - Adding "Fire Range" series + - Adding Ryzen Z2 series + - [Genoa] + - Probe up to four memory controllers + - Improved EPYC Genoa support: + - CCD and CCX topology fixed to compute the right thermal SMU address + - Increase BIT_IO_RETRIES_COUNT to parallelize HSMP_RD_DIMM_PWR calls + - Added specifics for an "Eng Sample" of Genoa architecture + - Accumulate the power consumed by RAM + - Attempt to monitor DIMM power consumption from HSMP + - Use generic voltage & power + - [Hawk Point] + - Set AddrCfg & DimmCfg addresses for Phoenix UMC + - [Family 1Ah] + - Added the HSMP for EPYC Turin + * [Intel] + - [MTL][ARL] + - Improving MC Bus and DDR speed to follow OC SOC + - Refactored IMC decoder to query DDR clock + - Merged the P-core and E-core monitoring loops + - Get/Set L1_NPP_Prefetch from MSR_MISC_FEATURE_CONTROL + - Provide monitoring functions to Arrow Lake + Also applying to Lunar Lake + - Grant ODCM and PWR MGMT accesses to MTL, ARL, Lunar Lake + - New features for Core Ultra 7 265K + - [x86_64] + - Order SMBIOS DIMM list by channel + - [IMC] Can display Twelve Channel memory controller + - SMBIOS dump resized to 12 channels multiplied 4 DIMM slots + - Compute the SMBIOS DIMM part number (rev 2) + - Check HCF capability for MPERF/APERF MSR access in VM + * [AArch64] [RISC-V] [PowerPC] + - [riscv64] Fill with the Machine Architecture ID Register marchid + - [ppc64] Added source comment + - [riscv64][ppc64] Improving Hybrid processor detection + - [ppc64] Fix the Carry flag asm code + - [ppc64] The processor version register (PVR) is a 32-bit register + - [ppc64] Use MFXER to get the XER + Raise the Carry Flag + - [ppc64][riscv64] ASM instructions for uBench macros + - [aarch64] Checking CSSELR and CCSIDR registers in ARMv9 + - [aarch64] If FEAT_CCIDX implemented read NumSets from upper reg + - [aarch64] Safely access the PMU registers + Detect the Android AVF hypervisor + Comment PMC in uBench macros + - [ppc64] Detect the IBM POWER10 Functional Simulator + - [aarch64][riscv64][ppc64] Improving DT integration to detect VM + - [AArch64] Improving virtualization detection from Device Tree + - [ppc64][riscv64] Device Tree fetching based on kernel version + - [PowerPC] Preliminary port to the ppc64le architecture + - [riscv64] Adding vendor Microchip + - [riscv64] Attempt to read the Hart ID from device tree + - [riscv64] Restore PMU counter delta calculation + - [riscv64] mvendorid & marchid based architecture qualification + - [riscv64] Specification of SSTATUS and SCOUNTEREN registers + - [riscv64] Normalize counters to work with unaccurate QEMU cycles + - [riscv64] Attempt to enable the Cycle and Instruction counters + - [riscv64] Read the performance cycles using rdcycle + - [riscv64] Read the retired instructions counter using rdinstret + - [riscv64] Get the TSC from rdtime instruction + - [riscv64] Comment out any reading of cycles + - [RISC-V] Code clean-up to debug start-up + - [RISC-V] Preliminary port of the riscv64 architecture + +------------------------------------------------------------------- +Sun Feb 16 10:27:03 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.1 + * [Build] + - Implement amd_pci_dev_to_node_id from Kernel 6.14 + - [CI] Pin build environment to ubuntu-22.04 (thanks @jlacvdr) + - Allow changing WARNING variable from command line (thanks @s-stepien) + * [AMD] + - [Strix Point] Attempt to decode UMC and IOMMU controllers + - [Raphael] Adding Ryzen 5 7400F + - [Granite Ridge] Adding Ryzen 5 9600 + +------------------------------------------------------------------- +Sun Dec 22 10:32:14 UTC 2024 - Michael Pujos <[email protected]> + +- Update to 1.98.8 + * [Build] + - [x86_64] AlmaLinux 9.5 (Teal Serval) compilation fix + - [UI] Fix System Registers window for a 3 digits CPU id number + * [Doc] + - SSH how to run the UI + * [AArch64] + - Checking specification of Memory Model Feature Registers + - Aggregate and display ISA features of ID_AA64ISAR3_EL1 + - Instruction Set Attribute Register 3 ID_AA64ISAR3_EL1 + - Processor Feature Register 2 AA64PFR2_EL1 + - Display FP and SIMD bits from MVFR + - Added remaining CLRBHB and PCDPHINT of ISAR2 + - Display the Streaming Vector Control Register SVCR + - Query and export the Media and VFP Feature Registers MVFR + - Display, export Floating-point Control Register FPCR + - Architectural Feature Access Control Register CPACR + - Display the Hypervisor Configuration Register HCR_EL2 based on CurrentEL + * [AMD] + - [VERMEER] Adding Ryzen 5 5600XT and 5600T processors + - [Zen 5c] Fixed EPYC Turin-Dense series + +------------------------------------------------------------------- +Fri Nov 22 09:42:29 UTC 2024 - Michael Pujos <[email protected]> + +- Update to 1.98.7 + * [AMD] + - [Family 1Ah][Granite Ridge] + - P-State programming fix + - Merge PCI identifier lists + - Reserve the BTC-NOBR aggregation to Zen2 architecture + * [AArch64] + - Query and JSON export Hypervisor Configuration Register HCR_EL2 + - Experimental mode required + +------------------------------------------------------------------- +Sat Nov 16 14:22:18 UTC 2024 - Michael Pujos <[email protected]> + +- Update to 1.98.6 + * [AMD] + - [V2000 Series] Adding the Ryzen Embedded V2A46 + - [Family 1Ah][All Families] Refactoring topology for CCD cluster + Confirmed 7950X, 3950X + * [Intel] + - ODCM is confirmed working on Raptor Lake architecture + Confirmed i9-14900K + * [UI] + - Increased max ratio in HWP condition to avoid a zero frequency + Confirmed i9-14900K + * [Build] + - Print other variables from Makefile recipe info + CORE_COUNT + TASK_ORDER + MAX_FREQ_HZ + HWM_CHIPSET + * [CI] + - [AArch64] Commenting out the debian-testing and alpine-latest + * [Doc] + - Mention the AMD family 1Ah support in README + +------------------------------------------------------------------- +Fri Nov 8 09:56:48 UTC 2024 - Michael Pujos <[email protected]> + +- Update to 1.98.5 + * [UI] + - Debugging a target clock ratio selector issue + * [Build] + - Makefile compliant with the -s silent option + - [CI] Disable the unfound arm64v8/ubuntu:rolling + * [AMD] + - [Strix Point] Adding PRO series + - [Zen5][Zen5c] Introducing the TURIN architecture + - Supply a fallback thermal junction max to various Zen series + - [Zen5] Mitigation mechanisms and Features bits + SBPB, + SRSO_NO, + SRSO_USR_KNL_NO, + ERMSB, + FSRS, + FSRC_CMPSB, + PREFETCHI + - [Zen] Added remaining X3D processor models ++++ 19 more lines (skipped) ++++ between /work/SRC/openSUSE:Leap:16.0/CoreFreq/CoreFreq.changes ++++ and /work/SRC/openSUSE:Leap:16.0/.CoreFreq.new.1085/CoreFreq.changes Old: ---- CoreFreq-1.98.4.tar.gz New: ---- CoreFreq-2.0.8.tar.gz fix-leap16-compilation.patch ----------(New B)---------- New: - added fix-leap16-compilation.patch to fix compilation on x86_64 Leap 16.0 ----------(New E)---------- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ CoreFreq.spec ++++++ --- /var/tmp/diff_new_pack.uUGsy7/_old 2025-08-06 17:15:27.361657981 +0200 +++ /var/tmp/diff_new_pack.uUGsy7/_new 2025-08-06 17:15:27.361657981 +0200 @@ -1,7 +1,7 @@ # # spec file for package CoreFreq # -# Copyright (c) 2024 SUSE LLC +# Copyright (c) 2025 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: CoreFreq -Version: 1.98.4 +Version: 2.0.8 Release: 0 Summary: CPU monitoring software for 64-bit processors License: GPL-2.0-or-later @@ -25,6 +25,8 @@ Source: %{url}/archive/refs/tags/%{version}.tar.gz#/%{name}-%{version}.tar.gz Source100: corefreqd.service Source101: preamble +# PATCH-FIX-OPENSUSE fix-leap16-compilation.patch bsc#1247592 +Patch: fix-leap16-compilation.patch BuildRequires: %{kernel_module_package_buildreqs} BuildRequires: pkgconfig BuildRequires: pkgconfig(libsystemd) @@ -40,7 +42,10 @@ Dhyana). %prep -%autosetup -p1 +%setup +%if 0%{?suse_version} == 1600 && 0%{?is_opensuse} +%patch -P 0 -p 1 +%endif %build %make_build ++++++ CoreFreq-1.98.4.tar.gz -> CoreFreq-2.0.8.tar.gz ++++++ ++++ 115068 lines of diff (skipped) ++++++ fix-leap16-compilation.patch ++++++ diff -ruN CoreFreq-2.0.8.orig/x86_64/corefreqk.h CoreFreq-2.0.8/x86_64/corefreqk.h --- CoreFreq-2.0.8.orig/x86_64/corefreqk.h 2025-08-06 14:14:26.771406762 +0200 +++ CoreFreq-2.0.8/x86_64/corefreqk.h 2025-08-06 15:02:28.729320262 +0200 @@ -700,7 +700,7 @@ #if defined(CONFIG_AMD_NB) && LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0) -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 14, 0) /* asm/amd_node.h */ + static u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) { return PCI_SLOT(pdev->devfn) - AMD_NODE0_PCI_SLOT; @@ -708,9 +708,6 @@ #define GetRootFromNode(_node) pci_get_domain_bus_and_slot( 0x0, 0x0, \ PCI_DEVFN(0x0, 0x0) ) -#else -#define GetRootFromNode(_node) node_to_amd_nb(_node)->root -#endif #define AMD_SMN_RW(node, address, value, write, indexPort, dataPort) \ ({ \
