Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package CoreFreq for openSUSE:Factory checked in at 2025-11-11 19:21:40 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old) and /work/SRC/openSUSE:Factory/.CoreFreq.new.1980 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq" Tue Nov 11 19:21:40 2025 rev:48 rq:1317091 version:2.0.9 Changes: -------- --- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2025-08-13 18:16:10.417098420 +0200 +++ /work/SRC/openSUSE:Factory/.CoreFreq.new.1980/CoreFreq.changes 2025-11-11 19:22:30.038397865 +0100 @@ -1,0 +2,22 @@ +Tue Nov 11 12:30:12 UTC 2025 - Michael Pujos <[email protected]> + +- Update to 2.0.9 + * [AMD] + - Adding Ryzen Z2 A and Ryzen AI Z2 Extreme + - [Turin][Dense] Complete the EPYC Embedded 9005 Series + - Adding the Ryzen 5 5500X3D processor + - Complete the Ryzen 8000 Series + - [Zen5][SHP] Introducing the Shimada Peak architecture + - [Family 15h] Provides Package voltage from Core aggregation + * [Intel] + - [Skylake/X] Provides Package voltage from Core aggregation + * [x86_64] + - [Virtualization] Initialized DCU_Mask bitmask + * [aarch64] + - Pass explicit variable-immediate type to fix assembly + * [Build] + - [x86_64] Fedora v34 api fix detecting RHEL MINOR 99 + - [Kernel][aarch64] Set mcelsius based on thermal_zone_get_temp() + - [Kernel] Preparing for the impacts of kernel version 6.18 + +------------------------------------------------------------------- Old: ---- CoreFreq-2.0.8.tar.gz New: ---- CoreFreq-2.0.9.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ CoreFreq.spec ++++++ --- /var/tmp/diff_new_pack.x6mzeP/_old 2025-11-11 19:22:30.778428859 +0100 +++ /var/tmp/diff_new_pack.x6mzeP/_new 2025-11-11 19:22:30.778428859 +0100 @@ -1,7 +1,7 @@ # # spec file for package CoreFreq # -# Copyright (c) 2025 SUSE LLC +# Copyright (c) 2025 SUSE LLC and contributors # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: CoreFreq -Version: 2.0.8 +Version: 2.0.9 Release: 0 Summary: CPU monitoring software for 64-bit processors License: GPL-2.0-or-later ++++++ CoreFreq-2.0.8.tar.gz -> CoreFreq-2.0.9.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/Makefile new/CoreFreq-2.0.9/Makefile --- old/CoreFreq-2.0.8/Makefile 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/Makefile 2025-11-10 10:51:24.000000000 +0100 @@ -4,7 +4,7 @@ COREFREQ_MAJOR = 2 COREFREQ_MINOR = 0 -COREFREQ_REV = 8 +COREFREQ_REV = 9 HW = $(shell uname -m) CC ?= cc WARNING ?= -Wall -Wfatal-errors diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/README.md new/CoreFreq-2.0.9/README.md --- old/CoreFreq-2.0.8/README.md 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/README.md 2025-11-10 10:51:24.000000000 +0100 @@ -431,6 +431,9 @@ yum group install "Development Tools" ``` +## Fedora +* In [Fedora Copr](https://copr.fedorainfracloud.org/coprs/sunnyyang/corefreq) repository, please contact [Sunny Yang](https://github.com/sunnyyangyangyang) + ## AlmaLinux, Rocky Linux ```sh ## as root, install kernel development package and dependencies diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/aarch64/bitasm.h new/CoreFreq-2.0.9/aarch64/bitasm.h --- old/CoreFreq-2.0.8/aarch64/bitasm.h 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/aarch64/bitasm.h 2025-11-10 10:51:24.000000000 +0100 @@ -174,7 +174,7 @@ _BITSET_POST_INST_##_lock \ : [ret] "=m" (_ret) \ : [addr] "r" (&_base), \ - [offset] "r" (_offset) \ + [offset] "r" ((Bit64)(_offset)) \ _BITSET_CLOBBERS_##_lock \ ); \ _ret; \ @@ -239,7 +239,7 @@ _BITCLR_POST_INST_##_lock \ : [ret] "=m" (_ret) \ : [addr] "r" (&_base), \ - [offset] "r" (_offset) \ + [offset] "r" ((Bit64)(_offset)) \ _BITCLR_CLOBBERS_##_lock \ ); \ _ret; \ @@ -303,7 +303,7 @@ _BIT_TEST_POST_INST_##_lock \ : [ret] "=m" (_ret) \ : [addr] "r" (&_base), \ - [offset] "r" (_offset) \ + [offset] "r" ((Bit64)(_offset)) \ _BIT_TEST_CLOBBERS_##_lock \ ); \ _ret; \ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/aarch64/corefreqd.c new/CoreFreq-2.0.9/aarch64/corefreqd.c --- old/CoreFreq-2.0.8/aarch64/corefreqd.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/aarch64/corefreqd.c 2025-11-10 10:51:24.000000000 +0100 @@ -2117,15 +2117,17 @@ Arg[cpu].TID = 0; } } else { + volatile unsigned long long seed64; unsigned int seed32; __asm__ volatile ( "isb" "\n\t" "mrs %0, cntvct_el0" - : "=r" (seed32) + : "=r" (seed64) : : ); + seed32 = (unsigned int) seed64; #ifdef __GLIBC__ initstate_r( seed32, RO(Shm)->Cpu[cpu].Slice.Random.state, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/aarch64/corefreqk.c new/CoreFreq-2.0.9/aarch64/corefreqk.c --- old/CoreFreq-2.0.8/aarch64/corefreqk.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/aarch64/corefreqk.c 2025-11-10 10:51:24.000000000 +0100 @@ -553,19 +553,19 @@ "mrs %[mvfr2], mvfr2_el1" "\n\t" "mrs %[flags], currentel" "\n\t" "isb" - : [midr] "=r" (midr), - [cntfrq] "=r" (cntfrq), - [cntpct] "=r" (cntpct), - [dfr0] "=r" (dfr0), - [isar0] "=r" (isar0), - [isar1] "=r" (isar1), - [mmfr0] "=r" (mmfr0), - [mmfr1] "=r" (mmfr1), - [pfr0] "=r" (pfr0), - [pfr1] "=r" (pfr1), - [mvfr0] "=r" (mvfr0), - [mvfr1] "=r" (mvfr1), - [mvfr2] "=r" (mvfr2), + : [midr] "=r" (midr.value), + [cntfrq] "=r" (cntfrq.value), + [cntpct] "=r" (cntpct.value), + [dfr0] "=r" (dfr0.value), + [isar0] "=r" (isar0.value), + [isar1] "=r" (isar1.value), + [mmfr0] "=r" (mmfr0.value), + [mmfr1] "=r" (mmfr1.value), + [pfr0] "=r" (pfr0.value), + [pfr1] "=r" (pfr1.value), + [mvfr0] "=r" (mvfr0.value), + [mvfr1] "=r" (mvfr1.value), + [mvfr2] "=r" (mvfr2.value), [flags] "=r" (FLAGS) : : "cc", "memory" @@ -589,7 +589,7 @@ __asm__ __volatile__( "mrs %[pmcr] , pmcr_el0" "\n\t" "isb" - : [pmcr] "=r" (pmcr) + : [pmcr] "=r" (pmcr.value) : : "memory" ); @@ -1345,7 +1345,7 @@ __asm__ __volatile__( "mrs %[dfr1] , id_aa64dfr1_el1""\n\t" "isb" - : [dfr1] "=r" (dfr1) + : [dfr1] "=r" (dfr1.value) : : "memory" ); @@ -2108,8 +2108,8 @@ "msr csselr_el1, %[cssel]" "\n\t" "mrs %[ccsid], ccsidr_el1" "\n\t" "isb" - : [ccsid] "=r" (Core->T.Cache[level].ccsid) - : [cssel] "r" (cssel[select]) + : [ccsid] "=r" (Core->T.Cache[level].ccsid.value) + : [cssel] "r" (cssel[select].value) : "memory" ); @@ -2130,7 +2130,7 @@ ( "mrs %[clidr], clidr_el1" "\n\t" "isb" - : [clidr] "=r" (clidr) + : [clidr] "=r" (clidr.value) : : "memory" ); @@ -2165,8 +2165,8 @@ "mrs %[midr] , midr_el1" "\n\t" "mrs %[mpid] , mpidr_el1" "\n\t" "isb" - : [midr] "=r" (midr), - [mpid] "=r" (mpid) + : [midr] "=r" (midr.value), + [mpid] "=r" (mpid.value) : : "memory" ); @@ -2422,7 +2422,7 @@ __asm__ __volatile__( "mrs %[cntfrq], cntfrq_el0" "\n\t" "isb" - : [cntfrq] "=r" (cntfrq) + : [cntfrq] "=r" (cntfrq.value) : : "memory" ); @@ -3069,8 +3069,8 @@ "orr %[flags], %[flags], x12" "\n\t" "orr %[flags], %[flags], x11" : [sctlr] "=r" (Core->SystemRegister.SCTLR), - [mmfr1] "=r" (mmfr1), - [pfr0] "=r" (pfr0), + [mmfr1] "=r" (mmfr1.value), + [pfr0] "=r" (pfr0.value), [fpcr] "=r" (Core->SystemRegister.FPCR), [fpsr] "=r" (Core->SystemRegister.FPSR), [flags] "=r" (Core->SystemRegister.FLAGS) @@ -3297,9 +3297,9 @@ "mrs %[enset], pmcntenset_el0" "\n\t" "mrs %[enclr], pmcntenclr_el0" "\n\t" "isb" - : [pmuser] "=r" (pmuser), - [enset] "=r" (enset), - [enclr] "=r" (enclr) + : [pmuser] "=r" (pmuser.value), + [enset] "=r" (enset.value), + [enclr] "=r" (enclr.value) : : "memory" ); @@ -3315,7 +3315,7 @@ __asm__ __volatile__( "mrs %[revid], revidr_el1" "\n\t" "isb" - : [revid] "=r" (revid) + : [revid] "=r" (revid.value) : : "memory" ); @@ -3614,20 +3614,20 @@ "mov x12 , %[CTRL]" "\n\t" "msr pmcr_el0, x12" "\n\t" "isb" - : [PMCR] "+m" (Save->PMCR), - [PMSELR] "+m" (Save->PMSELR), - [PMTYPE3] "+m" (Save->PMTYPE[2]), - [PMTYPE2] "+m" (Save->PMTYPE[1]), - [PMTYPE1] "+m" (Save->PMTYPE[0]), - [PMCCFILTR] "+m" (Save->PMCCFILTR), - [PMCNTEN] "+m" (Save->PMCNTEN), - [PMUSER] "+m" (Save->PMUSER) - : [EVENT3] "r" (0x0008), - [EVENT2] "r" (0x0011), - [FILTR1] "r" (0x0), - [ENSET] "r" (0b10000000000000000000000000001100), - [ENUSR] "r" (0b0000101), - [CTRL] "i" (0b0000000010000111) + : [PMCR] "+m" (Save->PMCR.value), + [PMSELR] "+m" (Save->PMSELR.value), + [PMTYPE3] "+m" (Save->PMTYPE[2].value), + [PMTYPE2] "+m" (Save->PMTYPE[1].value), + [PMTYPE1] "+m" (Save->PMTYPE[0].value), + [PMCCFILTR] "+m" (Save->PMCCFILTR.value), + [PMCNTEN] "+m" (Save->PMCNTEN.value), + [PMUSER] "+m" (Save->PMUSER.value) + : [EVENT3] "r" (0x0008LLU), + [EVENT2] "r" (0x0011LLU), + [FILTR1] "r" (0x0LLU), + [ENSET] "r" (0x8000000cLLU), + [ENUSR] "r" (0x5LLU), + [CTRL] "i" (0x87LLU) : "memory", "%x12" ); } @@ -3670,14 +3670,14 @@ "isb" : - : [PMCR] "r" (Save->PMCR), - [PMSELR] "m" (Save->PMSELR), - [PMTYPE3] "m" (Save->PMTYPE[2]), - [PMTYPE2] "m" (Save->PMTYPE[1]), - [PMTYPE1] "m" (Save->PMTYPE[0]), - [PMCCFILTR] "r" (Save->PMCCFILTR), - [PMCNTEN] "r" (Save->PMCNTEN), - [PMUSER] "r" (Save->PMUSER) + : [PMCR] "r" (Save->PMCR.value), + [PMSELR] "m" (Save->PMSELR.value), + [PMTYPE3] "m" (Save->PMTYPE[2].value), + [PMTYPE2] "m" (Save->PMTYPE[1].value), + [PMTYPE1] "m" (Save->PMTYPE[0].value), + [PMCCFILTR] "r" (Save->PMCCFILTR.value), + [PMCNTEN] "r" (Save->PMCNTEN.value), + [PMUSER] "r" (Save->PMUSER.value) : "memory", "%x12" ); } @@ -3794,7 +3794,7 @@ __asm__ volatile \ ( \ "mrs %[cntpct], cntpct_el0" \ - : [cntpct] "=r" (cntpct) \ + : [cntpct] "=r" (cntpct.value) \ : \ : "cc", "memory" \ ); \ @@ -3999,12 +3999,21 @@ { #ifdef CONFIG_THERMAL if (!IS_ERR(PRIVATE(OF(Core, AT(Core->Bind)))->ThermalZone)) { - int mcelsius; + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0) + unsigned int mcelsius; if (thermal_zone_get_temp(PRIVATE(OF(Core, AT(Core->Bind)))->ThermalZone, - &mcelsius) == 0) + (int*) &mcelsius) == 0) { Core->PowerThermal.Sensor = mcelsius; } + #else + unsigned long mcelsius; + if (thermal_zone_get_temp(PRIVATE(OF(Core, AT(Core->Bind)))->ThermalZone, + &mcelsius) == 0) + { + Core->PowerThermal.Sensor = (unsigned int) mcelsius; + } + #endif } #endif /* CONFIG_THERMAL */ } @@ -4601,7 +4610,12 @@ * Core->Clock.Hz) / 1000LLU; /* MANDATORY Per-CPU Initialization */ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 18, 0) + policy->cpuinfo.transition_latency = \ + CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS; + #else policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + #endif policy->cur = policy->cpuinfo.max_freq; policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/ppc64le/corefreqk.c new/CoreFreq-2.0.9/ppc64le/corefreqk.c --- old/CoreFreq-2.0.8/ppc64le/corefreqk.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/ppc64le/corefreqk.c 2025-11-10 10:51:24.000000000 +0100 @@ -2661,7 +2661,12 @@ * Core->Clock.Hz) / 1000LLU; /* MANDATORY Per-CPU Initialization */ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 18, 0) + policy->cpuinfo.transition_latency = \ + CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS; + #else policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + #endif policy->cur = policy->cpuinfo.max_freq; policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/riscv64/corefreqk.c new/CoreFreq-2.0.9/riscv64/corefreqk.c --- old/CoreFreq-2.0.8/riscv64/corefreqk.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/riscv64/corefreqk.c 2025-11-10 10:51:24.000000000 +0100 @@ -2648,7 +2648,12 @@ * Core->Clock.Hz) / 1000LLU; /* MANDATORY Per-CPU Initialization */ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 18, 0) + policy->cpuinfo.transition_latency = \ + CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS; + #else policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + #endif policy->cur = policy->cpuinfo.max_freq; policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/x86_64/corefreq-cli.c new/CoreFreq-2.0.9/x86_64/corefreq-cli.c --- old/CoreFreq-2.0.8/x86_64/corefreq-cli.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/x86_64/corefreq-cli.c 2025-11-10 10:51:24.000000000 +0100 @@ -7854,6 +7854,7 @@ case AMD_Zen5_Eldora: case AMD_Zen5_Turin: case AMD_Zen5_Turin_Dense: + case AMD_Zen5_SHP: TopologyFunc = Topology_CCD; OffLineItem = RSC(TOPOLOGY_OFF_2).CODE(); TopologySubHeader[1] = TopologyAltSubHeader[2]; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/x86_64/corefreqd.c new/CoreFreq-2.0.9/x86_64/corefreqd.c --- old/CoreFreq-2.0.8/x86_64/corefreqd.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/x86_64/corefreqd.c 2025-11-10 10:51:24.000000000 +0100 @@ -7997,6 +7997,7 @@ case AMD_Zen5_Turin_Dense: case AMD_Zen5_KRK: case AMD_Zen5_STXH: + case AMD_Zen5_SHP: case AMD_Family_17h: case Hygon_Family_18h: case AMD_Family_19h: @@ -8866,7 +8867,12 @@ PFlip->Voltage.VID.CPU); } -#define Pkg_ComputeVoltage_Intel_SKL_X Pkg_ComputeVoltage_None +static void Pkg_ComputeVoltage_Intel_SKL_X(struct PKG_FLIP_FLOP *PFlip) +{ + COMPUTE_VOLTAGE(INTEL_SKL_X, + PFlip->Voltage.CPU, + PFlip->Voltage.VID.CPU); +} static void Pkg_ComputeVoltage_Intel_SAV(struct PKG_FLIP_FLOP *PFlip) { @@ -8883,7 +8889,12 @@ #define Pkg_ComputeVoltage_AMD_0Fh Pkg_ComputeVoltage_None -#define Pkg_ComputeVoltage_AMD_15h Pkg_ComputeVoltage_None +static void Pkg_ComputeVoltage_AMD_15h(struct PKG_FLIP_FLOP *PFlip) +{ + COMPUTE_VOLTAGE(AMD_15h, + PFlip->Voltage.CPU, + PFlip->Voltage.VID.CPU); +} static void Pkg_ComputeVoltage_AMD_17h(struct PKG_FLIP_FLOP *PFlip) { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/x86_64/corefreqk.c new/CoreFreq-2.0.9/x86_64/corefreqk.c --- old/CoreFreq-2.0.8/x86_64/corefreqk.c 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/x86_64/corefreqk.c 2025-11-10 10:51:24.000000000 +0100 @@ -3,6 +3,8 @@ * Copyright (C) 2015-2025 CYRIL COURTIAT * Licenses: GPL2 * + * Rizankizumab [08.11.2025] + * * Time Capsule[12.24.2024] * Cyril to Christiane Courtiat * Love you Mum; rest in peace @@ -2211,6 +2213,7 @@ case AMD_Zen5_Eldora: case AMD_Zen5_Turin: case AMD_Zen5_Turin_Dense: + case AMD_Zen5_SHP: case AMD_Family_17h: case Hygon_Family_18h: case AMD_Family_19h: @@ -8317,6 +8320,7 @@ SMU_AMD_F17H_MATISSE_COF, PRIVATE(OF(Zen)).Device.DF); break; + case AMD_Zen5_SHP: case AMD_Zen5_Turin: case AMD_Zen5_Turin_Dense: case AMD_Zen4_Bergamo: @@ -13115,6 +13119,7 @@ Dump_CPUID(Core); BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->TM_Mask , Core->Bind); + BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->DCU_Mask , Core->Bind); BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->TurboBoost_Mask,Core->Bind); BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->C1E_Mask , Core->Bind); BITSET_CC(BUS_LOCK, PUBLIC(RO(Proc))->C3A_Mask , Core->Bind); @@ -22001,7 +22006,12 @@ * Core->Clock.Hz) / 1000LLU; /* MANDATORY Per-CPU Initialization */ + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 18, 0) + policy->cpuinfo.transition_latency = \ + CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS; + #else policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + #endif policy->cur = policy->cpuinfo.max_freq; policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; @@ -24011,7 +24021,8 @@ { unsigned long reqSize = vma->vm_end - vma->vm_start; #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) \ - || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) && (RHEL_MINOR >= 5)) + || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \ + && (RHEL_MINOR >= 5) && (RHEL_MINOR < 99)) vm_flags_t vm_ro = VM_READ | VM_DONTEXPAND; vm_flags_t vm_rw = VM_READ | VM_WRITE | VM_DONTEXPAND; #endif @@ -24028,7 +24039,8 @@ } #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) \ - || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) && (RHEL_MINOR >= 5)) + || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \ + && (RHEL_MINOR >= 5) && (RHEL_MINOR < 99)) vm_flags_reset_once(vma, vm_ro); #else vma->vm_flags = VM_READ | VM_DONTEXPAND; @@ -24051,7 +24063,8 @@ } #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) \ - || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) && (RHEL_MINOR >= 5)) + || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \ + && (RHEL_MINOR >= 5) && (RHEL_MINOR < 99)) vm_flags_reset_once(vma, vm_rw); #else vma->vm_flags = VM_READ | VM_WRITE | VM_DONTEXPAND; @@ -24079,7 +24092,8 @@ } #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) \ - || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) && (RHEL_MINOR >= 5)) + || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \ + && (RHEL_MINOR >= 5) && (RHEL_MINOR < 99)) vm_flags_reset_once(vma, vm_ro); #else vma->vm_flags = VM_READ | VM_DONTEXPAND; @@ -24111,7 +24125,8 @@ } #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) \ - || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) && (RHEL_MINOR >= 5)) + || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \ + && (RHEL_MINOR >= 5) && (RHEL_MINOR < 99)) vm_flags_reset_once(vma, vm_ro); #else vma->vm_flags = VM_READ | VM_DONTEXPAND; @@ -24142,7 +24157,8 @@ } #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) \ - || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) && (RHEL_MINOR >= 5)) + || (defined(RHEL_MAJOR) && (RHEL_MAJOR >= 9) \ + && (RHEL_MINOR >= 5) && (RHEL_MINOR < 99)) vm_flags_reset_once(vma, vm_rw); #else vma->vm_flags = VM_READ | VM_WRITE | VM_DONTEXPAND; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/x86_64/corefreqk.h new/CoreFreq-2.0.9/x86_64/corefreqk.h --- old/CoreFreq-2.0.8/x86_64/corefreqk.h 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/x86_64/corefreqk.h 2025-11-10 10:51:24.000000000 +0100 @@ -2122,7 +2122,8 @@ [Zen5/Turin] BF_02h Stepping 1 4 nm SP5 [Zen5c/Turin] BF_11h Stepping 0 3 nm SP5 [Zen5/5c/Krackan Point] BF_60h Stepping 0 4 nm [KRK]/FP8 - [Zen5/Strix Halo] BF_70h Stepping 0 4 nm [STXH]/FP11 */ + [Zen5/Strix Halo] BF_70h Stepping 0 4 nm [STXH]/FP11 + [Zen5/Shimada Peak] BF_08h Stepping 1 4 nm HEDT/sTR5 */ #define _AMD_Family_19h {.ExtFamily=0xA, .Family=0xF, .ExtModel=0x0, .Model=0x0} #define _AMD_Zen3_VMR {.ExtFamily=0xA, .Family=0xF, .ExtModel=0x2, .Model=0x1} #define _AMD_Zen3_CZN {.ExtFamily=0xA, .Family=0xF, .ExtModel=0x5, .Model=0x0} @@ -2156,6 +2157,7 @@ #define _AMD_Zen5_KRK {.ExtFamily=0xB, .Family=0xF, .ExtModel=0x6, .Model=0x0} #define _AMD_Zen5_STXH {.ExtFamily=0xB, .Family=0xF, .ExtModel=0x7, .Model=0x0} +#define _AMD_Zen5_SHP {.ExtFamily=0xB, .Family=0xF, .ExtModel=0x0, .Model=0x8} typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *); @@ -3866,7 +3868,8 @@ CN_MATISSE }; enum { - CN_VANGOGH + CN_VANGOGH, + CN_VANGOGH_HANDHELD }; enum { CN_MENDOCINO @@ -3951,6 +3954,10 @@ CN_STRIX_HALO }; +enum { + CN_SHIMADA_PEAK +}; + static char *Arch_AMD_Zen[] = ZLIST( [CN_SUMMIT_RIDGE] = "Zen/Summit Ridge", [CN_WHITEHAVEN] = "Zen/Whitehaven", @@ -3991,7 +3998,8 @@ static char *Arch_AMD_Zen2_Ariel[] = ZLIST("Zen2/Ariel"); static char *Arch_AMD_Zen2_Jupiter[] = ZLIST( - [CN_VANGOGH] = "Zen2/Van Gogh/Aerith" + [CN_VANGOGH] = "Zen2/Van Gogh/Aerith", + [CN_VANGOGH_HANDHELD] = "Zen2/Van Gogh/Handheld" ); static char *Arch_AMD_Zen2_Galileo[] = ZLIST( [CN_VANGOGH] = "Zen2/Van Gogh/Sephiroth" @@ -4066,6 +4074,9 @@ static char *Arch_AMD_Zen5_STXH[] = ZLIST( [CN_STRIX_HALO] = "Zen5/Strix Halo" ); +static char *Arch_AMD_Zen5_SHP[] = ZLIST( + [CN_SHIMADA_PEAK] = "Zen5/Shimada Peak" +); static char *Arch_AMD_Family_17h[] = ZLIST("AMD Family 17h"); @@ -7046,6 +7057,18 @@ .HSMP_Capable = 0, .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, + { + .Brand = ZLIST("AMD Ryzen Z2 A"), + .Boost = {+10, 0}, + .Param.Offset = {100, 0, 0}, + .CodeNameIdx = CN_VANGOGH_HANDHELD, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, {0} }; static PROCESSOR_SPECIFIC AMD_Zen2_MDN_Specific[] = { @@ -7136,8 +7159,9 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD Ryzen 7 5800X", - "AMD Ryzen 5 5600" ), + .Brand = ZLIST( "AMD Ryzen 7 5800X", \ + "AMD Ryzen 5 5600", \ + "AMD Ryzen 5 5500X3D" ), .Boost = {+9, +1}, .Param.Offset = {90, 0, 0}, .CodeNameIdx = CN_VERMEER, @@ -8537,7 +8561,8 @@ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 9 7945HX"), + .Brand = ZLIST( "AMD Ryzen 9 7945HX", \ + "AMD Ryzen 9 8945HX" ), .Boost = {+29, +1}, .Param.Offset = {100, 0, 0}, .CodeNameIdx = CN_DRAGON_RANGE, @@ -8549,7 +8574,8 @@ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 9 7940HX"), + .Brand = ZLIST( "AMD Ryzen 9 7940HX", \ + "AMD Ryzen 9 8940HX" ), .Boost = {+28, +1}, .Param.Offset = {100, 0, 0}, .CodeNameIdx = CN_DRAGON_RANGE, @@ -8562,7 +8588,8 @@ }, { .Brand = ZLIST( "AMD Ryzen 9 7845HX", \ - "AMD Ryzen 9 7840HX" ), + "AMD Ryzen 9 7840HX", \ + "AMD Ryzen 9 8840HX" ), .Boost = {+22, +1}, .Param.Offset = {100, 0, 0}, .CodeNameIdx = CN_DRAGON_RANGE, @@ -8574,7 +8601,8 @@ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen 7 7745HX"), + .Brand = ZLIST( "AMD Ryzen 7 7745HX", \ + "AMD Ryzen 7 8745HX" ), .Boost = {+15, +1}, .Param.Offset = {100, 0, 0}, .CodeNameIdx = CN_DRAGON_RANGE, @@ -8802,6 +8830,19 @@ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { + .Brand = ZLIST( "AMD Ryzen 7 8745HS",/* zh-cn */\ + "AMD Ryzen 7 8745H" /* zh-cn */), + .Boost = {+11, 0}, + .Param.Offset = {100, 0, 0}, + .CodeNameIdx = CN_HAWK_POINT, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 0, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK + }, + { .Brand = ZLIST( "AMD Ryzen 5 PRO 8645HS", \ "AMD Ryzen 5 8645HS", \ "AMD Ryzen 5 8645H", /* zh-cn */\ @@ -9229,7 +9270,8 @@ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK }, { - .Brand = ZLIST("AMD Ryzen Z2 Extreme"), + .Brand = ZLIST( "AMD Ryzen AI Z2 Extreme", \ + "AMD Ryzen Z2 Extreme" ), .Boost = {+30, 0}, .Param.Offset = {100, 0, 0}, .CodeNameIdx = CN_STX_HANDHELD, @@ -9385,7 +9427,8 @@ }; static PROCESSOR_SPECIFIC AMD_Zen5_Turin_Specific[] = { { - .Brand = ZLIST("AMD EPYC 9965"), /* Model: 17 */ + .Brand = ZLIST( "AMD EPYC Embedded 9965",\ + "AMD EPYC 9965" ), /* Model: 17 */ .Boost = {+15, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_TURIN_DENSE, @@ -9398,7 +9441,8 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD EPYC 9845"), + .Brand = ZLIST( "AMD EPYC Embedded 9845",\ + "AMD EPYC 9845" ), .Boost = {+16, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_TURIN_DENSE, @@ -9437,8 +9481,10 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD EPYC 9755", /* Model: 2 */ \ - "AMD EPYC 9335" ), + .Brand = ZLIST( "AMD EPYC Embedded 9755", \ + "AMD EPYC Embedded 9335", \ + "AMD EPYC 9755", /* Model: 2 */ \ + "AMD EPYC 9335" ), .Boost = {+14, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_TURIN, @@ -9451,7 +9497,8 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD EPYC 9745"), + .Brand = ZLIST( "AMD EPYC Embedded 9745",\ + "AMD EPYC 9745" ), .Boost = {+13, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_TURIN_DENSE, @@ -9477,7 +9524,9 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD EPYC 9455P" \ + .Brand = ZLIST( "AMD EPYC Embedded 9455P",\ + "AMD EPYC Embedded 9455",\ + "AMD EPYC 9455P" \ "AMD EPYC 9455" ), .Boost = {+13, 0}, .Param.Offset = {0, 0, 0}, @@ -9491,7 +9540,9 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD EPYC 9655P", \ + .Brand = ZLIST( "AMD EPYC Embedded 9655P",\ + "AMD EPYC Embedded 9655",\ + "AMD EPYC 9655P", \ "AMD EPYC 9655", \ "AMD EPYC 9535" ), .Boost = {+19, 0}, @@ -9519,7 +9570,9 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD EPYC 9565", \ + .Brand = ZLIST( "AMD EPYC Embedded 9555P",\ + "AMD EPYC Embedded 9555",\ + "AMD EPYC 9565", \ "AMD EPYC 9555P", \ "AMD EPYC 9555", \ "AMD EPYC 9475F" ), @@ -9548,7 +9601,9 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD EPYC 9365", \ + .Brand = ZLIST( "AMD EPYC Embedded 9355P",\ + "AMD EPYC Embedded 9355",\ + "AMD EPYC 9365", \ "AMD EPYC 9355P", \ "AMD EPYC 9355" ), .Boost = {+9, 0}, @@ -9563,7 +9618,8 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST( "AMD EPYC 9275F", \ + .Brand = ZLIST( "AMD EPYC Embedded 9135",\ + "AMD EPYC 9275F", \ "AMD EPYC 9135" ), .Boost = {+7, 0}, .Param.Offset = {0, 0, 0}, @@ -9577,7 +9633,8 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD EPYC 9255"), + .Brand = ZLIST( "AMD EPYC Embedded 9255",\ + "AMD EPYC 9255" ), .Boost = {+11, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_TURIN, @@ -9603,7 +9660,8 @@ |LATCH_HSMP_CAPABLE }, { - .Brand = ZLIST("AMD EPYC 9015"), + .Brand = ZLIST( "AMD EPYC Embedded 9015",\ + "AMD EPYC 9015" ), .Boost = {+5, 0}, .Param.Offset = {0, 0, 0}, .CodeNameIdx = CN_TURIN, @@ -9671,6 +9729,90 @@ }, {0} }; +static PROCESSOR_SPECIFIC AMD_Zen5_SHP_Specific[] = { + { + .Brand = ZLIST("AMD Ryzen Threadripper PRO 9995WX"), + .Boost = {+29, 0}, + .Param.Offset = {95, 0, 0}, + .CodeNameIdx = CN_SHIMADA_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD Ryzen Threadripper PRO 9985WX", \ + "AMD Ryzen Threadripper 9980X" ), + .Boost = {+22, 0}, + .Param.Offset = {95, 0, 0}, + .CodeNameIdx = CN_SHIMADA_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD Ryzen Threadripper PRO 9975WX", \ + "AMD Ryzen Threadripper 9970X" ), + .Boost = {+14, 0}, + .Param.Offset = {95, 0, 0}, + .CodeNameIdx = CN_SHIMADA_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST( "AMD Ryzen Threadripper PRO 9965WX", \ + "AMD Ryzen Threadripper 9960X" ), + .Boost = {+12, 0}, + .Param.Offset = {95, 0, 0}, + .CodeNameIdx = CN_SHIMADA_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen Threadripper PRO 9955WX"), + .Boost = {+9, 0}, + .Param.Offset = {95, 0, 0}, + .CodeNameIdx = CN_SHIMADA_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + { + .Brand = ZLIST("AMD Ryzen Threadripper PRO 9945WX"), + .Boost = {+7, 0}, + .Param.Offset = {95, 0, 0}, + .CodeNameIdx = CN_SHIMADA_PEAK, + .TgtRatioUnlocked = 1, + .ClkRatioUnlocked = 0b10, + .TurboUnlocked = 0, + .UncoreUnlocked = 0, + .HSMP_Capable = 1, + .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\ + |LATCH_HSMP_CAPABLE + }, + {0} +}; static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = { {0} @@ -13511,5 +13653,29 @@ .Specific = AMD_Zen5_STXH_Specific, .SystemDriver = AMD_Zen_Driver, .Architecture = Arch_AMD_Zen5_STXH + }, +[AMD_Zen5_SHP] = { /*130*/ + .Signature = _AMD_Zen5_SHP, + .Query = Query_AMD_F1Ah_PerCluster, + .Update = PerCore_AMD_Family_1Ah_Query, + .Start = Start_AMD_Family_1Ah, + .Stop = Stop_AMD_Family_1Ah, + .Exit = Exit_AMD_F1Ah, + .Timer = InitTimer_AMD_Family_1Ah, + .BaseClock = BaseClock_AMD_Family_1Ah, + .ClockMod = ClockMod_AMD_Zen, + .TurboClock = TurboClock_AMD_Zen, + .thermalFormula = THERMAL_FORMULA_AMD_1Ah, + .voltageFormula = VOLTAGE_FORMULA_AMD_1Ah, + .powerFormula = POWER_FORMULA_AMD_1Ah, + .PCI_ids = PCI_AMD_1Ah_ids, + .Uncore = { + .Start = Start_Uncore_AMD_Family_1Ah, + .Stop = Stop_Uncore_AMD_Family_1Ah, + .ClockMod = NULL + }, + .Specific = AMD_Zen5_SHP_Specific, + .SystemDriver = AMD_Zen_Driver, + .Architecture = Arch_AMD_Zen5_SHP } }; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/CoreFreq-2.0.8/x86_64/coretypes.h new/CoreFreq-2.0.9/x86_64/coretypes.h --- old/CoreFreq-2.0.8/x86_64/coretypes.h 2025-08-01 19:11:19.000000000 +0200 +++ new/CoreFreq-2.0.9/x86_64/coretypes.h 2025-11-10 10:51:24.000000000 +0100 @@ -153,6 +153,7 @@ AMD_Zen5_Turin_Dense, AMD_Zen5_KRK, AMD_Zen5_STXH, + AMD_Zen5_SHP, ARCHITECTURES };
