Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package libdrm for openSUSE:Factory checked in at 2025-12-09 12:46:00 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/libdrm (Old) and /work/SRC/openSUSE:Factory/.libdrm.new.1939 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "libdrm" Tue Dec 9 12:46:00 2025 rev:187 rq:1321606 version:2.4.130 Changes: -------- --- /work/SRC/openSUSE:Factory/libdrm/libdrm.changes 2025-11-19 14:51:55.851059447 +0100 +++ /work/SRC/openSUSE:Factory/.libdrm.new.1939/libdrm.changes 2025-12-09 12:48:27.063116518 +0100 @@ -1,0 +2,11 @@ +Mon Dec 8 15:08:17 UTC 2025 - Stefan Dirsch <[email protected]> + +- Update to 2.4.130 + * omap: fix omap_bo_size for tiled buffers + * amdgpu: add env support for amdgpu.ids path + * Support multiple paths in AMDGPU_ASIC_ID_TABLE_PATH envar + * amdgpu: Fix envar name in documentation + * Sync headers with drm-next + * headers: drm: Sync virtgpu_drm.h with Linux v6.16 + +------------------------------------------------------------------- Old: ---- libdrm-2.4.129.tar.xz New: ---- libdrm-2.4.130.tar.xz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ libdrm.spec ++++++ --- /var/tmp/diff_new_pack.bHGvBE/_old 2025-12-09 12:48:31.667310746 +0100 +++ /var/tmp/diff_new_pack.bHGvBE/_new 2025-12-09 12:48:31.667310746 +0100 @@ -29,7 +29,7 @@ Name: libdrm # Please remember to adjust the version in the n_libdrm-drop-valgrind* patches -Version: 2.4.129 +Version: 2.4.130 Release: 0 Summary: Userspace Interface for Kernel DRM Services License: MIT ++++++ libdrm-2.4.129.tar.xz -> libdrm-2.4.130.tar.xz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/README.rst new/libdrm-2.4.130/README.rst --- old/libdrm-2.4.129/README.rst 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/README.rst 2025-12-08 14:15:17.000000000 +0100 @@ -49,3 +49,12 @@ If you are installing into a system location you will need to run install separately, and as root. + +AMDGPU ASIC table file +---------------------- + +The AMDGPU driver requires the `amdgpu.ids` file. It is usually located at +`$PREFIX/share/libdrm`, but it is possible to specify a set of alternative +paths at runtime by setting the `AMDGPU_ASIC_ID_TABLE_PATHS` environment +variable with one or more colon-separated paths where to search for the +`amdgpu.ids` file. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/amdgpu/amdgpu_asic_id.c new/libdrm-2.4.130/amdgpu/amdgpu_asic_id.c --- old/libdrm-2.4.129/amdgpu/amdgpu_asic_id.c 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/amdgpu/amdgpu_asic_id.c 2025-12-08 14:15:17.000000000 +0100 @@ -22,6 +22,11 @@ * */ +// secure_getenv requires _GNU_SOURCE +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + #include <ctype.h> #include <stdio.h> #include <stdlib.h> @@ -160,6 +165,110 @@ fclose(fp); } +static char *join_path(const char *dir, const char *file) { + size_t dir_len = strlen(dir); + size_t file_len = strlen(file); + char *full_path = NULL; + + int need_slash = ((dir_len > 0) && (dir[dir_len - 1] != '/')); + size_t total_len = dir_len + (need_slash ? 1 : 0) + file_len + 1; // +1 for null terminator + + if (dir_len == 0) { + return strdup(file); + } + + full_path = malloc(total_len); + if (!full_path) { + return NULL; // Memory allocation failed + } + + strcpy(full_path, dir); + if (need_slash) { + full_path[dir_len] = '/'; + dir_len++; + } + strcpy(full_path + dir_len, file); + + return full_path; +} + +static char **split_env_var(const char *env_var_content) +{ + char **ret = NULL; + char *dup_env_val; + int elements = 1; + int index = 1; + + if (!env_var_content || env_var_content[0] == '\0') + return NULL; + + for(char *p = (char *)env_var_content; *p; p++) { + if (*p == ':') + elements++; + } + + dup_env_val = strdup(env_var_content); + if (!dup_env_val) { + return NULL; + } + ret = malloc(sizeof(char *) * (elements + 1)); + ret[0] = dup_env_val; + for(char *p = (char *)dup_env_val; *p; p++) { + if (*p == ':') { + *p = 0; + ret[index++] = p + 1; + } + } + ret[index] = NULL; // ensure that the last element in the array is NULL + return ret; +} + +static void split_env_var_free(char **split_var) +{ + if (split_var) { + // remember that the first element also points to the whole duplicated string, + // which was modified in place by replacing ':' with '\0' characters + free(split_var[0]); + free(split_var); + } +} + +static char *find_asic_id_table(void) +{ + // first check the paths in AMDGPU_ASIC_ID_TABLE_PATHS environment variable + const char *amdgpu_asic_id_table_paths = secure_getenv("AMDGPU_ASIC_ID_TABLE_PATHS"); + char *file_name = NULL; + char *found_path = NULL; + char **paths = NULL; + + if (!amdgpu_asic_id_table_paths) + return NULL; + + // extract the file name from AMDGPU_ASIC_ID_TABLE + file_name = strrchr(AMDGPU_ASIC_ID_TABLE, '/'); + if (!file_name) + return NULL; + file_name++; // skip the '/' + + paths = split_env_var(amdgpu_asic_id_table_paths); + if (!paths) + return NULL; + + // for each path, join with file_name and check if it exists + for (int i = 0; paths[i] != NULL; i++) { + char *full_path = join_path(paths[i], file_name); + if (!full_path) { + continue; + } + if (access(full_path, R_OK) == 0) { + found_path = full_path; + break; + } + } + split_env_var_free(paths); + return found_path; +} + void amdgpu_parse_asic_ids(struct amdgpu_device *dev) { FILE *fp; @@ -169,9 +278,15 @@ int line_num = 1; int r = 0; - fp = fopen(AMDGPU_ASIC_ID_TABLE, "r"); + char *amdgpu_asic_id_table_path = find_asic_id_table(); + + // if not found, use the default AMDGPU_ASIC_ID_TABLE path + if (!amdgpu_asic_id_table_path) + amdgpu_asic_id_table_path = strdup(AMDGPU_ASIC_ID_TABLE); + + fp = fopen(amdgpu_asic_id_table_path, "r"); if (!fp) { - fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE, + fprintf(stderr, "%s: %s\n", amdgpu_asic_id_table_path, strerror(errno)); goto get_cpu; } @@ -188,7 +303,7 @@ continue; } - drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line); + drmMsg("%s version: %s\n", amdgpu_asic_id_table_path, line); break; } @@ -206,7 +321,7 @@ if (r == -EINVAL) { fprintf(stderr, "Invalid format: %s: line %d: %s\n", - AMDGPU_ASIC_ID_TABLE, line_num, line); + amdgpu_asic_id_table_path, line_num, line); } else if (r && r != -EAGAIN) { fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n", __func__, strerror(-r)); @@ -216,6 +331,7 @@ fclose(fp); get_cpu: + free(amdgpu_asic_id_table_path); if (dev->info.ids_flags & AMDGPU_IDS_FLAGS_FUSION && dev->marketing_name == NULL) { amdgpu_parse_proc_cpuinfo(dev); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/include/drm/drm.h new/libdrm-2.4.130/include/drm/drm.h --- old/libdrm-2.4.129/include/drm/drm.h 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/include/drm/drm.h 2025-12-08 14:15:17.000000000 +0100 @@ -900,6 +900,21 @@ */ #define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6 +/** + * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE + * + * If set to 1 the DRM core will allow setting the COLOR_PIPELINE + * property on a &drm_plane, as well as drm_colorop properties. + * + * Setting of these plane properties will be rejected when this client + * cap is set: + * - COLOR_ENCODING + * - COLOR_RANGE + * + * The client must enable &DRM_CLIENT_CAP_ATOMIC first. + */ +#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7 + /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/include/drm/drm_fourcc.h new/libdrm-2.4.130/include/drm/drm_fourcc.h --- old/libdrm-2.4.129/include/drm/drm_fourcc.h 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/include/drm/drm_fourcc.h 2025-12-08 14:15:17.000000000 +0100 @@ -979,14 +979,20 @@ * 2 = Gob Height 8, Turing+ Page Kind mapping * 3 = Reserved for future use. * - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further - * bit remapping step that occurs at an even lower level than the - * page kind and block linear swizzles. This causes the layout of - * surfaces mapped in those SOC's GPUs to be incompatible with the - * equivalent mapping on other GPUs in the same system. + * 22:22 s Sector layout. There is a further bit remapping step that occurs + * 26:27 at an even lower level than the page kind and block linear + * swizzles. This causes the bit arrangement of surfaces in memory + * to differ subtly, and prevents direct sharing of surfaces between + * GPUs with different layouts. * - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. - * 1 = Desktop GPU and Tegra Xavier+ Layout + * 0 = Tegra K1 - Tegra Parker/TX2 Layout + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout + * 4 = Reserved for future use. + * 5 = Reserved for future use. + * 6 = Reserved for future use. + * 7 = Reserved for future use. * * 25:23 c Lossless Framebuffer Compression type. * @@ -1001,7 +1007,7 @@ * 6 = Reserved for future use * 7 = Reserved for future use * - * 55:25 - Reserved for future use. Must be zero. + * 55:28 - Reserved for future use. Must be zero. */ #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ fourcc_mod_code(NVIDIA, (0x10 | \ @@ -1009,6 +1015,7 @@ (((k) & 0xff) << 12) | \ (((g) & 0x3) << 20) | \ (((s) & 0x1) << 22) | \ + (((s) & 0x6) << 25) | \ (((c) & 0x7) << 23))) /* To grandfather in prior block linear format modifiers to the above layout, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/include/drm/drm_mode.h new/libdrm-2.4.130/include/drm/drm_mode.h --- old/libdrm-2.4.129/include/drm/drm_mode.h 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/include/drm/drm_mode.h 2025-12-08 14:15:17.000000000 +0100 @@ -629,6 +629,7 @@ #define DRM_MODE_OBJECT_FB 0xfbfbfbfb #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee +#define DRM_MODE_OBJECT_COLOROP 0xfafafafa #define DRM_MODE_OBJECT_ANY 0 struct drm_mode_obj_get_properties { @@ -846,6 +847,20 @@ __u64 matrix[9]; }; +struct drm_color_ctm_3x4 { + /* + * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude + * (not two's complement!) format. + * + * out matrix in + * |R| |0 1 2 3 | | R | + * |G| = |4 5 6 7 | x | G | + * |B| |8 9 10 11| | B | + * |1.0| + */ + __u64 matrix[12]; +}; + struct drm_color_lut { /* * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and @@ -857,6 +872,125 @@ __u16 reserved; }; +/* + * struct drm_color_lut32 + * + * 32-bit per channel color LUT entry, similar to drm_color_lut. + */ +struct drm_color_lut32 { + __u32 red; + __u32 green; + __u32 blue; + __u32 reserved; +}; + +/** + * enum drm_colorop_type - Type of color operation + * + * drm_colorops can be of many different types. Each type behaves differently + * and defines a different set of properties. This enum defines all types and + * gives a high-level description. + */ +enum drm_colorop_type { + /** + * @DRM_COLOROP_1D_CURVE: + * + * enum string "1D Curve" + * + * A 1D curve that is being applied to all color channels. The + * curve is specified via the CURVE_1D_TYPE colorop property. + */ + DRM_COLOROP_1D_CURVE, + + /** + * @DRM_COLOROP_1D_LUT: + * + * enum string "1D LUT" + * + * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries, + * packed into a blob via the DATA property. The driver's + * expected LUT size is advertised via the SIZE property. + * + * The DATA blob is an array of struct drm_color_lut32 with size + * of "size". + */ + DRM_COLOROP_1D_LUT, + + /** + * @DRM_COLOROP_CTM_3X4: + * + * enum string "3x4 Matrix" + * + * A 3x4 matrix. Its values are specified via the + * &drm_color_ctm_3x4 struct provided via the DATA property. + * + * The DATA blob is a float[12]: + * out matrix in + * | R | | 0 1 2 3 | | R | + * | G | = | 4 5 6 7 | x | G | + * | B | | 8 9 10 12 | | B | + */ + DRM_COLOROP_CTM_3X4, + + /** + * @DRM_COLOROP_MULTIPLIER: + * + * enum string "Multiplier" + * + * A simple multiplier, applied to all color values. The + * multiplier is specified as a S31.32 via the MULTIPLIER + * property. + */ + DRM_COLOROP_MULTIPLIER, + + /** + * @DRM_COLOROP_3D_LUT: + * + * enum string "3D LUT" + * + * A 3D LUT of &drm_color_lut32 entries, + * packed into a blob via the DATA property. The driver's expected + * LUT size is advertised via the SIZE property, i.e., a 3D LUT with + * 17x17x17 entries will have SIZE set to 17. + * + * The DATA blob is a 3D array of struct drm_color_lut32 with dimension + * length of "size". + * The LUT elements are traversed like so: + * + * for B in range 0..n + * for G in range 0..n + * for R in range 0..n + * index = R + n * (G + n * B) + * color = lut3d[index] + */ + DRM_COLOROP_3D_LUT, +}; + +/** + * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation + */ +enum drm_colorop_lut3d_interpolation_type { + /** + * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL: + * + * Tetrahedral 3DLUT interpolation + */ + DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL, +}; + +/** + * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs + */ +enum drm_colorop_lut1d_interpolation_type { + /** + * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR: + * + * Linear interpolation. Values between points of the LUT will be + * linearly interpolated. + */ + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, +}; + /** * struct drm_plane_size_hint - Plane size hints * @width: The width of the plane in pixel diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/include/drm/virtgpu_drm.h new/libdrm-2.4.130/include/drm/virtgpu_drm.h --- old/libdrm-2.4.129/include/drm/virtgpu_drm.h 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/include/drm/virtgpu_drm.h 2025-12-08 14:15:17.000000000 +0100 @@ -46,12 +46,16 @@ #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 #define DRM_VIRTGPU_WAIT 0x08 #define DRM_VIRTGPU_GET_CAPS 0x09 +#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a +#define DRM_VIRTGPU_CONTEXT_INIT 0x0b #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 +#define VIRTGPU_EXECBUF_RING_IDX 0x04 #define VIRTGPU_EXECBUF_FLAGS (\ VIRTGPU_EXECBUF_FENCE_FD_IN |\ VIRTGPU_EXECBUF_FENCE_FD_OUT |\ + VIRTGPU_EXECBUF_RING_IDX |\ 0) struct drm_virtgpu_map { @@ -60,6 +64,17 @@ __u32 pad; }; +#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01 +#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \ + VIRTGPU_EXECBUF_SYNCOBJ_RESET | \ + 0) +struct drm_virtgpu_execbuffer_syncobj { + __u32 handle; + __u32 flags; + __u64 point; +}; + +/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */ struct drm_virtgpu_execbuffer { __u32 flags; __u32 size; @@ -67,10 +82,22 @@ __u64 bo_handles; __u32 num_bo_handles; __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ + __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */ + __u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */ + __u32 num_in_syncobjs; + __u32 num_out_syncobjs; + __u64 in_syncobjs; + __u64 out_syncobjs; }; #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ +#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */ +#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */ +#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */ +#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */ +#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */ +#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */ struct drm_virtgpu_getparam { __u64 param; @@ -100,7 +127,7 @@ __u32 bo_handle; __u32 res_handle; __u32 size; - __u32 stride; + __u32 blob_mem; }; struct drm_virtgpu_3d_box { @@ -117,6 +144,8 @@ struct drm_virtgpu_3d_box box; __u32 level; __u32 offset; + __u32 stride; + __u32 layer_stride; }; struct drm_virtgpu_3d_transfer_from_host { @@ -124,6 +153,8 @@ struct drm_virtgpu_3d_box box; __u32 level; __u32 offset; + __u32 stride; + __u32 layer_stride; }; #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ @@ -132,6 +163,12 @@ __u32 flags; }; +#define VIRTGPU_DRM_CAPSET_VIRGL 1 +#define VIRTGPU_DRM_CAPSET_VIRGL2 2 +#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3 +#define VIRTGPU_DRM_CAPSET_VENUS 4 +#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5 +#define VIRTGPU_DRM_CAPSET_DRM 6 struct drm_virtgpu_get_caps { __u32 cap_set_id; __u32 cap_set_ver; @@ -140,6 +177,55 @@ __u32 pad; }; +struct drm_virtgpu_resource_create_blob { +#define VIRTGPU_BLOB_MEM_GUEST 0x0001 +#define VIRTGPU_BLOB_MEM_HOST3D 0x0002 +#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003 + +#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001 +#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002 +#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 + /* zero is invalid blob_mem */ + __u32 blob_mem; + __u32 blob_flags; + __u32 bo_handle; + __u32 res_handle; + __u64 size; + + /* + * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and + * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero. + */ + __u32 pad; + __u32 cmd_size; + __u64 cmd; + __u64 blob_id; +}; + +#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001 +#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002 +#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003 +#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME 0x0004 +struct drm_virtgpu_context_set_param { + __u64 param; + __u64 value; +}; + +struct drm_virtgpu_context_init { + __u32 num_params; + __u32 pad; + + /* pointer to drm_virtgpu_context_set_param array */ + __u64 ctx_set_params; +}; + +/* + * Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in + * effect. The event size is sizeof(drm_event), since there is no additional + * payload. + */ +#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000 + #define DRM_IOCTL_VIRTGPU_MAP \ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) @@ -175,6 +261,14 @@ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ struct drm_virtgpu_get_caps) +#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \ + struct drm_virtgpu_resource_create_blob) + +#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \ + struct drm_virtgpu_context_init) + #if defined(__cplusplus) } #endif diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/meson.build new/libdrm-2.4.130/meson.build --- old/libdrm-2.4.129/meson.build 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/meson.build 2025-12-08 14:15:17.000000000 +0100 @@ -26,7 +26,7 @@ project( 'libdrm', ['c'], - version : '2.4.129', + version : '2.4.130', license : 'MIT', meson_version : '>= 0.59', default_options : ['buildtype=debugoptimized', 'c_std=c11'], diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.129/omap/omap_drm.c new/libdrm-2.4.130/omap/omap_drm.c --- old/libdrm-2.4.129/omap/omap_drm.c 2025-11-17 16:17:12.000000000 +0100 +++ new/libdrm-2.4.130/omap/omap_drm.c 2025-12-08 14:15:17.000000000 +0100 @@ -41,10 +41,6 @@ #include "omap_drm.h" #include "omap_drmif.h" -#define __round_mask(x, y) ((__typeof__(x))((y)-1)) -#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) -#define PAGE_SIZE 4096 - static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER; static void * dev_table; @@ -207,12 +203,6 @@ bo = bo_from_handle(dev, req.handle); pthread_mutex_unlock(&table_lock); - if (flags & OMAP_BO_TILED) { - bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height; - } else { - bo->size = size.bytes; - } - return bo; fail: @@ -432,7 +422,7 @@ drm_public void *omap_bo_map(struct omap_bo *bo) { if (!bo->map) { - if (!bo->offset) { + if (!bo->size || !bo->offset) { get_buffer_info(bo); }
