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Package is "cpuid" Mon Jun 15 19:50:20 2026 rev:26 rq:1359526 version:20260503 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2026-03-30 18:38:42.417636102 +0200 +++ /work/SRC/openSUSE:Factory/.cpuid.new.1981/cpuid.changes 2026-06-15 19:53:59.265946406 +0200 @@ -1,0 +2,11 @@ +Mon Jun 15 11:05:49 UTC 2026 - Jan Engelhardt <[email protected]> + +- Update to release 20260503 + * Added synth decoding for Medusa Point, Fire Range, Granite + Ridge, Ryzen 200, Hawk Point Refresh, Bartlett Lake, Xbox + Series S/X (ProjectX), Zhaoxin KaiXian/KX-7000, Wildcat Lake + * Added showing CPPC floor performance counter, Matrix Multiple & + Reversal instruction availability, RMPCHKD instruction + availability. + +------------------------------------------------------------------- Old: ---- cpuid-20260220.src.tar.gz New: ---- cpuid-20260503.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.xKjN4a/_old 2026-06-15 19:53:59.937974596 +0200 +++ /var/tmp/diff_new_pack.xKjN4a/_new 2026-06-15 19:53:59.937974596 +0200 @@ -17,7 +17,7 @@ Name: cpuid -Version: 20260220 +Version: 20260503 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later ++++++ _scmsync.obsinfo ++++++ --- /var/tmp/diff_new_pack.xKjN4a/_old 2026-06-15 19:54:00.001977280 +0200 +++ /var/tmp/diff_new_pack.xKjN4a/_new 2026-06-15 19:54:00.005977448 +0200 @@ -1,5 +1,5 @@ -mtime: 1774880551 -commit: 38d36fc00de49cef2d4ae4559a59bf0a2e2287fd90ad1e226cf58194903baae8 +mtime: 1781521628 +commit: 95b80270a5b46311e0401b0f9e183183f1842ea4d9169d904f8386574efc1437 url: https://src.opensuse.org/jengelh/cpuid revision: master ++++++ build.specials.obscpio ++++++ ++++++ build.specials.obscpio ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/.gitignore new/.gitignore --- old/.gitignore 1970-01-01 01:00:00.000000000 +0100 +++ new/.gitignore 2026-06-15 13:07:08.000000000 +0200 @@ -0,0 +1 @@ +.osc ++++++ cpuid-20260220.src.tar.gz -> cpuid-20260503.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20260220/ChangeLog new/cpuid-20260503/ChangeLog --- old/cpuid-20260220/ChangeLog 2026-02-20 14:43:56.000000000 +0100 +++ new/cpuid-20260503/ChangeLog 2026-05-03 16:27:32.000000000 +0200 @@ -1,3 +1,94 @@ +Sun May 3 2026 Todd Allen <[email protected]> + * Made new release. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Updated synth decoding for (0,6),(11,7),4 Bartlett Lake-S B0. + * cpuid.c: Added synth decoding for (0,6),(11,15),6 Bartlett Lake-S H0. + * cpuid.c: Added synth decoding for (0,6),(11,15),7 Bartlett Lake-S C0. + * cpuid.c: Added synth decoding for (0,6),(13,7) Bartlett Lake-S, + including 0=A0 stepping. Decodes E-cores in case any every show up. + * cpuid.man: Added intel doc 871433. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for (0,6),(13,5),1 Wildcat Lake A1. + * cpuid.man: Added Intel doc 914196. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x8000001b/eax IBS alternate disable bit support. + * cpuid.c: Added 0x8000001b/eax IBS fetch latency filtering support. + * cpuid.c: Added 0x8000001b/eax IBS address bit 63 filtering support. + * cpuid.c: Added 0x8000001b/eax IBS streaming store filtering support. + * cpuid.c: Added 0x8000001b/eax IBS buffering v1 support. + * cpuid.c: Added 0x8000001b/eax IBS memory profiler v1 support. + * cpuid.man: Added AMD 69205 doc. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000025/edx enhanced SMT protection support. + * cpuid.man: Added AMD 69204 doc. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000025/edx RMP dirty & RMPCHKD instruction support. + * cpuid.man: Added AMD 69203 doc. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x8000000a/ecx guest PMC event filtering supported. + * cpuid.man: Added AMD 69202 doc. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000025/edx RMPOPT support. + * cpuid.man: Added AMD 69201 doc. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000020/0/ebx GLBE: global bandwidth enforcement, + * cpuid.c: Added 0x80000020/0/ebx GLSBE: global slow bandwidth + enforcement. + * cpuid.c: Added 0x80000020/0/ebx PLZA: privilege level zero association. + * cpuid.c: Added 0x80000020/7 GLBE fields. + * cpuid.c: Added 0x80000020/8 GLSBE fields. + * cpuid.man: Added AMD 69193 doc. + +Sun May 3 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000001/ebx PkgType SP6/TR5 for Family 1A Model 02. + * cpuid.c: Renamed 0x8000001f to AMD Secure Encryption Virtualization. + * cpuid.c: Renamed 0x80000025 to AMD Secure Encryption Virtualization 2. + +Thu Apr 30 2026 Todd Allen <[email protected]> + * cpuid.c: Added uarch & synth decoding for (0,7),(6,11) Zhaoxin KaiXian + KX-7000 [Century Avenue]. + * cpuid.c: Added synth decoding for (0,6),(11,7),4 Bartlett Lake. + * cpuid.c: Added uarch & synth decoding for (8,15),(8,8) Microsoft + Xbox Series S/X (ProjectX). + +Sat Apr 18 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000021/eax bit matrix multiply & reversal instrs. + * cpuid.man: Added AMD 69192 doc. + +Wed Apr 15 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x8000000a/ecx PML: page modification logging supported. + * cpuid.man: Added AMD 69208 doc. + +Tue Apr 14 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x80000007/edx CPPC floor performance. + * cpuid.man: Added AMD 69206 doc. + +Sun Apr 5 2026 Todd Allen <[email protected]> + * cpuid.c: Merged display of 0x10 (RDT) and 0x28 (RDT-A) leaf registers, + because they are identical. + * cpuid.c: Added {0x10,0x28}/0/ebx bit 6: resource priority supported. + * cpuid.c: Added {0x10,0x28}/6 resource priority control sub-leaves. + +Mon Mar 30 2026 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for (0,6),(13,7) Core 200E Bartlett + Lake CPUs. + +Wed Mar 25 2026 Todd Allen <[email protected]> + * Added preliminary synth decoding for (11,15),(8,*) Medusa Point, + based on geekbench sample. + * Changed synth decoding for (11,15),(4,0-7) to include Fire Range, + the mobile variant of Granite Ridge. + * Changed synth decoding for (10,15),(7,0-7) to include Ryzen 200. + This is Hawk Point Refresh, but the same models as original Hawk Point. + Fri Feb 20 2026 Todd Allen <[email protected]> * Made new release. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20260220/FAMILY.NOTES new/cpuid-20260503/FAMILY.NOTES --- old/cpuid-20260220/FAMILY.NOTES 2026-02-18 15:17:20.000000000 +0100 +++ new/cpuid-20260503/FAMILY.NOTES 2026-05-03 16:24:54.000000000 +0200 @@ -49,14 +49,15 @@ 2017 9000 Series Coffee Lake refresh of Coffee Lake, spectre/meltdown LGA 1151 2019 10000 Series Comet Lake *optim of {Coffee, Whiskey} Lake (K,U) LGA 1200 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 2019 10000 Series Sunny Cove new architecture (Ice Lake) (10nm) 3rd (same) Whitley LGA 4189: P+ - 2020 11000 Series Willow Cove optim of Sunny Cove (Tiger Lake) (10nm) + 2019 10000 Series Sunny Cove new architecture (Ice Lake) (10nm) n/a 3rd (same) Whitley LGA 4189: P+ + 2020 11000 Series Willow Cove optim of Sunny Cove (Tiger Lake) (10nm) n/a 2021 Cypress Cove backport of Willow Cove (Rocket Lake) (14nm) LGA 1200 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2021 12000 Series Golden Cove new architecture (Alder Lake) (Intel 7) LGA 1700 4th Sapphire Rapids Eagle Stream LGA 4677 2022 13000 Series Raptor Cove modified Golden Cove (Raptor Lake) (Intel 7) LGA 1700 5th Emerald Rapids Eagle Stream LGA 4677 - 2023 14000 Series Raptor Cove refreshed Raptor Cove (Intel 7) - 2023 Core Ultra 100 Redwood Cove modified Raptor Cove (Meteor Lake) (Intel 4) 6th Granite Rapids Birch Stream LGA 7529 + 2023 14000 Series Raptor Cove refreshed Raptor Cove (Intel 7) LGA 1700 + 2026 Core 200 " " (Bartlett Lake) (Intel 7?) LGA 1700 + 2023 Core Ultra 100 Redwood Cove modified Raptor Cove (Meteor Lake) (Intel 4) LGA 1851 6th Granite Rapids Birch Stream LGA 7529 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2024 Core Ultra 200 Lion Cove new architecture (Arrow Lake (TSMC N3) desktop) LGA 1851 2024 " " " (Lunar Lake (TSMC N3B) AI/low power) BGA 2833 @@ -64,7 +65,6 @@ 2026 " " " (Wildcat Lake (Intel 18A) mobile) n/a ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ? Core Ultra 300? Lion Cove refresh of Lion Cove (Arrow Lake? (Intel 20A)) (2026) LGA 1851? - ? Raptor Cove (Bartlett Lake?) (2026?) LGA 1700? ? - Panther Cove? <-?-> 7th Diamond Rapids (2026) Oak Stream LGA 9324? ? Core Ultra 400? Coyote Cove? (Nova Lake? (Intel 18A?)) (2H 2026?) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -297,24 +297,37 @@ 7000: Dragon Range (MI300 super) 8000: Hawk Point + 200: Hawk Point refresh 2023 Zen 4c (N5) 4th Gen: 97p4: Bergamo{==Stones-dense?}(cloud) 4th Gen: 8cp4: Siena{==Stones-dense?}(edge) - 2024 Zen 5 (N4P) 9000: Granite Ridge 9000: Shimada Peak AI 300: Krackan Point 5th Gen: 9cp5: Turin{==Breithorn} - 5th Gen: 4cp5: Grado + 2024 Zen 5 (N4P) 9000: Granite Ridge 9000: Shimada Peak 9000: Fire Range + AI 300: Krackan Point 5th Gen: 9cp5: Turin{==Breithorn} + 5th Gen: 4cp5: Grado 2005: Grade/Fire Range? AI 300: Strix Point AI 300: Strix Halo{==Sarlak} 2024 Zen 5c (N3) 5th Gen: 9cp5: Turin-Dense{==Breithorn-dense} ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - ? 200: Hawk Point Refresh - ? 9000: Fire Range - ? Annapurna Embedded - ? AI ???: Bald Eagle Point? - ? ????: Gorgon Point? AI ???: Gorgon Point? - ? Escher? - ? 2027? Zen 6 10000: Medusa (2026)? 6th Gen: Venice{==Weisshorn} - Zen 6c 6th Gen: Monarch + 5th Gen: 8cp5: Turin-Dense{==Breithorn-dense} + AI 400: Gorgon Point? + ? Annapurna Embedded + ? 2026? Zen 6 ????: Olympic Ridge ????: Gator Range 6th Gen: Venice{==Weisshorn} + AI 400: Medusa Point AI 400: Medusa Point + Zen 6c 6th Gen: Venice-Dense? ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + uArch Code Names (that no one uses): + + Gen CCD Normal Dense (c) + ------------------------------------------------ + Zen Zeppelin + Zen+ Zeppelin + Zen 2 Aspen Highlands + Zen 3 Breckenrdige + Zen 4 Durango Persphone Dionysus + Zen 5 Eldora Nirvana Prometheus + Zen 6 ? Morpheus Monarch + ------------------------------------------------ + Ryzen = Desktop/Mobile Ryzen Threadripper = Desktop Enthusiast (64-core) EPYC = Server diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20260220/Makefile new/cpuid-20260503/Makefile --- old/cpuid-20260220/Makefile 2026-02-20 14:38:05.000000000 +0100 +++ new/cpuid-20260503/Makefile 2026-05-03 13:46:47.000000000 +0200 @@ -9,7 +9,7 @@ INSTALL_STRIP=-s PACKAGE=cpuid -VERSION=20260220 +VERSION=20260503 RELEASE=1 PROG=$(PACKAGE) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20260220/cpuid.c new/cpuid-20260503/cpuid.c --- old/cpuid-20260220/cpuid.c 2026-02-19 15:38:09.000000000 +0100 +++ new/cpuid-20260503/cpuid.c 2026-05-03 16:19:13.000000000 +0200 @@ -2465,6 +2465,7 @@ FMm ( 8,15, 6, 8, *u = "Zen 2", *p = "7nm"); // undocumented, but instlatx64 samples FMm ( 8,15, 7, 0, *u = "Zen 2", *p = "7nm"); // undocumented, but samples from Steven Noonan FMm ( 8,15, 8, 0, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via instlatx64 + FMm ( 8,15, 8, 8, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via Zone Me FMm ( 8,15, 9, 0, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via instlatx64 from @patrickschur_ FMm ( 8,15, 9, 8, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via instlatx64 from @zimogorets FMm ( 8,15, 10, 0, *u = "Zen 2", *p = "7nm"); // sample via instlatx64 from @ExecuFix @@ -2555,6 +2556,7 @@ FM (0, 7, 1,11, *u = "WuDaoKou", *p = "28nm"); // Google_cpu_features* FM (0, 7, 3,11, *u = "LuJiaZui", *p = "16nm"); // Google_cpu_features* FM (0, 7, 5,11, *u = "YongFeng", *p = "7nm"); // Google_cpu_features* (speculative?) + FM (0, 7, 6,11, *u = "Century Avenue"); // chipsandcheese.com article DEFAULT ((void)NULL); } @@ -3955,11 +3957,16 @@ FMSQ( 0, 6, 11, 7, 1, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX B0)"); FMSQ( 0, 6, 11, 7, 1, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX B0)"); FMS ( 0, 6, 11, 7, 1, "Intel (unknown type) (Raptor Lake-S/HX B0)"); + // Intel doc 871433: 8P+16E, 6P+8E, 6P+4E + FMSQ( 0, 6, 11, 7, 4, Ha, "Intel Core 200E E-core (Bartlett Lake-S B0)"); + FMSQ( 0, 6, 11, 7, 4, Hc, "Intel Core 200E P-core (Bartlett Lake-S B0)"); + FMSQ( 0, 6, 11, 7, 4, dc, "Intel Core 200E (Bartlett Lake-S B0)"); + FMS ( 0, 6, 11, 7, 4, "Intel (unknown type) (Bartlett Lake-S B0)"); FMQ ( 0, 6, 11, 7, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E)"); - FMQ ( 0, 6, 11, 7, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX)"); - FMQ ( 0, 6, 11, 7, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX)"); - FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX)"); - FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake-S/HX)"); + FMQ ( 0, 6, 11, 7, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX / Bartlett Lake-S)"); + FMQ ( 0, 6, 11, 7, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX / Bartlett Lake-S)"); + FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX / Bartlett Lake-S)"); + FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake-S/HX / Bartlett Lake-S)"); // Intel doc 740518 provides steppings 2 & 3, but without names // Intel doc 743844 provides steppings 2 & 3, with names! // ILPMDF* 20230214 contradicts it, saying 2=Q0, but it's prone to cut&paste @@ -4004,28 +4011,41 @@ // Intel doc 740518 provides steppings 2 & 5, but without names // Intel doc 743844 provides steppings 2 & 5, with names: C0 & H0. // ILPMDF* 20231114 confirms steppings C0 & H0. - // https://browser.geekbench.com/v6/cpu/12794012 finds a CPU with stepping 6, - // but with brand Intel Core 3 201TE, which Intel claims is "Bartlett Lake". - // Perhaps Bartlett Lake is just a branding distinction? FMSQ( 0, 6, 11,15, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 2, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)"); FMS ( 0, 6, 11,15, 2, "Intel (unknown type) (Raptor Lake-S/HX C0)"); + // Intel doc 871433: 6P+4E + FMSQ( 0, 6, 11,15, 3, Ha, "Intel Core 200E E-core (Bartlett Lake-S C0)"); + FMSQ( 0, 6, 11,15, 3, Hc, "Intel Core 200E P-core (Bartlett Lake-S C0)"); + FMSQ( 0, 6, 11,15, 3, dc, "Intel Core 200E (Bartlett Lake-S C0)"); + FMS ( 0, 6, 11,15, 3, "Intel (unknown type) (Bartlett Lake-S C0)"); + // (See stepping 2 above) FMSQ( 0, 6, 11,15, 5, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P H0)"); FMSQ( 0, 6, 11,15, 5, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P H0)"); FMSQ( 0, 6, 11,15, 5, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P H0)"); FMS ( 0, 6, 11,15, 5, "Intel (unknown type) (Raptor Lake-S/HX/P H0)"); - FMQ ( 0, 6, 11,15, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P)"); - FMQ ( 0, 6, 11,15, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P)"); - FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P)"); - FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/HX/P)"); + // Intel doc 871433: 4P+0E, 2P+0E + FMSQ( 0, 6, 11,15, 6, Ha, "Intel Core 200E E-core (Bartlett Lake-S H0)"); + FMSQ( 0, 6, 11,15, 6, Hc, "Intel Core 200E P-core (Bartlett Lake-S H0)"); + FMSQ( 0, 6, 11,15, 6, dc, "Intel Core 200E (Bartlett Lake-S H0)"); + FMS ( 0, 6, 11,15, 6, "Intel (unknown type) (Bartlett Lake-S H0)"); + // Intel doc 871433: 6P+4E + FMSQ( 0, 6, 11,15, 7, Ha, "Intel Core 200E E-core (Bartlett Lake-S C0)"); + FMSQ( 0, 6, 11,15, 7, Hc, "Intel Core 200E P-core (Bartlett Lake-S C0)"); + FMSQ( 0, 6, 11,15, 7, dc, "Intel Core 200E (Bartlett Lake-S C0)"); + FMS ( 0, 6, 11,15, 7, "Intel (unknown type) (Bartlett Lake-S C0)"); + FMQ ( 0, 6, 11,15, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P / Bartlett Lake-S)"); + FMQ ( 0, 6, 11,15, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P / Bartlett Lake-S)"); + FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P / Bartlett Lake-S)"); + FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/HX/P / Bartlett Lake-S)"); // Intel doc 834774 // ILPMDF* 20250512 confirms stepping 2 as A1. FMSQ( 0, 6, 12, 5, 2, dU, "Intel Core Ultra 2xxH (Arrow Lake-H A1)"); FMS ( 0, 6, 12, 5, 2, "Intel (unknown type) (Arrow Lake-H A1)"); FMQ ( 0, 6, 12, 5, dU, "Intel Core Ultra 2xxH (Arrow Lake-H)"); FM ( 0, 6, 12, 5, "Intel (unknown type) (Arrow Lake)"); - // Intel doc 834774 + // Intel doc 834774 (also 832586) // ILPMDF* 20250512 confirms stepping 2 as B0. FMSQ( 0, 6, 12, 6, 2, dU, "Intel Core Ultra 2xxS/HX (Arrow Lake-S/HX B0)"); FMS ( 0, 6, 12, 6, 2, "Intel (unknown type) (Arrow Lake-S B0)"); @@ -4043,7 +4063,15 @@ FM ( 0, 6, 12,15, "Intel Xeon (unknown type) (Emerald Rapids)"); FMS ( 0, 6, 13, 5, 0, "Intel (unknown type) (Wildcat Lake A0)"); // Coreboot* FM ( 0, 6, 13, 5, "Intel (unknown type) (Wildcat Lake)"); // Coreboot* - FM ( 0, 6, 13, 7, "Intel (unknown type) (Bartlett Lake)"); // LX* + // Intel doc 871433 12P+0E, 10P+0E, 8P+0E + FMSQ( 0, 6, 13, 7, 0, Ha, "Intel Core 200E E-core (Bartlett Lake-S A0)"); + FMSQ( 0, 6, 13, 7, 0, Hc, "Intel Core 200E P-core (Bartlett Lake-S A0)"); + FMSQ( 0, 6, 13, 7, 0, dc, "Intel Core 200E (Bartlett Lake-S A0)"); + FMS ( 0, 6, 13, 7, 0, "Intel (unknown type) (Bartlett Lake-S A0)"); + FMQ ( 0, 6, 13, 7, Ha, "Intel Core 200E E-core (Bartlett Lake-S)"); + FMQ ( 0, 6, 13, 7, Hc, "Intel Core 200E P-core (Bartlett Lake-S)"); + FMQ ( 0, 6, 13, 7, dc, "Intel Core 200E (Bartlett Lake-S)"); + FM ( 0, 6, 13, 7, "Intel (unknown type) (Bartlett Lake-S)"); FM ( 0, 6, 13,13, "Intel (unknown type) (Clearwater Forest)"); // MSR_CPUID_table* FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); @@ -4982,6 +5010,7 @@ FMm ( 8,15, 6, 8, "AMD Ryzen 5000 (Lucienne %c%u)"); // undocumented, but instlatx64 samples FMm ( 8,15, 7, 0, "AMD Ryzen 3000 (Matisse %c%u)"); // PPR 56176, samples from Steven Noonan FM ( 8,15, 8, 4, "AMD 4800S Desktop Kit (ProjectX)"); // undocumented, but sample via instlatx64 + FM ( 8,15, 8, 8, "AMD Microsoft Xbox Series S/X (ProjectX)"); // undocumented, but sample from Zone Me FMm ( 8,15, 9, 0, "AMD Custom APU: Steam Deck (Van Gogh %c%u)"); // undocumented, but samples from instlatx64 FMm ( 8,15, 9, 8, "AMD Custom APU: Magic Leap Demophon (Mero %c%u)"); // undocumented, but (engr?) sample via instlatx64 from @zimogorets FMm ( 8,15, 10, 0, "AMD Ryzen 7000 (Mendocino %c%u)"); // PPR 57243 @@ -5000,7 +5029,7 @@ FMmQ(10,15, 6, 0, sE, "AMD EPYC 4000 (Raphael %c%u)"); // PPR 56713 FMmQ(10,15, 6, 0, dR, "AMD Ryzen 7000 (Raphael %c%u)"); // PPR 56713 FMm (10,15, 6, 0, "AMD (unknown type) (Raphael %c%u)"); // PPR 56713 - FMm (10,15, 7, 0, "AMD Ryzen 7000/8000 (Phoenix/Hawk Point %c%u)"); // PPR 57019, instlatx64 sample of Ryzen 7 8845HS, which AMD also says is Hawk Point + FMm (10,15, 7, 0, "AMD Ryzen 7000/8000/200 (Phoenix/Hawk Point %c%u)"); // PPR 57019, instlatx64 sample of Ryzen 7 8845HS, which AMD also says is Hawk Point FM (10,15, 7,12, "AMD Ryzen (Hawk Point %c%u)"); // sample via instlatx64 from geekbench.com (special case only for model 12?) FMm (10,15, 7, 8, "AMD Ryzen (Phoenix 2 %c%u)"); // Coreboot* FMm (10,15, 8, 0, "AMD Instinct MI300C"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam @@ -5014,15 +5043,23 @@ FMm (11,15, 0, 8, "AMD EPYC (5th Gen) (Shimada Peak %c%u)"); FMm (11,15, 1, 0, "AMD EPYC (5th Gen) (Turin-Dense %c%u)"); // PPR 58730, LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 1, 8, "AMD EPYC (5th Gen) (Turin-Dense %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - // Are all these Strix Point's Ryzen AI 300 CPU's? + // Are (11,15),(2,*) all Strix Point's Ryzen AI 300 CPU's? // I suspect the latter ones are not. + // instlatx64 asserts that (11,15),(2,*) is EPYC (5th Gen) (Turin-Dense), + // but the sources don't make the connection to Turin-Dense. FMm (11,15, 2, 0, "AMD Ryzen AI 300 (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 2, 8, "AMD Ryzen AI 300 (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 0, "AMD Ryzen (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 8, "AMD Ryzen (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + // There is evidence of (11,15),(4,4) being: + // Ryzen 9 (many) (Granite Ridge) + // Ryzen 9 9850/9955HX/9955HX3D (Grado/Fire Range : AMD doesn't say) (geekbench samples) + // EPYC 4005 (Grado) + // Embedded EPYC 2005 (Fire Range) (instlatx64 claim) + // Is there any *good* way to differentiate? FMmQ(11,15, 4, 0, sE, "AMD EPYC 4005 (Grado %c%u)"); // undocumented, but screenshot via instlatx64 from https://www.phoronix.com/image-viewer.php?id=amd-epyc-4545p&image=amd_epyc_4545p_4_lrg - FMmQ(11,15, 4, 0, dR, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // PPR 57896 - FMm (11,15, 4, 0, "AMD (unknown type) (Granite Ridge/Grado %c%u)"); // PPR 57896 + FMmQ(11,15, 4, 0, dR, "AMD Ryzen 9000 (Granite Ridge/Fire Range %c%u)"); // PPR 57896 + FMm (11,15, 4, 0, "AMD (unknown type) (Granite Ridge/Fire Range/Grado %c%u)"); // PPR 57896 FMm (11,15, 4, 8, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 5, 0, "AMD EPYC (6th Gen) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 5, 8, "AMD EPYC (6th Gen) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian @@ -5031,6 +5068,8 @@ // PPR 57930, but it mentions no products and no architecture names FMm (11,15, 7, 0, "AMD Ryzen AI 300 (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 7, 8, "AMD Ryzen AI 300 (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 8, 0, "AMD Ryzen (Medusa Point %c%u)"); // undocumented, but sample via instlatx64 from geekbench.com + FMm (11,15, 8, 8, "AMD Ryzen (Medusa Point %c%u)"); // undocumented, but sample via instlatx64 from geekbench.com // An LLVM patch from AMD's Umesh Kalvakuntla mentions (11,15),(13,*) as // "Annapurna", presumably EPYC Embedded Annapurna. F (11,15, "AMD (unknown model)"); @@ -5146,6 +5185,7 @@ FM (0, 7, 1,11, "Zhaoxin KaiXian KX-5000 / Kaisheng KH-20000"); // Google_cpu_features* FMQ (0, 7, 3,11, vZ, "Zhaoxin KaiXian KX-6000 / Kaisheng KH-30000"); // instlatx64 example with CentaurHauls vendor! FMQ (0, 7, 5,11, vZ, "Zhaoxin Kaisheng KH-40000"); // Google_cpu_features* + FMQ (0, 7, 6,11, vZ, "Zhaoxin KaiXian KX-7000"); // instlatx64 sample DEFAULT ("unknown"); return result; @@ -7163,21 +7203,23 @@ } static void -print_10_0_ebx(unsigned int value) +print_10_28_0_ebx(unsigned int value) { static named_item names[] = { { "L3 cache allocation technology supported", 1, 1, bools }, { "L2 cache allocation technology supported", 2, 2, bools }, { "memory bandwidth allocation supported" , 3, 3, bools }, { "cache bandwidth allocation supported" , 5, 5, bools }, + { "resource priority supported" , 6, 6, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } +// Covers leaf 0x10 or 0x28, sub-leaf 1 or 2. static void -print_10_12_eax(unsigned int value) +print_10_28_1_2_eax(unsigned int value) { static named_item names[] = { { "length of capacity bit mask" , 0, 4, MINUS1_IMAGES }, @@ -7188,7 +7230,7 @@ } static void -print_10_12_ecx(unsigned int value) +print_10_28_1_ecx(unsigned int value) { static named_item names[] = { { "non-CPU agent support" , 1, 1, bools }, @@ -7201,10 +7243,11 @@ } static void -print_10_3_eax(unsigned int value) +print_10_28_2_ecx(unsigned int value) { static named_item names[] - = { { "maximum throttling value" , 0, 11, MINUS1_IMAGES }, + = { { "code and data prioritization supported" , 2, 2, bools }, + { "non-contiguous bitmask supported" , 3, 3, bools }, }; print_names(value, names, LENGTH(names), @@ -7212,10 +7255,21 @@ } static void -print_10_3_ecx(unsigned int value) +print_10_28_3_eax(unsigned int value) { static named_item names[] - = { { "per-thread MBA control" , 0, 0, bools }, + = { { "maximum MBA throttling value supported" , 0, 11, MINUS1_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void +print_10_28_3_ecx(unsigned int value) +{ + static named_item names[] + = { { "per-thread MBA control supported" , 0, 0, bools }, { "delay values are linear" , 2, 2, bools }, }; @@ -7224,12 +7278,12 @@ } static void -print_10_5_eax(unsigned int value) +print_10_28_5_eax(unsigned int value) { static ccstring scopes[1<<4] = { "invalid (0)", "logical processor (1)" }; static named_item names[] - = { { "maximum throttling value" , 0, 7, MINUS1_IMAGES }, + = { { "maximum core throttling value supported" , 0, 7, MINUS1_IMAGES }, { "QoS_Core_BW_Thrtl_n MSR scope" , 8, 11, scopes }, }; @@ -7238,10 +7292,10 @@ } static void -print_10_5_ecx(unsigned int value) +print_10_28_5_ecx(unsigned int value) { static ccstring linears[] = { "non-linear (0)", - "linear (1)" }; + "approx linear (1)" }; static named_item names[] = { { "bandwidth control response" , 3, 3, linears }, @@ -7252,7 +7306,7 @@ } static void -print_10_n_edx(unsigned int value) +print_10_28_n_edx(unsigned int value) { static named_item names[] = { { "highest COS number supported" , 0, 15, NIL_IMAGES }, @@ -7263,6 +7317,18 @@ } static void +print_10_28_6_eax(unsigned int value) +{ + static named_item names[] + = { { "per-thread enable supported" , 0, 0, bools }, + { "package enable supported" , 1, 1, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void print_12_0_eax(unsigned int value) { static named_item names[] @@ -7835,6 +7901,8 @@ /* max_len => */ 40); } +// Leaf 0x1f registers share code with leaf 0xb. + static void print_20_ebx(unsigned int value) { @@ -7925,6 +7993,12 @@ { "CNTR perf metrics subgroup support" , 6, 6, bools }, { "LBR bits support" , 8, 9, lbrs }, // Bits 17-23 correspond to XER bits 49-55 (32 bit offset) + // + // The -061 version of the Futures doc adjusted the leaf range to + // 16-23 (8 bits), and the XER bit range to the disjoint ranges 49-50 + // and 53-55 (5 bits total, or 7 bits including the hole). This + // is totally unclear. I'm not changing this code until I see a + // better description of the mapping. { "XER XMMn support" , 17, 17, bools }, { "XER YMMn Hi 128 support" , 18, 18, bools }, { "XER R16-R31 support" , 19, 19, bools }, @@ -7991,122 +8065,7 @@ /* max_len => */ 38); } -static void -print_28_0_ebx(unsigned int value) -{ - static named_item names[] - = { { "supports L3 Cache Allocation Technology" , 1, 1, bools }, - { "supports L2 Cache Allocation Technology" , 2, 2, bools }, - { "supports Memory Bandwidth Allocation" , 3, 3, bools }, - { "supports Cache Bandwidth Allocation" , 5, 5, bools }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 38); -} - -static void -print_28_1_eax(unsigned int value) -{ - static named_item names[] - = { { "length of capacity bit mask" , 0, 4, MINUS1_IMAGES }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_1_ecx(unsigned int value) -{ - static named_item names[] - = { { "supports L3 CAT for non-CPU agents" , 1, 1, bools }, - { "supports L3 Code & Data Prioritization" , 2, 2, bools }, - { "supports non-contiguous capacity bitmask", 3, 3, bools }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_2_eax(unsigned int value) -{ - static named_item names[] - = { { "length of capacity bit mask" , 0, 4, MINUS1_IMAGES }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_2_ecx(unsigned int value) -{ - static named_item names[] - = { { "supports L2 Code & Data Prioritization" , 2, 2, bools }, - { "supports non-contiguous capacity bitmask", 3, 3, bools }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_3_eax(unsigned int value) -{ - static named_item names[] - = { { "maximum MBA throttling value supported" , 0, 11, NIL_IMAGES }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_3_ecx(unsigned int value) -{ - static named_item names[] - = { { "supports per-thread MBA controls" , 0, 0, bools }, - { "delay response is linear" , 2, 2, bools }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_5_eax(unsigned int value) -{ - static named_item names[] - = { { "maximum core throttling value supported" , 0, 11, NIL_IMAGES }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_5_ecx(unsigned int value) -{ - static named_item names[] - = { { "bandwidth response is approx linear" , 3, 3, bools }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} - -static void -print_28_n_edx(unsigned int value) -{ - static named_item names[] - = { { "highest COS number supported" , 0, 15, NIL_IMAGES }, - }; - - print_names(value, names, LENGTH(names), - /* max_len => */ 40); -} +// Leaf 0x28 registers share code with leaf 0x10. static void print_29_0_ebx(unsigned int value) @@ -9194,7 +9153,10 @@ NULL, NULL, NULL, - "SP5 (4)" }; + "SP5 (4)", + NULL, + NULL, + "SP6/TR5 (7)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(4) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, @@ -9437,6 +9399,7 @@ { "connected standby" , 13, 13, bools }, { "RAPL: running average power limit" , 14, 14, bools }, { "fast CPPC" , 15, 15, bools }, + { "CPPC floor performance" , 16, 16, bools }, }; printf(" Advanced Power Management Features (0x80000007/edx):\n"); @@ -9589,7 +9552,9 @@ print_8000000a_ecx(unsigned int value) { static named_item names[] - = { { "x2AVIC_EXT: 4096 vCPUs supported" , 6, 6, bools }, + = { { "guest PMC event filtering supported" , 3, 3, bools }, + { "PML: page modification logging supported", 4, 4, bools }, + { "x2AVIC_EXT: 4096 vCPUs supported" , 6, 6, bools }, }; print_names(value, names, LENGTH(names), @@ -9665,6 +9630,12 @@ { "IBS op data 4 MSR support" , 10, 10, bools }, { "IBS L3 miss filtering support" , 11, 11, bools }, { "IBS load latency filtering support" , 12, 12, bools }, + { "IBS alternate disable bit support" , 13, 13, bools }, + { "IBS fetch latency filtering support" , 14, 14, bools }, + { "IBS address bit 63 filtering support" , 15, 15, bools }, + { "IBS streaming store filtering support" , 16, 16, bools }, + { "IBS buffering v1 support" , 17, 17, bools }, + { "IBS memory profiler v1 support" , 18, 18, bools }, { "simplified DTLB page size & miss report" , 19, 19, bools }, }; @@ -9927,6 +9898,9 @@ { "L3 range reservation support" , 4, 4, bools }, { "assignable bandwidth monitoring counters", 5, 5, bools }, { "SDCI allocation enforcement" , 6, 6, bools }, + { "GLBE: global bandwidth enforcement" , 7, 7, bools }, + { "GLSBE: global slow bandwidth enforcement", 8, 8, bools }, + { "PLZA: privilege level zero association" , 9, 9, bools }, }; print_names(value, names, LENGTH(names), @@ -10003,6 +9977,21 @@ } static void +print_80000020_78_ebx(unsigned int value) +{ + static named_item names[] + = { { "bandwidth ceiling units (1/8 GB/s)" , 0, 15, MINUS1_IMAGES }, + }; + print_names(value, names, LENGTH(names), + /* max_len => */ 34); + + unsigned int units_raw = BIT_EXTRACT_LE(value, 0, 16) + 1; + unsigned int units_MBs = units_raw * 128; + printf(" bandwidth ceiling units = %u MB/s = %f GB/s\n", + units_MBs, (double)units_MBs / 1024.0); +} + +static void print_80000021_eax(unsigned int value) { static named_item names[] @@ -10028,6 +10017,7 @@ { "IC PREFETCH support" , 20, 20, bools }, { "FP512 is downgraded to FP256" , 21, 21, bools }, { "workload OS feedback support" , 22, 22, bools }, // LX* calls this ABMC: Assignable Bandwidth Monitoring Counters + { "bit matrix multiply & reversal instrs" , 23, 23, bools }, { "ret addr predictor security support" , 24, 24, bools }, { "guest: selective branch pred barrier" , 27, 27, bools }, { "guest: PRED_CMD[IBPB] flushes br predict", 28, 28, bools }, @@ -10126,7 +10116,7 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 34); + /* max_len => */ 39); } static void @@ -10139,7 +10129,20 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 34); + /* max_len => */ 39); +} + +static void +print_80000025_edx(unsigned int value) +{ + static named_item names[] + = { { "RMPOPT support" , 0, 0, bools }, + { "enhanced SMT protection support" , 1, 1, bools }, + { "RMP dirty & RMPCHKD instruction support" , 2, 2, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 39); } static void @@ -10948,28 +10951,34 @@ } else if (reg == 0x10) { if (sub == 0) { printf(" Resource Director Technology Allocation (0x10/0):\n"); - print_10_0_ebx(words[WORD_EBX]); - } else if (sub == 1 || sub == 2) { - if (sub == 1) { - printf(" L3 Cache Allocation Technology (0x10/1):\n"); - } else if (sub == 2) { - printf(" L2 Cache Allocation Technology (0x10/2):\n"); - } - print_10_12_eax(words[WORD_EAX]); - printf(" Bit-granular map of isolation/contention = 0x%08x\n", + print_10_28_0_ebx(words[WORD_EBX]); + } else if (sub == 1) { + printf(" L3 Cache Allocation Technology (0x10/1):\n"); + print_10_28_1_2_eax(words[WORD_EAX]); + print_10_28_1_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); + printf(" alloc units isolation/contention map = 0x%08x\n", + words[WORD_EBX]); + } else if (sub == 2) { + printf(" L2 Cache Allocation Technology (0x10/2):\n"); + print_10_28_1_2_eax(words[WORD_EAX]); + print_10_28_2_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); + printf(" alloc units isolation/contention map = 0x%08x\n", words[WORD_EBX]); - print_10_12_ecx(words[WORD_ECX]); - print_10_n_edx(words[WORD_EDX]); } else if (sub == 3) { printf(" Memory Bandwidth Allocation (0x10/3):\n"); - print_10_3_eax(words[WORD_EAX]); - print_10_3_ecx(words[WORD_ECX]); - print_10_n_edx(words[WORD_EDX]); + print_10_28_3_eax(words[WORD_EAX]); + print_10_28_3_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); } else if (sub == 5) { printf(" Cache Bandwidth Allocation (0x10/5):\n"); - print_10_5_eax(words[WORD_EAX]); - print_10_5_ecx(words[WORD_ECX]); - print_10_n_edx(words[WORD_EDX]); + print_10_28_5_eax(words[WORD_EAX]); + print_10_28_5_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); + } else if (sub == 6) { + printf(" Resource Priority Control (0x10/6):\n"); + print_10_28_6_eax(words[WORD_EAX]); } else { print_reg_raw(reg, sub, words); } @@ -11214,32 +11223,37 @@ } } else if (reg == 0x28) { if (sub == 0) { - printf(" Intel RDT-A Asymmetric (0x28/0):\n"); - print_28_0_ebx(words[WORD_EBX]); + printf(" RDT-A Asymmetric (0x28/0):\n"); + print_10_28_0_ebx(words[WORD_EBX]); } else if (sub == 1) { - printf(" Intel RDT-A Asymmetric: L3 Cache (0x28/1):\n"); - print_28_1_eax(words[WORD_EAX]); - print_28_1_ecx(words[WORD_ECX]); - print_28_n_edx(words[WORD_EDX]); + printf(" RDT-A Asymmetric: L3 Cache Allocation Technology" + " (0x28/1):\n"); + print_10_28_1_2_eax(words[WORD_EAX]); + print_10_28_1_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); printf(" alloc units isolation/contention map = 0x%08x\n", words[WORD_EBX]); } else if (sub == 2) { - printf(" Intel RDT-A Asymmetric: L2 Cache (0x28/2):\n"); - print_28_2_eax(words[WORD_EAX]); - print_28_2_ecx(words[WORD_ECX]); - print_28_n_edx(words[WORD_EDX]); + printf(" RDT-A Asymmetric: L2 Cache Allocation Technology" + " (0x28/2):\n"); + print_10_28_1_2_eax(words[WORD_EAX]); + print_10_28_2_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); printf(" alloc units isolation/contention map = 0x%08x\n", words[WORD_EBX]); } else if (sub == 3) { - printf(" Intel RDT-A Asymmetric: Memory Bandwidth (0x28/3):\n"); - print_28_3_eax(words[WORD_EAX]); - print_28_3_ecx(words[WORD_ECX]); - print_28_n_edx(words[WORD_EDX]); + printf(" RDT-A Asymmetric: Memory Bandwidth (0x28/3):\n"); + print_10_28_3_eax(words[WORD_EAX]); + print_10_28_3_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); } else if (sub == 5) { - printf(" Intel RDT-A Asymmetric: Cache Bandwidth (0x28/5):\n"); - print_28_5_eax(words[WORD_EAX]); - print_28_5_ecx(words[WORD_ECX]); - print_28_n_edx(words[WORD_EDX]); + printf(" RDT-A Asymmetric: Cache Bandwidth (0x28/5):\n"); + print_10_28_5_eax(words[WORD_EAX]); + print_10_28_5_ecx(words[WORD_ECX]); + print_10_28_n_edx(words[WORD_EDX]); + } else if (sub == 6) { + printf(" RDT-A Asymmetric: Resource Priority Control (0x28/6):\n"); + print_10_28_6_eax(words[WORD_EAX]); } else { print_reg_raw(reg, sub, words); } @@ -11520,7 +11534,7 @@ } print_8000001e_ecx(words[WORD_ECX]); } else if (reg == 0x8000001f) { - printf(" AMD Secure Encryption (0x8000001f):\n"); + printf(" AMD Secure Encryption Virtualization (0x8000001f):\n"); print_8000001f_eax(words[WORD_EAX]); print_8000001f_ebx(words[WORD_EBX]); printf(" number of SEV-enabled guests supported = 0x%0x (%u)\n", @@ -11558,6 +11572,22 @@ print_80000020_5_eax(words[WORD_EAX]); print_80000020_5_ebx(words[WORD_EBX]); print_80000020_5_ecx(words[WORD_ECX]); + } else if (sub == 7) { + printf(" PQoS Global Memory Bandwidth Enforcement" + " (0x80000020/7):\n"); + printf(" ceiling width = 0x%0x (%u)\n", + words[WORD_EAX], words[WORD_EAX]); + print_80000020_78_ebx(words[WORD_EBX]); + printf(" number of classes of service = 0x%0x (%u)\n", + words[WORD_EDX], words[WORD_EDX]); + } else if (sub == 8) { + printf(" PQoS Global Memory Slow Bandwidth Enforcement" + " (0x80000020/7):\n"); + printf(" ceiling width = 0x%0x (%u)\n", + words[WORD_EAX], words[WORD_EAX]); + print_80000020_78_ebx(words[WORD_EBX]); + printf(" number of classes of service = 0x%0x (%u)\n", + words[WORD_EDX], words[WORD_EDX]); } else { print_reg_raw(reg, sub, words); } @@ -11577,9 +11607,10 @@ print_80000023_eax(words[WORD_EAX]); print_80000023_ebx(words[WORD_EBX]); } else if (reg == 0x80000025) { - printf(" Segmented RMP Table (0x80000025):\n"); + printf(" AMD Secure Encryption Virtualization 2 (0x80000025):\n"); print_80000025_eax(words[WORD_EAX]); print_80000025_ebx(words[WORD_EBX]); + print_80000025_edx(words[WORD_EDX]); } else if (reg == 0x80000026) { /* Similar to 0xb & 0x1f, but with extra bit fields */ if (sub == 0) { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20260220/cpuid.man new/cpuid-20260503/cpuid.man --- old/cpuid-20260220/cpuid.man 2026-02-20 14:43:36.000000000 +0100 +++ new/cpuid-20260503/cpuid.man 2026-05-03 16:28:22.000000000 +0200 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20260220 2026/02/20 06:43:23 todd $ +.\" $Id: cpuid.man,v 20260220 2026/05/03 08:28:07 todd $ .\" -.TH CPUID 1 "20 Feb 2026" "20260220" +.TH CPUID 1 "3 May 2026" "20260503" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -572,8 +572,12 @@ .br 869992: Intel Core Ultra Processors (Series 3) Specification Update .br +871433: Intel Core Series 2 Processor for Edge Platforms Datasheet +.br 872188: Intel Core Ultra Processors (Series 3) Datasheet, Volume 1 of 2 .br +914196: Intel Core Processors (Series 3) Specification Update +.br Intel Microcode Update Guidance .br Branch History Injection and Intra-mode Branch Target Injection / @@ -712,6 +716,25 @@ .br 58730: AMD Revision Guide for AMD Family 1Ah Models 10h-1Fh Processors .br +69192: AMD64 Bit Matrix Multiply and Bit Reversal Instructions +.br +69193: AMD64 Zen6 Platform Quality of Service (PQOS) Extensions +.br +69201: AMD64 RMPOPT +.br +69202: AMD64 Guest PMC Event Filtering +.br +69203: AMD64 RMP Dirty +.br +69204: AMD64 Enhanced SMT Protection +.br +69205: AMD64 Zen6 Instruction Based Sampling (IBS) Extensions and Features +.br +69206: AMD64 Collaborative Processor Performance Control (CPPC) Performance +Priority +.br +69208: AMD64 Page Modification Logging +.br AMD64 Technology Indirect Branch Control Extension (White Paper), Revision 4.10.18 .br diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20260220/cpuid.spec new/cpuid-20260503/cpuid.spec --- old/cpuid-20260220/cpuid.spec 2026-02-20 14:44:46.000000000 +0100 +++ new/cpuid-20260503/cpuid.spec 2026-05-03 16:29:04.000000000 +0200 @@ -1,4 +1,4 @@ -%define version 20260220 +%define version 20260503 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
