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Hello community,
here is the log from the commit of package spirv-llvm-translator for
openSUSE:Factory checked in at 2026-11-05 18:19:20
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/spirv-llvm-translator (Old)
and /work/SRC/openSUSE:Factory/.spirv-llvm-translator.new.3759290 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "spirv-llvm-translator"
Thu Nov 5 18:19:20 2026 rev:37 rq:1394805 version:23.1.3
Changes:
--------
---
/work/SRC/openSUSE:Factory/spirv-llvm-translator/spirv-llvm-translator.changes
2026-10-13 17:43:19.445233001 +0200
+++
/work/SRC/openSUSE:Factory/.spirv-llvm-translator.new.3759290/spirv-llvm-translator.changes
2026-11-05 18:19:28.387587652 +0100
@@ -1,0 +2,11 @@
+Sun Nov 1 22:24:14 UTC 2026 - Aaron Puchert <[email protected]>
+
+- Update to version 23.1.3.
+ * Emit FPFastMathMode for Call.
+ * Rework translation of memset to restore better performance.
+ * Add support for SPV_INTEL_subgroup_bitcast_shuffle.
+- Add Add-support-for-SPV_INTEL_subgroup_bitcast_shuffle.patch to
+ revert latest change: our version of spirv-headers doesn't have
+ the extension yet.
+
+-------------------------------------------------------------------
Old:
----
SPIRV-LLVM-Translator-23.1.2.tar.gz
New:
----
Add-support-for-SPV_INTEL_subgroup_bitcast_shuffle.patch
SPIRV-LLVM-Translator-23.1.3.tar.gz
----------(New B)----------
New: * Add support for SPV_INTEL_subgroup_bitcast_shuffle.
- Add Add-support-for-SPV_INTEL_subgroup_bitcast_shuffle.patch to
revert latest change: our version of spirv-headers doesn't have
----------(New E)----------
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ spirv-llvm-translator.spec ++++++
--- /var/tmp/diff_new_pack.65XlWC/_old 2026-11-05 18:19:29.152619132 +0100
+++ /var/tmp/diff_new_pack.65XlWC/_new 2026-11-05 18:19:29.154619214 +0100
@@ -23,7 +23,7 @@
%define sover 23
Name: spirv-llvm-translator
-Version: 23.1.2
+Version: 23.1.3
Release: 0
Summary: LLVM/SPIR-V Bi-Directional Translator library
License: BSD-3-Clause
@@ -31,6 +31,7 @@
URL: https://github.com/KhronosGroup/SPIRV-LLVM-Translator
Source:
https://github.com/KhronosGroup/SPIRV-LLVM-Translator/archive/refs/tags/v%{version}.tar.gz#/SPIRV-LLVM-Translator-%{version}.tar.gz
Source101: %{name}.rpmlintrc
+Patch1: Add-support-for-SPV_INTEL_subgroup_bitcast_shuffle.patch
BuildRequires: cmake >= 3.3
BuildRequires: gcc%{?gcc_version} >= 9
BuildRequires: gcc%{?gcc_version}-c++ >= 9
@@ -66,6 +67,7 @@
%prep
%setup -q -n SPIRV-LLVM-Translator-%{version}
+%patch -P1 -p1 -R
%build
%cmake \
++++++ Add-support-for-SPV_INTEL_subgroup_bitcast_shuffle.patch ++++++
>From db5855d76a0ff33228bcf48032b350b25dcdbcf2 Mon Sep 17 00:00:00 2001
From: Piotr Kanclerz <[email protected]>
Date: Thu, 29 Oct 2026 16:45:41 +0100
Subject: [PATCH] [Backport to 23] Add support for
SPV_INTEL_subgroup_bitcast_shuffle (#4022) (#4124)
Spec:
https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle.html
Also includes the fix from #4121 removing the duplicated
SubgroupBitcastShuffleINTEL name map entry.
Co-authored-by: Ben Ashbaugh <[email protected]>
---
include/LLVMSPIRVExtensions.inc | 1 +
lib/SPIRV/SPIRVReader.cpp | 6 +-
lib/SPIRV/libSPIRV/SPIRVEntry.h | 2 +
lib/SPIRV/libSPIRV/SPIRVInstruction.h | 14 +
lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 1 +
lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h | 1 +
spirv-headers-tag.conf | 2 +-
.../bitcast_shuffle.ll | 276 ++++++++++++++++++
8 files changed, 300 insertions(+), 3 deletions(-)
create mode 100644
test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc
index af89697f9f..c1bf59a4cd 100644
--- a/include/LLVMSPIRVExtensions.inc
+++ b/include/LLVMSPIRVExtensions.inc
@@ -81,6 +81,7 @@ EXT(SPV_INTEL_task_sequence)
EXT(SPV_INTEL_maximum_registers)
EXT(SPV_INTEL_bindless_images)
EXT(SPV_INTEL_2d_block_io)
+EXT(SPV_INTEL_subgroup_bitcast_shuffle)
EXT(SPV_INTEL_subgroup_matrix_multiply_accumulate)
EXT(SPV_INTEL_subgroup_matrix_multiply_accumulate_float4)
EXT(SPV_INTEL_subgroup_matrix_multiply_accumulate_float8)
diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp
index bc87849405..7c4ccb2b3d 100644
--- a/lib/SPIRV/SPIRVReader.cpp
+++ b/lib/SPIRV/SPIRVReader.cpp
@@ -4007,7 +4007,7 @@ Instruction *SPIRVToLLVM::transBuiltinFromInst(const
std::string &FuncName,
Func->addFnAttr(Attribute::NoUnwind);
if (isGroupOpCode(OC) || isGroupNonUniformOpcode(OC) ||
isIntelSubgroupOpCode(OC) || isSplitBarrierINTELOpCode(OC) ||
- OC == OpControlBarrier)
+ OC == OpSubgroupBitcastShuffleINTEL || OC == OpControlBarrier)
Func->addFnAttr(Attribute::Convergent);
}
CallInst *Call;
@@ -4189,6 +4189,7 @@ Instruction
*SPIRVToLLVM::transSPIRVBuiltinFromInst(SPIRVInstruction *BI,
case internal::OpClampConvertFToSINTEL:
case internal::OpStochasticRoundFToFINTEL:
case internal::OpClampStochasticRoundFToSINTEL:
+ case OpSubgroupBitcastShuffleINTEL:
// Old opcodes, for backward compatibility.
case internal::OpClampConvertFToFINTEL:
case internal::OpClampStochasticRoundFToFINTEL:
@@ -4202,13 +4203,14 @@ Instruction
*SPIRVToLLVM::transSPIRVBuiltinFromInst(SPIRVInstruction *BI,
}
bool IsRetSigned = true;
- switch (OC) {
+ switch (static_cast<size_t>(OC)) {
case OpConvertFToU:
case OpSatConvertSToU:
case OpUConvert:
case OpUDotKHR:
case OpUDotAccSatKHR:
case OpReadClockKHR:
+ case OpSubgroupBitcastShuffleINTEL:
IsRetSigned = false;
break;
case OpImageRead:
diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.h b/lib/SPIRV/libSPIRV/SPIRVEntry.h
index e3f94484d6..27dcef0bd0 100644
--- a/lib/SPIRV/libSPIRV/SPIRVEntry.h
+++ b/lib/SPIRV/libSPIRV/SPIRVEntry.h
@@ -945,6 +945,8 @@ class SPIRVCapability : public SPIRVEntryNoId<OpCapability>
{
case CapabilityVectorComputeINTEL:
case CapabilityVectorAnyINTEL:
return ExtensionID::SPV_INTEL_vector_compute;
+ case CapabilitySubgroupBitcastShuffleINTEL:
+ return ExtensionID::SPV_INTEL_subgroup_bitcast_shuffle;
case internal::CapabilitySubgroupRequirementsINTEL:
return ExtensionID::SPV_INTEL_subgroup_requirements;
case CapabilityFPFastMathModeINTEL:
diff --git a/lib/SPIRV/libSPIRV/SPIRVInstruction.h
b/lib/SPIRV/libSPIRV/SPIRVInstruction.h
index ff803fb696..9dbfa0a120 100644
--- a/lib/SPIRV/libSPIRV/SPIRVInstruction.h
+++ b/lib/SPIRV/libSPIRV/SPIRVInstruction.h
@@ -4856,6 +4856,20 @@ _SPIRV_OP_FTOF(StochasticRoundFToF, true, 5, true)
_SPIRV_OP_FTOF(ClampStochasticRoundFToF, true, 5, true)
#undef _SPIRV_OP_FTOF
+class SPIRVSubgroupBitcastShuffleINTELInst : public SPIRVInstTemplateBase {
+public:
+ std::optional<ExtensionID> getRequiredExtension() const override {
+ return ExtensionID::SPV_INTEL_subgroup_bitcast_shuffle;
+ }
+ SPIRVCapVec getRequiredCapability() const override {
+ return getVec(CapabilitySubgroupBitcastShuffleINTEL);
+ }
+};
+
+typedef SPIRVInstTemplate<SPIRVSubgroupBitcastShuffleINTELInst,
+ OpSubgroupBitcastShuffleINTEL, true, 4>
+ SPIRVSubgroupBitcastShuffleINTEL;
+
class SPIRVFPConversionFtoSINTELInstBase : public SPIRVInstTemplateBase {
public:
SPIRVCapVec getRequiredCapability() const override {
diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
index cfd7e90da4..4104cc5f64 100644
--- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
+++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -565,6 +565,7 @@ template <> inline void SPIRVMap<Capability,
std::string>::init() {
add(CapabilityDemoteToHelperInvocation, "DemoteToHelperInvocation");
add(CapabilityDemoteToHelperInvocationEXT, "DemoteToHelperInvocationEXT");
add(CapabilityBindlessTextureNV, "BindlessTextureNV");
+ add(CapabilitySubgroupBitcastShuffleINTEL, "SubgroupBitcastShuffleINTEL");
add(CapabilitySubgroupShuffleINTEL, "SubgroupShuffleINTEL");
add(CapabilitySubgroupBufferBlockIOINTEL, "SubgroupBufferBlockIOINTEL");
add(CapabilitySubgroupBufferPrefetchINTEL, "SubgroupBufferPrefetchINTEL");
diff --git a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
index ab96b81a9e..2857d4c07e 100644
--- a/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
+++ b/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
@@ -578,6 +578,7 @@ _SPIRV_OP(ConvertBF16ToFINTEL, 6117)
_SPIRV_OP(ControlBarrierArriveINTEL, 6142)
_SPIRV_OP(ControlBarrierWaitINTEL, 6143)
_SPIRV_OP(ArithmeticFenceEXT, 6145)
+_SPIRV_OP(SubgroupBitcastShuffleINTEL, 6208)
_SPIRV_OP(SubgroupBlockPrefetchINTEL, 6221)
_SPIRV_OP(Subgroup2DBlockLoadINTEL, 6231)
_SPIRV_OP(Subgroup2DBlockLoadTransformINTEL, 6232)
diff --git a/spirv-headers-tag.conf b/spirv-headers-tag.conf
index 708c8a3749..c10d046927 100644
--- a/spirv-headers-tag.conf
+++ b/spirv-headers-tag.conf
@@ -1 +1 @@
-575b6512579ebde466ed3dfc04e413439d14d95d
+cb42dec3830d3ac67fa449ecdc0c0f73d5e74498
diff --git
a/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
b/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
new file mode 100644
index 0000000000..983e6417c4
--- /dev/null
+++
b/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
@@ -0,0 +1,276 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_subgroup_bitcast_shuffle -o
%t.spv
+; RUN: llvm-spirv %t.spv --to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; RUN: not llvm-spirv %t.bc 2>&1 -o %t.err.spv | FileCheck %s
--check-prefix=CHECK-ERROR
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V
extension:
+; CHECK-ERROR-NEXT: SPV_INTEL_subgroup_bitcast_shuffle
+
+; CHECK-SPIRV-DAG: Capability SubgroupBitcastShuffleINTEL
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_subgroup_bitcast_shuffle"
+
+; CHECK-SPIRV-DAG: TypeInt [[#TI8:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#TI16:]] 16 0
+; CHECK-SPIRV-DAG: TypeInt [[#TI32:]] 32 0
+; CHECK-SPIRV-DAG: TypeInt [[#TI64:]] 64 0
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I8:]] [[#TI8]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I8:]] [[#TI8]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I8:]] [[#TI8]] 8
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I16:]] [[#TI16]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I16:]] [[#TI16]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I32:]] [[#TI32]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV16I8:]] [[#TI8]] 16
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I16:]] [[#TI16]] 8
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I32:]] [[#TI32]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I64:]] [[#TI64]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV16I16:]] [[#TI16]] 16
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I32:]] [[#TI32]] 8
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I64:]] [[#TI64]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV16I32:]] [[#TI32]] 16
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I64:]] [[#TI64]] 8
+
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I32]]
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_16bit()
+; CHECK-LLVM: call spir_func i16
@_Z43__spirv_SubgroupBitcastShuffleINTEL_RushortDv2_c(<2 x i8>
+; CHECK-LLVM: call spir_func <2 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar2s(i16
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_32bit()
+; CHECK-LLVM: call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2Dv4_c(<4 x i8>
+; CHECK-LLVM: call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4Dv2_s(<2 x i16>
+; CHECK-LLVM: call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv4_c(<4 x i8>
+; CHECK-LLVM: call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4i(i32
+; CHECK-LLVM: call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv2_s(<2 x i16>
+; CHECK-LLVM: call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2i(i32
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_64bit()
+; CHECK-LLVM: call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv8_c(<8 x i8>
+; CHECK-LLVM: call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv4_s(<4 x i16>
+; CHECK-LLVM: call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv8_c(<8 x i8>
+; CHECK-LLVM: call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv2_i(<2 x i32>
+; CHECK-LLVM: call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv8_c(<8 x i8>
+; CHECK-LLVM: call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8l(i64
+; CHECK-LLVM: call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv4_s(<4 x i16>
+; CHECK-LLVM: call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv2_i(<2 x i32>
+; CHECK-LLVM: call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv4_s(<4 x i16>
+; CHECK-LLVM: call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4l(i64
+; CHECK-LLVM: call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv2_i(<2 x i32>
+; CHECK-LLVM: call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2l(i64
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_128bit()
+; CHECK-LLVM: call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv16_c(<16 x i8>
+; CHECK-LLVM: call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv8_s(<8 x i16>
+; CHECK-LLVM: call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv16_c(<16 x i8>
+; CHECK-LLVM: call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv4_i(<4 x i32>
+; CHECK-LLVM: call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv16_c(<16 x i8>
+; CHECK-LLVM: call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv2_l(<2 x i64>
+; CHECK-LLVM: call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv8_s(<8 x i16>
+; CHECK-LLVM: call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv4_i(<4 x i32>
+; CHECK-LLVM: call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv8_s(<8 x i16>
+; CHECK-LLVM: call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv2_l(<2 x i64>
+; CHECK-LLVM: call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv4_i(<4 x i32>
+; CHECK-LLVM: call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv2_l(<2 x i64>
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_256bit()
+; CHECK-LLVM: call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv16_s(<16 x i16>
+; CHECK-LLVM: call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv8_i(<8 x i32>
+; CHECK-LLVM: call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv16_s(<16 x i16>
+; CHECK-LLVM: call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv4_l(<4 x i64>
+; CHECK-LLVM: call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv8_i(<8 x i32>
+; CHECK-LLVM: call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv4_l(<4 x i64>
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_512bit()
+; CHECK-LLVM: call spir_func <8 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong8Dv16_i(<16 x i32>
+; CHECK-LLVM: call spir_func <16 x i32>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruint16Dv8_l(<8 x i64>
+
+target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir"
+
+define spir_kernel void @test_16bit() {
+entry:
+ %v2i8 = load <2 x i8>, ptr undef
+ %s16 = load i16, ptr undef
+
+ %r2x8to16 = call spir_func i16
@_Z43__spirv_SubgroupBitcastShuffleINTEL_RushortDv2_c(<2 x i8> %v2i8)
+ %r16to2x8 = call spir_func <2 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar2s(i16 %s16)
+ ret void
+}
+
+define spir_kernel void @test_32bit() {
+entry:
+ %v4i8 = load <4 x i8>, ptr undef
+ %v2i16 = load <2 x i16>, ptr undef
+ %s32 = load i32, ptr undef
+
+ %r4x8to2x16 = call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2Dv4_c(<4 x i8> %v4i8)
+ %r2x16to4x8 = call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4Dv2_s(<2 x i16> %v2i16)
+ %r4x8to32 = call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv4_c(<4 x i8> %v4i8)
+ %r32to4x8 = call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4i(i32 %s32)
+ %r2x16to32 = call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv2_s(<2 x i16> %v2i16)
+ %r32to2x16 = call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2i(i32 %s32)
+ ret void
+}
+
+define spir_kernel void @test_64bit() {
+entry:
+ %v8i8 = load <8 x i8>, ptr undef
+ %v4i16 = load <4 x i16>, ptr undef
+ %v2i32 = load <2 x i32>, ptr undef
+ %s64 = load i64, ptr undef
+
+ %r8x8to4x16 = call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv8_c(<8 x i8> %v8i8)
+ %r4x16to8x8 = call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv4_s(<4 x i16> %v4i16)
+ %r8x8to2x32 = call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv8_c(<8 x i8> %v8i8)
+ %r2x32to8x8 = call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv2_i(<2 x i32> %v2i32)
+ %r8x8to64 = call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv8_c(<8 x i8> %v8i8)
+ %r64to8x8 = call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8l(i64 %s64)
+ %r4x16to2x32 = call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv4_s(<4 x i16> %v4i16)
+ %r2x32to4x16 = call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv2_i(<2 x i32> %v2i32)
+ %r4x16to64 = call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv4_s(<4 x i16> %v4i16)
+ %r64to4x16 = call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4l(i64 %s64)
+ %r2x32to64 = call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv2_i(<2 x i32> %v2i32)
+ %r64to2x32 = call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2l(i64 %s64)
+ ret void
+}
+
+define spir_kernel void @test_128bit() {
+entry:
+ %v16i8 = load <16 x i8>, ptr undef
+ %v8i16 = load <8 x i16>, ptr undef
+ %v4i32 = load <4 x i32>, ptr undef
+ %v2i64 = load <2 x i64>, ptr undef
+
+ %r16x8to8x16 = call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv16_c(<16 x i8> %v16i8)
+ %r8x16to16x8 = call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv8_s(<8 x i16> %v8i16)
+ %r16x8to4x32 = call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv16_c(<16 x i8> %v16i8)
+ %r4x32to16x8 = call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv4_i(<4 x i32> %v4i32)
+ %r16x8to2x64 = call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv16_c(<16 x i8> %v16i8)
+ %r2x64to16x8 = call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv2_l(<2 x i64> %v2i64)
+ %r8x16to4x32 = call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv8_s(<8 x i16> %v8i16)
+ %r4x32to8x16 = call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv4_i(<4 x i32> %v4i32)
+ %r8x16to2x64 = call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv8_s(<8 x i16> %v8i16)
+ %r2x64to8x16 = call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv2_l(<2 x i64> %v2i64)
+ %r4x32to2x64 = call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv4_i(<4 x i32> %v4i32)
+ %r2x64to4x32 = call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv2_l(<2 x i64> %v2i64)
+ ret void
+}
+
+define spir_kernel void @test_256bit() {
+entry:
+ %v16i16 = load <16 x i16>, ptr undef
+ %v8i32 = load <8 x i32>, ptr undef
+ %v4i64 = load <4 x i64>, ptr undef
+
+ %r16x16to8x32 = call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv16_s(<16 x i16> %v16i16)
+ %r8x32to16x16 = call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv8_i(<8 x i32> %v8i32)
+ %r16x16to4x64 = call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv16_s(<16 x i16> %v16i16)
+ %r4x64to16x16 = call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv4_l(<4 x i64> %v4i64)
+ %r8x32to4x64 = call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv8_i(<8 x i32> %v8i32)
+ %r4x64to8x32 = call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv4_l(<4 x i64> %v4i64)
+ ret void
+}
+
+define spir_kernel void @test_512bit() {
+entry:
+ %v16i32 = load <16 x i32>, ptr undef
+ %v8i64 = load <8 x i64>, ptr undef
+
+ %r16x32to8x64 = call spir_func <8 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong8Dv16_i(<16 x i32> %v16i32)
+ %r8x64to16x32 = call spir_func <16 x i32>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruint16Dv8_l(<8 x i64> %v8i64)
+ ret void
+}
+
+declare dso_local spir_func i16
@_Z43__spirv_SubgroupBitcastShuffleINTEL_RushortDv2_c(<2 x i8>)
+declare dso_local spir_func <2 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar2s(i16)
+
+declare dso_local spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2Dv4_c(<4 x i8>)
+declare dso_local spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4Dv2_s(<2 x i16>)
+declare dso_local spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv4_c(<4 x i8>)
+declare dso_local spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4i(i32)
+declare dso_local spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv2_s(<2 x i16>)
+declare dso_local spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2i(i32)
+
+declare dso_local spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv8_c(<8 x i8>)
+declare dso_local spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv4_s(<4 x i16>)
+declare dso_local spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv8_c(<8 x i8>)
+declare dso_local spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv2_i(<2 x i32>)
+declare dso_local spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv8_c(<8 x i8>)
+declare dso_local spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8l(i64)
+declare dso_local spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv4_s(<4 x i16>)
+declare dso_local spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv2_i(<2 x i32>)
+declare dso_local spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv4_s(<4 x i16>)
+declare dso_local spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4l(i64)
+declare dso_local spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv2_i(<2 x i32>)
+declare dso_local spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2l(i64)
+
+declare dso_local spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv16_c(<16 x i8>)
+declare dso_local spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv8_s(<8 x i16>)
+declare dso_local spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv16_c(<16 x i8>)
+declare dso_local spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv4_i(<4 x i32>)
+declare dso_local spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv16_c(<16 x i8>)
+declare dso_local spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv2_l(<2 x i64>)
+declare dso_local spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv8_s(<8 x i16>)
+declare dso_local spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv4_i(<4 x i32>)
+declare dso_local spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv8_s(<8 x i16>)
+declare dso_local spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv2_l(<2 x i64>)
+declare dso_local spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv4_i(<4 x i32>)
+declare dso_local spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv2_l(<2 x i64>)
+
+declare dso_local spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv16_s(<16 x i16>)
+declare dso_local spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv8_i(<8 x i32>)
+declare dso_local spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv16_s(<16 x i16>)
+declare dso_local spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv4_l(<4 x i64>)
+declare dso_local spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv8_i(<8 x i32>)
+declare dso_local spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv4_l(<4 x i64>)
+
+declare dso_local spir_func <8 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong8Dv16_i(<16 x i32>)
+declare dso_local spir_func <16 x i32>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruint16Dv8_l(<8 x i64>)
+
+!llvm.module.flags = !{!0}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
++++++ SPIRV-LLVM-Translator-23.1.2.tar.gz ->
SPIRV-LLVM-Translator-23.1.3.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/.github/workflows/check-in-tree-build.yml
new/SPIRV-LLVM-Translator-23.1.3/.github/workflows/check-in-tree-build.yml
--- old/SPIRV-LLVM-Translator-23.1.2/.github/workflows/check-in-tree-build.yml
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/.github/workflows/check-in-tree-build.yml
2026-10-29 16:45:41.000000000 +0100
@@ -52,6 +52,8 @@
env:
LLVM_VERSION: 23
SPIRV_TOOLS_INSTALL: ${{ github.workspace }}/spirv-tools-install
+ # Latest SPIRV-Tools release at the time of the LLVM 23 release.
+ SPIRV_TOOLS_TAG: v2026.3
jobs:
build_and_test_linux:
@@ -76,15 +78,26 @@
# Linux systems in GitHub Actions already have older versions of
clang
# pre-installed. Make sure to override these with the relevant
version.
sudo update-alternatives --install /usr/bin/clang clang
/usr/bin/clang-${{ env.LLVM_VERSION }} 1000
- - name: Restore SPIRV-Tools cache
- # The prebuild-spirv-tools workflow owns populating this cache.
- # The primary key never matches (no one saves it); restore-keys
- # pulls the most recent prebuild entry.
- uses: actions/cache/restore@v5
+ - name: Cache SPIRV-Tools ${{ env.SPIRV_TOOLS_TAG }}
+ id: spirv-tools-cache
+ uses: actions/cache@v5
with:
path: ${{ env.SPIRV_TOOLS_INSTALL }}
- key: spirv-tools-main-latest
- restore-keys: spirv-tools-main-
+ key: spirv-tools-${{ env.SPIRV_TOOLS_TAG }}
+ - name: Build and install SPIRV-Tools ${{ env.SPIRV_TOOLS_TAG }}
+ if: steps.spirv-tools-cache.outputs.cache-hit != 'true'
+ run: |
+ git clone --depth=1 --branch ${{ env.SPIRV_TOOLS_TAG }}
https://github.com/KhronosGroup/SPIRV-Tools SPIRV-Tools
+ python3 SPIRV-Tools/utils/git-sync-deps
+ cmake -S SPIRV-Tools -B SPIRV-Tools/build \
+ -DCMAKE_BUILD_TYPE=Release \
+ -DCMAKE_INSTALL_PREFIX=${{ env.SPIRV_TOOLS_INSTALL }} \
+ -DSPIRV_SKIP_TESTS=ON \
+ -G "Unix Makefiles"
+ make -C SPIRV-Tools/build install -j$(nproc)
+ - name: Check SPIRV-Tools version
+ run: |
+ ${{ env.SPIRV_TOOLS_INSTALL }}/bin/spirv-val --version | grep
"^SPIRV-Tools ${{ env.SPIRV_TOOLS_TAG }} "
- name: Checkout LLVM sources
uses: actions/checkout@v5
with:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/.github/workflows/check-out-of-tree-build.yml
new/SPIRV-LLVM-Translator-23.1.3/.github/workflows/check-out-of-tree-build.yml
---
old/SPIRV-LLVM-Translator-23.1.2/.github/workflows/check-out-of-tree-build.yml
2026-09-29 15:35:16.000000000 +0200
+++
new/SPIRV-LLVM-Translator-23.1.3/.github/workflows/check-out-of-tree-build.yml
2026-10-29 16:45:41.000000000 +0100
@@ -48,6 +48,8 @@
env:
LLVM_VERSION: 23
SPIRV_TOOLS_INSTALL: ${{ github.workspace }}/spirv-tools-install
+ # Latest SPIRV-Tools release at the time of the LLVM 23 release.
+ SPIRV_TOOLS_TAG: v2026.3
jobs:
build_and_test:
@@ -75,15 +77,26 @@
# Linux systems in GitHub Actions already have older versions of
clang
# pre-installed. Make sure to override these with the relevant
version.
sudo update-alternatives --install /usr/bin/clang clang
/usr/bin/clang-${{ env.LLVM_VERSION }} 1000
- - name: Restore SPIRV-Tools cache
- # The prebuild-spirv-tools workflow owns populating this cache.
- # The primary key never matches (no one saves it); restore-keys
- # pulls the most recent prebuild entry.
- uses: actions/cache/restore@v5
+ - name: Cache SPIRV-Tools ${{ env.SPIRV_TOOLS_TAG }}
+ id: spirv-tools-cache
+ uses: actions/cache@v5
with:
path: ${{ env.SPIRV_TOOLS_INSTALL }}
- key: spirv-tools-main-latest
- restore-keys: spirv-tools-main-
+ key: spirv-tools-${{ env.SPIRV_TOOLS_TAG }}
+ - name: Build and install SPIRV-Tools ${{ env.SPIRV_TOOLS_TAG }}
+ if: steps.spirv-tools-cache.outputs.cache-hit != 'true'
+ run: |
+ git clone --depth=1 --branch ${{ env.SPIRV_TOOLS_TAG }}
https://github.com/KhronosGroup/SPIRV-Tools SPIRV-Tools
+ python3 SPIRV-Tools/utils/git-sync-deps
+ cmake -S SPIRV-Tools -B SPIRV-Tools/build \
+ -DCMAKE_BUILD_TYPE=Release \
+ -DCMAKE_INSTALL_PREFIX=${{ env.SPIRV_TOOLS_INSTALL }} \
+ -DSPIRV_SKIP_TESTS=ON \
+ -G "Unix Makefiles"
+ make -C SPIRV-Tools/build install -j$(nproc)
+ - name: Check SPIRV-Tools version
+ run: |
+ ${{ env.SPIRV_TOOLS_INSTALL }}/bin/spirv-val --version | grep
"^SPIRV-Tools ${{ env.SPIRV_TOOLS_TAG }} "
- name: Checkout the translator sources
uses: actions/checkout@v5
with:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/.github/workflows/prebuild-spirv-tools.yml
new/SPIRV-LLVM-Translator-23.1.3/.github/workflows/prebuild-spirv-tools.yml
--- old/SPIRV-LLVM-Translator-23.1.2/.github/workflows/prebuild-spirv-tools.yml
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/.github/workflows/prebuild-spirv-tools.yml
1970-01-01 01:00:00.000000000 +0100
@@ -1,50 +0,0 @@
-# This workflow builds SPIRV-Tools from main once per day and caches the
-# install tree. The build- and test-workflows only restore from this cache
-# (via restore-keys prefix match), so this workflow owns the freshness of
-# the tools.
-#
-# workflow_dispatch is provided for manual refresh when a SPIRV-Tools fix
-# needs to be picked up before the next scheduled run, or to bootstrap the
-# cache on first deployment.
-name: Prebuild SPIRV-Tools
-
-on:
- schedule:
- - cron: 0 23 * * *
- workflow_dispatch:
-
-env:
- SPIRV_TOOLS_INSTALL: ${{ github.workspace }}/spirv-tools-install
-
-jobs:
- prebuild:
- name: Build and cache SPIRV-Tools main
- runs-on: ubuntu-24.04
- steps:
- - name: Get current date for SPIRV-Tools cache key
- id: date
- run: echo "date=$(date -u +%Y-%m-%d)" >> $GITHUB_OUTPUT
- - name: Check for existing cache entry
- id: spirv-tools-cache
- uses: actions/cache/restore@v5
- with:
- path: ${{ env.SPIRV_TOOLS_INSTALL }}
- key: spirv-tools-main-${{ steps.date.outputs.date }}
- lookup-only: true
- - name: Build and install SPIRV-Tools
- if: steps.spirv-tools-cache.outputs.cache-hit != 'true'
- run: |
- git clone --depth=1 https://github.com/KhronosGroup/SPIRV-Tools
SPIRV-Tools
- python3 SPIRV-Tools/utils/git-sync-deps
- cmake -S SPIRV-Tools -B SPIRV-Tools/build \
- -DCMAKE_BUILD_TYPE=Release \
- -DCMAKE_INSTALL_PREFIX=${{ env.SPIRV_TOOLS_INSTALL }} \
- -DSPIRV_SKIP_TESTS=ON \
- -G "Unix Makefiles"
- make -C SPIRV-Tools/build install -j$(nproc)
- - name: Save SPIRV-Tools cache
- if: steps.spirv-tools-cache.outputs.cache-hit != 'true'
- uses: actions/cache/save@v5
- with:
- path: ${{ env.SPIRV_TOOLS_INSTALL }}
- key: spirv-tools-main-${{ steps.date.outputs.date }}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/include/LLVMSPIRVExtensions.inc
new/SPIRV-LLVM-Translator-23.1.3/include/LLVMSPIRVExtensions.inc
--- old/SPIRV-LLVM-Translator-23.1.2/include/LLVMSPIRVExtensions.inc
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/include/LLVMSPIRVExtensions.inc
2026-10-29 16:45:41.000000000 +0100
@@ -81,6 +81,7 @@
EXT(SPV_INTEL_maximum_registers)
EXT(SPV_INTEL_bindless_images)
EXT(SPV_INTEL_2d_block_io)
+EXT(SPV_INTEL_subgroup_bitcast_shuffle)
EXT(SPV_INTEL_subgroup_matrix_multiply_accumulate)
EXT(SPV_INTEL_subgroup_matrix_multiply_accumulate_float4)
EXT(SPV_INTEL_subgroup_matrix_multiply_accumulate_float8)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/SPIRVReader.cpp
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/SPIRVReader.cpp
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/SPIRVReader.cpp 2026-09-29
15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/SPIRVReader.cpp 2026-10-29
16:45:41.000000000 +0100
@@ -2810,6 +2810,7 @@
Args, BC->getName(), BB);
setCallingConv(Call);
setAttrByCalledFunc(Call);
+ applyFPFastMathModeDecorations(BV, Call);
return mapValue(BV, Call);
}
@@ -4006,7 +4007,7 @@
Func->addFnAttr(Attribute::NoUnwind);
if (isGroupOpCode(OC) || isGroupNonUniformOpcode(OC) ||
isIntelSubgroupOpCode(OC) || isSplitBarrierINTELOpCode(OC) ||
- OC == OpControlBarrier)
+ OC == OpSubgroupBitcastShuffleINTEL || OC == OpControlBarrier)
Func->addFnAttr(Attribute::Convergent);
}
CallInst *Call;
@@ -4188,6 +4189,7 @@
case internal::OpClampConvertFToSINTEL:
case internal::OpStochasticRoundFToFINTEL:
case internal::OpClampStochasticRoundFToSINTEL:
+ case OpSubgroupBitcastShuffleINTEL:
// Old opcodes, for backward compatibility.
case internal::OpClampConvertFToFINTEL:
case internal::OpClampStochasticRoundFToFINTEL:
@@ -4201,13 +4203,14 @@
}
bool IsRetSigned = true;
- switch (OC) {
+ switch (static_cast<size_t>(OC)) {
case OpConvertFToU:
case OpSatConvertSToU:
case OpUConvert:
case OpUDotKHR:
case OpUDotAccSatKHR:
case OpReadClockKHR:
+ case OpSubgroupBitcastShuffleINTEL:
IsRetSigned = false;
break;
case OpImageRead:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/SPIRVWriter.cpp
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/SPIRVWriter.cpp
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/SPIRVWriter.cpp 2026-09-29
15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/SPIRVWriter.cpp 2026-10-29
16:45:41.000000000 +0100
@@ -641,6 +641,16 @@
return 0;
}
+// Lower global_device and global_host address spaces that were added in
+// SYCL as part of SYCL_INTEL_usm_address_spaces extension to just global
+// address space if device doesn't support SPV_INTEL_usm_storage_classes
+// extension
+bool LLVMToSPIRVBase::shouldLowerUSMAddrSpace(unsigned AddrSpc) const {
+ return !BM->isAllowedToUseExtension(
+ ExtensionID::SPV_INTEL_usm_storage_classes) &&
+ (AddrSpc == SPIRAS_GlobalDevice || AddrSpc == SPIRAS_GlobalHost);
+}
+
SPIRVType *LLVMToSPIRVBase::transPointerType(Type *ET, unsigned AddrSpc) {
Type *T = PointerType::get(ET->getContext(), AddrSpc);
if (ET->isFunctionTy() &&
@@ -656,15 +666,8 @@
// A pointer to image or pipe type in LLVM is translated to a SPIRV
// (non-pointer) image or pipe type.
auto *ST = dyn_cast<StructType>(ET);
- // Lower global_device and global_host address spaces that were added in
- // SYCL as part of SYCL_INTEL_usm_address_spaces extension to just global
- // address space if device doesn't support SPV_INTEL_usm_storage_classes
- // extension
- if (!BM->isAllowedToUseExtension(
- ExtensionID::SPV_INTEL_usm_storage_classes) &&
- ((AddrSpc == SPIRAS_GlobalDevice) || (AddrSpc == SPIRAS_GlobalHost))) {
+ if (shouldLowerUSMAddrSpace(AddrSpc))
return transPointerType(ET, SPIRAS_Global);
- }
// Lower function pointer address space to private if
// spirv-emit-function-ptr-addr-space is not passed
if (AddrSpc == SPIRAS_CodeSectionINTEL &&
@@ -766,6 +769,8 @@
return Loc->second;
SPIRVType *TranslatedTy = nullptr;
+ if (shouldLowerUSMAddrSpace(AddrSpc))
+ return transPointerType(ET, SPIRAS_Global);
if (AddrSpc == SPIRAS_CodeSectionINTEL &&
!BM->shouldEmitFunctionPtrAddrSpace())
return transPointerType(ET, SPIRAS_Private);
@@ -3285,12 +3290,16 @@
if (auto *BVF = dyn_cast_or_null<FPMathOperator>(V)) {
auto Opcode = BVF->getOpcode();
+ bool IsSPV16Op = (Opcode == Instruction::FNeg ||
+ Opcode == Instruction::FCmp || BV->isExtInst()) &&
+ BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_6);
+ bool IsFC2Op =
+ BV->getOpCode() == OpFunctionCall &&
+ BM->isAllowedToUseExtension(ExtensionID::SPV_KHR_float_controls2);
if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
Opcode == Instruction::FMul || Opcode == Instruction::FDiv ||
Opcode == Instruction::FRem || BV->getOpCode() == OpFmaKHR ||
- ((Opcode == Instruction::FNeg || Opcode == Instruction::FCmp ||
- BV->isExtInst()) &&
- BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_6))) {
+ IsSPV16Op || IsFC2Op) {
bool AllowFloatControls2 =
BM->isAllowedToUseExtension(ExtensionID::SPV_KHR_float_controls2);
bool AllowIntelFpFastMathMode =
@@ -3391,9 +3400,13 @@
}
if (M != 0) {
BV->setFPFastMathMode(M);
- if (Opcode == Instruction::FNeg || Opcode == Instruction::FCmp ||
- BV->isExtInst())
+ if (IsSPV16Op)
BM->setMinSPIRVVersion(VersionNumber::SPIRV_1_6);
+ if (IsFC2Op) {
+ BM->setMinSPIRVVersion(VersionNumber::SPIRV_1_6);
+ BM->addCapability(CapabilityFloatControls2);
+ BM->addExtension(ExtensionID::SPV_KHR_float_controls2);
+ }
}
}
}
@@ -5053,8 +5066,8 @@
return nullptr;
}
uint64_t NumElements = static_cast<ConstantInt *>(Len)->getZExtValue();
- // A zero-sized memset is a no-op. Emitting OpCopyMemorySized with a Size
- // operand of 0 is invalid SPIR-V, so drop the intrinsic entirely.
+ // A zero-sized memset is a no-op. Emitting OpTypeArray with zero length
+ // is invalid SPIR-V, so drop the intrinsic entirely.
if (NumElements == 0)
return nullptr;
auto *AT = ArrayType::get(Val->getType(), NumElements);
@@ -5072,20 +5085,13 @@
std::vector<SPIRVValue *> Elts(TNumElts, transValue(Val, BB));
Init = BM->addCompositeConstant(CompositeTy, Elts);
}
- SPIRVType *VarTy = transPointerType(AT, SPIRAS_Private);
- SPIRVBasicBlock *EntryBB = BB->getParent()->getBasicBlock(0);
- SPIRVValue *Var = BM->addVariable(VarTy, nullptr, /*isConstant*/ false,
- spv::internal::LinkageTypeInternal, Init,
- "", StorageClassFunction, EntryBB);
std::vector<SPIRVWord> MemAccess = GetMemoryAccess(
MSI, BM->isAllowedToUseVersion(VersionNumber::SPIRV_1_4));
- if (!MemAccess.empty() && MemAccess[0] == MemoryAccessAlignedMask)
- Var->setAlignment(MemAccess[1]);
- SPIRVType *SourceTy = transPointerType(Val->getType(), SPIRAS_Private);
- SPIRVValue *Source = BM->addUnaryInst(OpBitcast, SourceTy, Var, BB);
SPIRVValue *Target = transValue(MSI->getRawDest(), BB);
- return BM->addCopyMemorySizedInst(Target, Source, CompositeTy->getLength(),
- MemAccess, BB);
+ SPIRVType *StorePtrTy = transPointerType(
+ CompositeTy, MSI->getRawDest()->getType()->getPointerAddressSpace());
+ SPIRVValue *StorePtr = BM->addUnaryInst(OpBitcast, StorePtrTy, Target, BB);
+ return BM->addStoreInst(StorePtr, Init, MemAccess, BB);
} break;
case Intrinsic::memcpy:
// A zero-sized memcpy is a no-op. Emitting OpCopyMemorySized with a Size
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/SPIRVWriter.h
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/SPIRVWriter.h
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/SPIRVWriter.h 2026-09-29
15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/SPIRVWriter.h 2026-10-29
16:45:41.000000000 +0100
@@ -165,6 +165,7 @@
bool CreateForward = true,
FuncTransMode FuncTrans = FuncTransMode::Decl);
void transGlobalIOPipeStorage(GlobalVariable *V, MDNode *IO);
+ bool shouldLowerUSMAddrSpace(unsigned AddrSpace) const;
static SPIRVInstruction *applyRoundingModeConstraint(Value *V,
SPIRVInstruction *I);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVEntry.h
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVEntry.h
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVEntry.h
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVEntry.h
2026-10-29 16:45:41.000000000 +0100
@@ -945,6 +945,8 @@
case CapabilityVectorComputeINTEL:
case CapabilityVectorAnyINTEL:
return ExtensionID::SPV_INTEL_vector_compute;
+ case CapabilitySubgroupBitcastShuffleINTEL:
+ return ExtensionID::SPV_INTEL_subgroup_bitcast_shuffle;
case internal::CapabilitySubgroupRequirementsINTEL:
return ExtensionID::SPV_INTEL_subgroup_requirements;
case CapabilityFPFastMathModeINTEL:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVInstruction.h
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVInstruction.h
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVInstruction.h
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVInstruction.h
2026-10-29 16:45:41.000000000 +0100
@@ -4856,6 +4856,20 @@
_SPIRV_OP_FTOF(ClampStochasticRoundFToF, true, 5, true)
#undef _SPIRV_OP_FTOF
+class SPIRVSubgroupBitcastShuffleINTELInst : public SPIRVInstTemplateBase {
+public:
+ std::optional<ExtensionID> getRequiredExtension() const override {
+ return ExtensionID::SPV_INTEL_subgroup_bitcast_shuffle;
+ }
+ SPIRVCapVec getRequiredCapability() const override {
+ return getVec(CapabilitySubgroupBitcastShuffleINTEL);
+ }
+};
+
+typedef SPIRVInstTemplate<SPIRVSubgroupBitcastShuffleINTELInst,
+ OpSubgroupBitcastShuffleINTEL, true, 4>
+ SPIRVSubgroupBitcastShuffleINTEL;
+
class SPIRVFPConversionFtoSINTELInstBase : public SPIRVInstTemplateBase {
public:
SPIRVCapVec getRequiredCapability() const override {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
2026-10-29 16:45:41.000000000 +0100
@@ -565,6 +565,7 @@
add(CapabilityDemoteToHelperInvocation, "DemoteToHelperInvocation");
add(CapabilityDemoteToHelperInvocationEXT, "DemoteToHelperInvocationEXT");
add(CapabilityBindlessTextureNV, "BindlessTextureNV");
+ add(CapabilitySubgroupBitcastShuffleINTEL, "SubgroupBitcastShuffleINTEL");
add(CapabilitySubgroupShuffleINTEL, "SubgroupShuffleINTEL");
add(CapabilitySubgroupBufferBlockIOINTEL, "SubgroupBufferBlockIOINTEL");
add(CapabilitySubgroupBufferPrefetchINTEL, "SubgroupBufferPrefetchINTEL");
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
--- old/SPIRV-LLVM-Translator-23.1.2/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
2026-10-29 16:45:41.000000000 +0100
@@ -578,6 +578,7 @@
_SPIRV_OP(ControlBarrierArriveINTEL, 6142)
_SPIRV_OP(ControlBarrierWaitINTEL, 6143)
_SPIRV_OP(ArithmeticFenceEXT, 6145)
+_SPIRV_OP(SubgroupBitcastShuffleINTEL, 6208)
_SPIRV_OP(SubgroupBlockPrefetchINTEL, 6221)
_SPIRV_OP(Subgroup2DBlockLoadINTEL, 6231)
_SPIRV_OP(Subgroup2DBlockLoadTransformINTEL, 6232)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/SPIRV-LLVM-Translator-23.1.2/spirv-headers-tag.conf
new/SPIRV-LLVM-Translator-23.1.3/spirv-headers-tag.conf
--- old/SPIRV-LLVM-Translator-23.1.2/spirv-headers-tag.conf 2026-09-29
15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/spirv-headers-tag.conf 2026-10-29
16:45:41.000000000 +0100
@@ -1 +1 @@
-575b6512579ebde466ed3dfc04e413439d14d95d
+cb42dec3830d3ac67fa449ecdc0c0f73d5e74498
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
new/SPIRV-LLVM-Translator-23.1.3/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
---
old/SPIRV-LLVM-Translator-23.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-23.1.3/test/extensions/INTEL/SPV_INTEL_subgroup_bitcast_shuffle/bitcast_shuffle.ll
2026-10-29 16:45:41.000000000 +0100
@@ -0,0 +1,276 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_subgroup_bitcast_shuffle -o
%t.spv
+; RUN: llvm-spirv %t.spv --to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; RUN: not llvm-spirv %t.bc 2>&1 -o %t.err.spv | FileCheck %s
--check-prefix=CHECK-ERROR
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V
extension:
+; CHECK-ERROR-NEXT: SPV_INTEL_subgroup_bitcast_shuffle
+
+; CHECK-SPIRV-DAG: Capability SubgroupBitcastShuffleINTEL
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_subgroup_bitcast_shuffle"
+
+; CHECK-SPIRV-DAG: TypeInt [[#TI8:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#TI16:]] 16 0
+; CHECK-SPIRV-DAG: TypeInt [[#TI32:]] 32 0
+; CHECK-SPIRV-DAG: TypeInt [[#TI64:]] 64 0
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I8:]] [[#TI8]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I8:]] [[#TI8]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I8:]] [[#TI8]] 8
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I16:]] [[#TI16]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I16:]] [[#TI16]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I32:]] [[#TI32]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV16I8:]] [[#TI8]] 16
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I16:]] [[#TI16]] 8
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I32:]] [[#TI32]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV2I64:]] [[#TI64]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#TV16I16:]] [[#TI16]] 16
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I32:]] [[#TI32]] 8
+; CHECK-SPIRV-DAG: TypeVector [[#TV4I64:]] [[#TI64]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#TV16I32:]] [[#TI32]] 16
+; CHECK-SPIRV-DAG: TypeVector [[#TV8I64:]] [[#TI64]] 8
+
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TI64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I8]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV2I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I16]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV4I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I32]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV8I64]]
+; CHECK-SPIRV: SubgroupBitcastShuffleINTEL [[#TV16I32]]
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_16bit()
+; CHECK-LLVM: call spir_func i16
@_Z43__spirv_SubgroupBitcastShuffleINTEL_RushortDv2_c(<2 x i8>
+; CHECK-LLVM: call spir_func <2 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar2s(i16
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_32bit()
+; CHECK-LLVM: call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2Dv4_c(<4 x i8>
+; CHECK-LLVM: call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4Dv2_s(<2 x i16>
+; CHECK-LLVM: call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv4_c(<4 x i8>
+; CHECK-LLVM: call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4i(i32
+; CHECK-LLVM: call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv2_s(<2 x i16>
+; CHECK-LLVM: call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2i(i32
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_64bit()
+; CHECK-LLVM: call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv8_c(<8 x i8>
+; CHECK-LLVM: call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv4_s(<4 x i16>
+; CHECK-LLVM: call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv8_c(<8 x i8>
+; CHECK-LLVM: call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv2_i(<2 x i32>
+; CHECK-LLVM: call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv8_c(<8 x i8>
+; CHECK-LLVM: call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8l(i64
+; CHECK-LLVM: call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv4_s(<4 x i16>
+; CHECK-LLVM: call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv2_i(<2 x i32>
+; CHECK-LLVM: call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv4_s(<4 x i16>
+; CHECK-LLVM: call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4l(i64
+; CHECK-LLVM: call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv2_i(<2 x i32>
+; CHECK-LLVM: call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2l(i64
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_128bit()
+; CHECK-LLVM: call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv16_c(<16 x i8>
+; CHECK-LLVM: call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv8_s(<8 x i16>
+; CHECK-LLVM: call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv16_c(<16 x i8>
+; CHECK-LLVM: call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv4_i(<4 x i32>
+; CHECK-LLVM: call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv16_c(<16 x i8>
+; CHECK-LLVM: call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv2_l(<2 x i64>
+; CHECK-LLVM: call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv8_s(<8 x i16>
+; CHECK-LLVM: call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv4_i(<4 x i32>
+; CHECK-LLVM: call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv8_s(<8 x i16>
+; CHECK-LLVM: call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv2_l(<2 x i64>
+; CHECK-LLVM: call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv4_i(<4 x i32>
+; CHECK-LLVM: call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv2_l(<2 x i64>
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_256bit()
+; CHECK-LLVM: call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv16_s(<16 x i16>
+; CHECK-LLVM: call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv8_i(<8 x i32>
+; CHECK-LLVM: call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv16_s(<16 x i16>
+; CHECK-LLVM: call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv4_l(<4 x i64>
+; CHECK-LLVM: call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv8_i(<8 x i32>
+; CHECK-LLVM: call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv4_l(<4 x i64>
+
+; CHECK-LLVM-LABEL: define spir_kernel void @test_512bit()
+; CHECK-LLVM: call spir_func <8 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong8Dv16_i(<16 x i32>
+; CHECK-LLVM: call spir_func <16 x i32>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruint16Dv8_l(<8 x i64>
+
+target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir"
+
+define spir_kernel void @test_16bit() {
+entry:
+ %v2i8 = load <2 x i8>, ptr undef
+ %s16 = load i16, ptr undef
+
+ %r2x8to16 = call spir_func i16
@_Z43__spirv_SubgroupBitcastShuffleINTEL_RushortDv2_c(<2 x i8> %v2i8)
+ %r16to2x8 = call spir_func <2 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar2s(i16 %s16)
+ ret void
+}
+
+define spir_kernel void @test_32bit() {
+entry:
+ %v4i8 = load <4 x i8>, ptr undef
+ %v2i16 = load <2 x i16>, ptr undef
+ %s32 = load i32, ptr undef
+
+ %r4x8to2x16 = call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2Dv4_c(<4 x i8> %v4i8)
+ %r2x16to4x8 = call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4Dv2_s(<2 x i16> %v2i16)
+ %r4x8to32 = call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv4_c(<4 x i8> %v4i8)
+ %r32to4x8 = call spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4i(i32 %s32)
+ %r2x16to32 = call spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv2_s(<2 x i16> %v2i16)
+ %r32to2x16 = call spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2i(i32 %s32)
+ ret void
+}
+
+define spir_kernel void @test_64bit() {
+entry:
+ %v8i8 = load <8 x i8>, ptr undef
+ %v4i16 = load <4 x i16>, ptr undef
+ %v2i32 = load <2 x i32>, ptr undef
+ %s64 = load i64, ptr undef
+
+ %r8x8to4x16 = call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv8_c(<8 x i8> %v8i8)
+ %r4x16to8x8 = call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv4_s(<4 x i16> %v4i16)
+ %r8x8to2x32 = call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv8_c(<8 x i8> %v8i8)
+ %r2x32to8x8 = call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv2_i(<2 x i32> %v2i32)
+ %r8x8to64 = call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv8_c(<8 x i8> %v8i8)
+ %r64to8x8 = call spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8l(i64 %s64)
+ %r4x16to2x32 = call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv4_s(<4 x i16> %v4i16)
+ %r2x32to4x16 = call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv2_i(<2 x i32> %v2i32)
+ %r4x16to64 = call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv4_s(<4 x i16> %v4i16)
+ %r64to4x16 = call spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4l(i64 %s64)
+ %r2x32to64 = call spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv2_i(<2 x i32> %v2i32)
+ %r64to2x32 = call spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2l(i64 %s64)
+ ret void
+}
+
+define spir_kernel void @test_128bit() {
+entry:
+ %v16i8 = load <16 x i8>, ptr undef
+ %v8i16 = load <8 x i16>, ptr undef
+ %v4i32 = load <4 x i32>, ptr undef
+ %v2i64 = load <2 x i64>, ptr undef
+
+ %r16x8to8x16 = call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv16_c(<16 x i8> %v16i8)
+ %r8x16to16x8 = call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv8_s(<8 x i16> %v8i16)
+ %r16x8to4x32 = call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv16_c(<16 x i8> %v16i8)
+ %r4x32to16x8 = call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv4_i(<4 x i32> %v4i32)
+ %r16x8to2x64 = call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv16_c(<16 x i8> %v16i8)
+ %r2x64to16x8 = call spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv2_l(<2 x i64> %v2i64)
+ %r8x16to4x32 = call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv8_s(<8 x i16> %v8i16)
+ %r4x32to8x16 = call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv4_i(<4 x i32> %v4i32)
+ %r8x16to2x64 = call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv8_s(<8 x i16> %v8i16)
+ %r2x64to8x16 = call spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv2_l(<2 x i64> %v2i64)
+ %r4x32to2x64 = call spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv4_i(<4 x i32> %v4i32)
+ %r2x64to4x32 = call spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv2_l(<2 x i64> %v2i64)
+ ret void
+}
+
+define spir_kernel void @test_256bit() {
+entry:
+ %v16i16 = load <16 x i16>, ptr undef
+ %v8i32 = load <8 x i32>, ptr undef
+ %v4i64 = load <4 x i64>, ptr undef
+
+ %r16x16to8x32 = call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv16_s(<16 x i16> %v16i16)
+ %r8x32to16x16 = call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv8_i(<8 x i32> %v8i32)
+ %r16x16to4x64 = call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv16_s(<16 x i16> %v16i16)
+ %r4x64to16x16 = call spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv4_l(<4 x i64> %v4i64)
+ %r8x32to4x64 = call spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv8_i(<8 x i32> %v8i32)
+ %r4x64to8x32 = call spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv4_l(<4 x i64> %v4i64)
+ ret void
+}
+
+define spir_kernel void @test_512bit() {
+entry:
+ %v16i32 = load <16 x i32>, ptr undef
+ %v8i64 = load <8 x i64>, ptr undef
+
+ %r16x32to8x64 = call spir_func <8 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong8Dv16_i(<16 x i32> %v16i32)
+ %r8x64to16x32 = call spir_func <16 x i32>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruint16Dv8_l(<8 x i64> %v8i64)
+ ret void
+}
+
+declare dso_local spir_func i16
@_Z43__spirv_SubgroupBitcastShuffleINTEL_RushortDv2_c(<2 x i8>)
+declare dso_local spir_func <2 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar2s(i16)
+
+declare dso_local spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2Dv4_c(<4 x i8>)
+declare dso_local spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4Dv2_s(<2 x i16>)
+declare dso_local spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv4_c(<4 x i8>)
+declare dso_local spir_func <4 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar4i(i32)
+declare dso_local spir_func i32
@_Z41__spirv_SubgroupBitcastShuffleINTEL_RuintDv2_s(<2 x i16>)
+declare dso_local spir_func <2 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort2i(i32)
+
+declare dso_local spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv8_c(<8 x i8>)
+declare dso_local spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv4_s(<4 x i16>)
+declare dso_local spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv8_c(<8 x i8>)
+declare dso_local spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8Dv2_i(<2 x i32>)
+declare dso_local spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv8_c(<8 x i8>)
+declare dso_local spir_func <8 x i8>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruchar8l(i64)
+declare dso_local spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2Dv4_s(<4 x i16>)
+declare dso_local spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4Dv2_i(<2 x i32>)
+declare dso_local spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv4_s(<4 x i16>)
+declare dso_local spir_func <4 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort4l(i64)
+declare dso_local spir_func i64
@_Z42__spirv_SubgroupBitcastShuffleINTEL_RulongDv2_i(<2 x i32>)
+declare dso_local spir_func <2 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint2l(i64)
+
+declare dso_local spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv16_c(<16 x i8>)
+declare dso_local spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv8_s(<8 x i16>)
+declare dso_local spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv16_c(<16 x i8>)
+declare dso_local spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv4_i(<4 x i32>)
+declare dso_local spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv16_c(<16 x i8>)
+declare dso_local spir_func <16 x i8>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Ruchar16Dv2_l(<2 x i64>)
+declare dso_local spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv8_s(<8 x i16>)
+declare dso_local spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv4_i(<4 x i32>)
+declare dso_local spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv8_s(<8 x i16>)
+declare dso_local spir_func <8 x i16>
@_Z44__spirv_SubgroupBitcastShuffleINTEL_Rushort8Dv2_l(<2 x i64>)
+declare dso_local spir_func <2 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong2Dv4_i(<4 x i32>)
+declare dso_local spir_func <4 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint4Dv2_l(<2 x i64>)
+
+declare dso_local spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv16_s(<16 x i16>)
+declare dso_local spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv8_i(<8 x i32>)
+declare dso_local spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv16_s(<16 x i16>)
+declare dso_local spir_func <16 x i16>
@_Z45__spirv_SubgroupBitcastShuffleINTEL_Rushort16Dv4_l(<4 x i64>)
+declare dso_local spir_func <4 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong4Dv8_i(<8 x i32>)
+declare dso_local spir_func <8 x i32>
@_Z42__spirv_SubgroupBitcastShuffleINTEL_Ruint8Dv4_l(<4 x i64>)
+
+declare dso_local spir_func <8 x i64>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Rulong8Dv16_i(<16 x i32>)
+declare dso_local spir_func <16 x i32>
@_Z43__spirv_SubgroupBitcastShuffleINTEL_Ruint16Dv8_l(<8 x i64>)
+
+!llvm.module.flags = !{!0}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/extensions/KHR/SPV_KHR_float_controls2/fp-fast-math-mode-function-call.ll
new/SPIRV-LLVM-Translator-23.1.3/test/extensions/KHR/SPV_KHR_float_controls2/fp-fast-math-mode-function-call.ll
---
old/SPIRV-LLVM-Translator-23.1.2/test/extensions/KHR/SPV_KHR_float_controls2/fp-fast-math-mode-function-call.ll
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-23.1.3/test/extensions/KHR/SPV_KHR_float_controls2/fp-fast-math-mode-function-call.ll
2026-10-29 16:45:41.000000000 +0100
@@ -0,0 +1,48 @@
+; Verify that FPFastMathMode decorations are emitted for OpFunctionCall when
+; SPV_KHR_float_controls2 is enabled. Also verify that non-core instructions
+; (e.g. OpGroupFMulKHR from SPV_KHR_uniform_group_instructions) do NOT get a
+; spurious FPFastMathMode decoration. SPV_KHR_float_controls2 extends
+; FPFastMathMode to all *core* instructions, but not to extension-defined ones.
+
+; Without FC2: no decoration on call.
+; RUN: llvm-spirv -spirv-text %s --spirv-max-version=1.5
--spirv-ext=+SPV_KHR_uniform_group_instructions -o - | FileCheck %s
--check-prefix=NO-DECO
+; RUN: llvm-spirv -spirv-text %s
--spirv-ext=+SPV_KHR_uniform_group_instructions -o - | FileCheck %s
--check-prefix=NO-DECO
+
+; With FC2: decoration emitted on OpFunctionCall, not on extension
instructions.
+; RUN: llvm-spirv -spirv-text %s
--spirv-ext=+SPV_KHR_float_controls2,+SPV_KHR_uniform_group_instructions -o - |
FileCheck %s --check-prefix=SPIRV
+
+; Roundtrip with FC2.
+; RUN: llvm-spirv %s
--spirv-ext=+SPV_KHR_float_controls2,+SPV_KHR_uniform_group_instructions -o
%t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis | FileCheck %s --check-prefix=IR
+
+target triple = "spirv-unknown-unknown"
+
+define internal spir_func float @helper(float %x) {
+ %r = fmul float %x, %x
+ ret float %r
+}
+
+declare spir_func float @_Z20__spirv_GroupFMulKHRjjf(i32, i32, float)
+
+; NO-DECO-NOT: FPFastMathMode
+
+; SPIRV-DAG: FunctionCall [[#]] [[#CALL:]]
+; SPIRV-DAG: GroupFMulKHR [[#]] [[#GFMUL:]]
+; SPIRV-DAG: Decorate [[#CALL]] FPFastMathMode 458767
+
+; OpGroupFMulKHR is defined by SPV_KHR_uniform_group_instructions, not core.
+; It should NOT get FPFastMathMode because FC2 only covers core instructions.
+; SPIRV-NOT: Decorate [[#GFMUL]] FPFastMathMode
+
+define spir_kernel void @test(ptr addrspace(1) %out, float %a) {
+entry:
+ ; IR: %call_fast = call reassoc nnan ninf nsz arcp contract spir_func float
@helper(float %a)
+ %call_fast = call fast spir_func float @helper(float %a)
+ store float %call_fast, ptr addrspace(1) %out, align 4
+
+ %gfmul_fast = call fast spir_func float @_Z20__spirv_GroupFMulKHRjjf(i32 2,
i32 0, float %a)
+ store float %gfmul_fast, ptr addrspace(1) %out, align 4
+
+ ret void
+}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-align.ll
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-align.ll
--- old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-align.ll
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-align.ll
2026-10-29 16:45:41.000000000 +0100
@@ -16,16 +16,18 @@
%r.sroa.0 = alloca [2 x i64], i32 1, align 16
%r.sroa.0.0.r.ascast.sroa_cast1 = addrspacecast ptr %r.sroa.0 to ptr
addrspace(4)
-; CHECK-SPIRV: Decorate [[#]] Alignment 16
-; CHECK-SPIRV: Decorate [[#SrcVar:]] Alignment [[#SrcAlignment:]]
-; CHECK-SPIRV: Variable [[#]] [[#SrcVar]] 7
-; CHECK-SPIRV: Bitcast [[#]] [[#]] [[#]]
-; CHECK-SPIRV: Bitcast [[#]] [[#Src:]] [[#SrcVar]]
-; CHECK-SPIRV: CopyMemorySized [[#]] [[#Src]] [[#]] 2 [[#SrcAlignment]]
-; CHECK-LLVM: %{{[0-9]+}} = alloca [16 x i8], align [[#SrcAlignment:]]
-; CHECK-LLVM: store [16 x i8] zeroinitializer, ptr %{{[0-9]+}}, align 1
-; CHECK-LLVM: [[SrcOp:%[0-9]+]] = bitcast ptr %{{[0-9]+}} to ptr
-; CHECK-LLVM: call void @llvm.memcpy.p4.p0.i64(ptr addrspace(4) align 16
%{{[0-9]+}}, ptr align [[#SrcAlignment]] [[SrcOp]], i64 16, i1 false)
+; CHECK-SPIRV: Decorate [[#Var:]] Alignment 16
+; CHECK-SPIRV: ConstantNull [[#]] [[#Init:]]
+; CHECK-SPIRV: Variable [[#]] [[#Var]]
+; CHECK-SPIRV: PtrCastToGeneric [[#]] [[#Generic:]] [[#Var]]
+; CHECK-SPIRV: Bitcast [[#]] [[#BytePtr:]] [[#Generic]]
+; CHECK-SPIRV: Bitcast [[#]] [[#StorePtr:]] [[#BytePtr]]
+; CHECK-SPIRV: Store [[#StorePtr]] [[#Init]] 2 16
+; CHECK-LLVM: %[[X:.+]] = alloca [2 x i64], align 16
+; CHECK-LLVM: %[[Generic:.+]] = addrspacecast ptr %[[X]] to ptr addrspace(4)
+; CHECK-LLVM: %[[#BytePtr:]] = bitcast ptr addrspace(4) %[[Generic]] to ptr
addrspace(4)
+; CHECK-LLVM: %[[#ArrayPtr:]] = bitcast ptr addrspace(4) %[[#BytePtr]] to ptr
addrspace(4)
+; CHECK-LLVM: store [16 x i8] zeroinitializer, ptr addrspace(4)
%[[#ArrayPtr]], align 16
call void @llvm.memset.p4.i64(ptr addrspace(4) align 16
%r.sroa.0.0.r.ascast.sroa_cast1, i8 0, i64 16, i1 false)
ret void
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-long-composite.ll
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-long-composite.ll
---
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-long-composite.ll
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-long-composite.ll
2026-10-29 16:45:41.000000000 +0100
@@ -0,0 +1,40 @@
+; Test memset with non-zero fill, and a constant length too large for
+; a single OpConstantComposite that exceeds maximum WordCount.
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: not llvm-spirv %t.bc -o %t.spv 2>&1 | FileCheck %s
--check-prefix=CHECK-ERROR
+
+; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_long_composites %t.bc -o %t.spv
+; RUN: llvm-spirv %t.spv --to-text -o - | FileCheck %s
--check-prefix=CHECK-SPIRV --implicit-check-not=Variable
--implicit-check-not=CopyMemorySized
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis | FileCheck %s
--check-prefix=CHECK-LLVM
+; TODO: currently spirv-val falsely rejects OpConstantCompositeContinuedINTEL
in the module.
+; Re-enable spirv-val once it's fixed. Tracker:
https://github.com/KhronosGroup/SPIRV-Tools/issues/6954
+; RUNx: spirv-val %t.spv
+
+; CHECK-ERROR: InvalidWordCount: Can't encode instruction with word count
greater than 65535:
+; CHECK-ERROR-NEXT: Id: [[#]], OpCode: ConstantComposite
+
+; CHECK-SPIRV: Capability LongCompositesINTEL
+; CHECK-SPIRV: Extension "SPV_INTEL_long_composites"
+; CHECK-SPIRV: TypeInt [[#ByteTy:]] 8 0
+; CHECK-SPIRV: Constant [[#]] [[#Length:]] 70000
+; CHECK-SPIRV: Constant [[#ByteTy]] [[#Byte:]] 3
+; CHECK-SPIRV: TypeArray [[#ArrayTy:]] [[#ByteTy]] [[#Length]]
+; CHECK-SPIRV: TypePointer [[#StorePtrTy:]] 5 [[#ArrayTy]]
+; CHECK-SPIRV: 65535 ConstantComposite [[#ArrayTy]] [[#Init:]]
[[#Byte]]{{( [0-9]+)+ ?$}}
+; CHECK-SPIRV-NEXT: 4469 ConstantCompositeContinuedINTEL [[#Byte]]{{( [0-9]+)+
?$}}
+; CHECK-SPIRV: Bitcast [[#StorePtrTy]] [[#ArrayPtr:]] [[#]]
+; CHECK-SPIRV: Store [[#ArrayPtr]] [[#Init]] 2 4
+
+; CHECK-LLVM: store [70000 x i8] c"{{(\\03)+}}", ptr addrspace(1) %[[#]],
align 4
+
+target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+define spir_kernel void @fill(ptr addrspace(1) %dst) {
+entry:
+ call void @llvm.memset.p1.i64(ptr addrspace(1) align 4 %dst, i8 3, i64
70000, i1 false)
+ ret void
+}
+
+declare void @llvm.memset.p1.i64(ptr addrspace(1) noalias writeonly, i8, i64,
i1 immarg)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-opaque.ll
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-opaque.ll
--- old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-opaque.ll
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-opaque.ll
2026-10-29 16:45:41.000000000 +0100
@@ -23,24 +23,26 @@
; CHECK-SPIRV: Constant {{[0-9]+}} [[Lenmemset0:[0-9]+]] 12
; CHECK-SPIRV: Constant {{[0-9]+}} [[Const21:[0-9]+]] 21
; CHECK-SPIRV: TypeArray [[Int8x4:[0-9]+]] [[Int8]] [[Lenmemset21]]
+; CHECK-SPIRV: TypePointer [[#Int8x4Ptr:]] 7 [[Int8x4]]
; CHECK-SPIRV-UNTYPED-PTR: TypeUntypedPointerKHR [[Int8Ptr:[0-9]+]] 8
; CHECK-SPIRV-TYPED-PTR: TypePointer [[Int8Ptr:[0-9]+]] 8 [[Int8]]
; CHECK-SPIRV: TypeArray [[Int8x12:[0-9]+]] [[Int8]] [[Lenmemset0]]
-; CHECK-SPIRV-TYPED-PTR: TypePointer [[Int8PtrConst:[0-9]+]] 7 [[Int8]]
-; CHECK-SPIRV-UNTYPED-PTR: TypeUntypedPointerKHR [[Int8PtrConst:[0-9]+]] 7
+; CHECK-SPIRV: TypePointer [[#Int8x12Ptr:]] 8 [[Int8x12]]
; CHECK-SPIRV: ConstantNull [[Int8x12]] [[Init:[0-9]+]]
; CHECK-SPIRV: 7 ConstantComposite [[Int8x4]] [[InitComp:[0-9]+]] [[Const21]]
[[Const21]] [[Const21]] [[Const21]]
; CHECK-SPIRV: ConstantFalse [[#]] [[#False:]]
-; CHECK-SPIRV: Variable {{[0-9]+}} [[Val:[0-9]+]] 7 [[Init]]
-; CHECK-SPIRV: Variable {{[0-9]+}} [[ValComp:[0-9]+]] 7 [[InitComp]]
-; CHECK-SPIRV: Bitcast [[Int8Ptr]] [[Target:[0-9]+]] {{[0-9]+}}
-; CHECK-SPIRV: Bitcast [[Int8PtrConst]] [[Source:[0-9]+]] [[Val]]
-; CHECK-SPIRV: CopyMemorySized [[Target]] [[Source]] [[Lenmemset0]] 2 4
+; CHECK-SPIRV: FunctionParameter [[#]] [[#AggResult:]]
+; CHECK-SPIRV: Variable [[#Int8x4Ptr]] [[#X:]] 7
-; CHECK-SPIRV: Bitcast [[Int8PtrConst]] [[SourceComp:[0-9]+]] [[ValComp]]
-; CHECK-SPIRV: CopyMemorySized {{[0-9]+}} [[SourceComp]] [[Lenmemset21]] 2 4
+; CHECK-SPIRV: Bitcast [[Int8Ptr]] [[Target:[0-9]+]] [[#AggResult]]
+; CHECK-SPIRV: Bitcast [[#Int8x12Ptr]] [[#TargetArray:]] [[Target]]
+; CHECK-SPIRV: Store [[#TargetArray]] [[Init]] 2 4
+
+; CHECK-SPIRV: Bitcast [[#]] [[#XBytePtr:]] [[#X]]
+; CHECK-SPIRV: Bitcast [[#Int8x4Ptr]] [[#TargetComp:]] [[#XBytePtr]]
+; CHECK-SPIRV: Store [[#TargetComp]] [[InitComp]] 2 4
; CHECK-SPIRV: FunctionCall [[#]] [[#]] [[#NonConstMemset]] [[#]] [[#]] [[#]]
[[#False]]
@@ -74,18 +76,18 @@
%struct.S1 = type { i32, i32, i32 }
-; CHECK-LLVM-OPAQUE: %{{[0-9]+}} = alloca [12 x i8], align 4
-; CHECK-LLVM-OPAQUE: store [12 x i8] zeroinitializer, ptr %{{[0-9]+}}, align 1
-; CHECK-LLVM-OPAQUE: %{{[0-9]+}} = alloca [4 x i8], align 4
-; CHECK-LLVM-OPAQUE: store [4 x i8] c"\15\15\15\15", ptr %{{[0-9]+}}, align 1
-
; Function Attrs: nounwind
define spir_func void @_Z5foo11v(ptr addrspace(4) noalias captures(none)
sret(%struct.S1) %agg.result, i32 %s1, i64 %s2, i8 %v) #0 {
%x = alloca [4 x i8]
+; CHECK-LLVM-OPAQUE: %[[X:.+]] = alloca [4 x i8]
tail call void @llvm.memset.p4.i32(ptr addrspace(4) align 4 %agg.result, i8
0, i32 12, i1 false)
-; CHECK-LLVM-OPAQUE: call void @llvm.memcpy.p4.p0.i32(ptr addrspace(4) align 4
%{{[0-9]+}}, ptr align 4 %{{[0-9]+}}, i32 12, i1 false)
+; CHECK-LLVM-OPAQUE: %[[#DstBytePtr:]] = bitcast ptr addrspace(4) %agg.result
to ptr addrspace(4)
+; CHECK-LLVM-OPAQUE: %[[#DstArrayPtr:]] = bitcast ptr addrspace(4)
%[[#DstBytePtr]] to ptr addrspace(4)
+; CHECK-LLVM-OPAQUE: store [12 x i8] zeroinitializer, ptr addrspace(4)
%[[#DstArrayPtr]], align 4
tail call void @llvm.memset.p0.i32(ptr align 4 %x, i8 21, i32 4, i1 false)
-; CHECK-LLVM-OPAQUE: call void @llvm.memcpy.p0.p0.i32(ptr align 4 %{{[0-9]+}},
ptr align 4 %{{[0-9]+}}, i32 4, i1 false)
+; CHECK-LLVM-OPAQUE: %[[#XBytePtr:]] = bitcast ptr %[[X]] to ptr
+; CHECK-LLVM-OPAQUE: %[[#XArrayPtr:]] = bitcast ptr %[[#XBytePtr]] to ptr
+; CHECK-LLVM-OPAQUE: store [4 x i8] c"\15\15\15\15", ptr %[[#XArrayPtr]],
align 4
; non-const value
tail call void @llvm.memset.p0.i32(ptr align 4 %x, i8 %v, i32 3, i1 false)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-store.ll
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-store.ll
--- old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/memset-store.ll
1970-01-01 01:00:00.000000000 +0100
+++ new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/memset-store.ll
2026-10-29 16:45:41.000000000 +0100
@@ -0,0 +1,109 @@
+; Test that memset is lowered to a single OpStore of a composite constant,
+; with non-zero fill.
+; Also test the global_device & global_host address spaces are translated
+; correctly so that the target pointer matches the (bitcast) store pointer,
+; with and without SPV_INTEL_usm_storage_classes extension.
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -spirv-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
--implicit-check-not=Variable --implicit-check-not=CopyMemorySized
--implicit-check-not="Capability USMStorageClassesINTEL"
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis | FileCheck %s
--check-prefixes=CHECK-LLVM,CHECK-LLVM-GLOBAL
+
+; TODO: currently the Translator has a bug that it doesn't emit "OpExtension
SPV_INTEL_usm_storage_classes"
+; when the extension is enabled, therefore spirv-val will reject it. Re-enable
spirv-val once this bug is
+; fixed in the translator.
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_usm_storage_classes -o
%t.usm.spv
+; RUN: llvm-spirv %t.usm.spv --to-text -o - | FileCheck %s
--check-prefix=CHECK-SPIRV-USM
+; RUN: llvm-spirv -r %t.usm.spv -o - | llvm-dis | FileCheck %s
--check-prefixes=CHECK-LLVM,CHECK-LLVM-USM
+; RUNx: spirv-val %t.usm.spv
+
+; Without SPV_INTEL_usm_storage_classes both USM address spaces are lowered to
+; CrossWorkgroup (storage class 5), so all three kernels share one destination
+; pointer type, and fill_device and fill_host share one store pointer type.
+; CHECK-SPIRV: TypeInt [[#ByteTy:]] 8 0
+; CHECK-SPIRV: Constant [[#]] [[#Length:]] 3
+; CHECK-SPIRV: Constant [[#ByteTy]] [[#Byte:]] 42
+; CHECK-SPIRV: TypePointer [[#BytePtrTy:]] 5 [[#ByteTy]]
+; CHECK-SPIRV: TypeArray [[#ArrayTy:]] [[#ByteTy]] [[#Length]]
+; CHECK-SPIRV: TypePointer [[#StorePtrTy:]] 5 [[#ArrayTy]]
+; CHECK-SPIRV: TypeArray [[#UsmArrayTy:]] [[#ByteTy]] [[#]]
+; CHECK-SPIRV: TypePointer [[#UsmStorePtrTy:]] 5 [[#UsmArrayTy]]
+; CHECK-SPIRV: ConstantComposite [[#ArrayTy]] [[#Init:]] [[#Byte]] [[#Byte]]
[[#Byte]]
+; CHECK-SPIRV: ConstantNull [[#UsmArrayTy]] [[#DeviceInit:]]
+; CHECK-SPIRV: ConstantNull [[#UsmArrayTy]] [[#HostInit:]]
+
+; CHECK-SPIRV: FunctionParameter [[#BytePtrTy]] [[#Base:]]
+; CHECK-SPIRV: PtrAccessChain [[#BytePtrTy]] [[#OffsetPtr:]] [[#Base]] [[#]]
+; CHECK-SPIRV: Bitcast [[#StorePtrTy]] [[#ArrayPtr:]] [[#OffsetPtr]]
+; CHECK-SPIRV: Store [[#ArrayPtr]] [[#Init]] 3 1
+
+; CHECK-SPIRV: FunctionParameter [[#BytePtrTy]] [[#Device:]]
+; CHECK-SPIRV: Bitcast [[#UsmStorePtrTy]] [[#DeviceStorePtr:]] [[#Device]]
+; CHECK-SPIRV: Store [[#DeviceStorePtr]] [[#DeviceInit]] 2 4
+
+; CHECK-SPIRV: FunctionParameter [[#BytePtrTy]] [[#Host:]]
+; CHECK-SPIRV: Bitcast [[#UsmStorePtrTy]] [[#HostStorePtr:]] [[#Host]]
+; CHECK-SPIRV: Store [[#HostStorePtr]] [[#HostInit]] 2 4
+
+; CHECK-LLVM: %[[Dest:[a-zA-Z0-9.]+]] = getelementptr i8, ptr addrspace(1)
%base, i64 1
+; CHECK-LLVM: %[[#StorePtr:]] = bitcast ptr addrspace(1) %[[Dest]] to ptr
addrspace(1)
+; CHECK-LLVM: store volatile [3 x i8] c"***", ptr addrspace(1) %[[#StorePtr]],
align 1
+
+; The global_device and global_host destinations were lowered to
CrossWorkgroup,
+; so they come back as global (addrspace(1)) pointers.
+; CHECK-LLVM-GLOBAL: define spir_kernel void @fill_device(ptr addrspace(1)
%dst)
+; CHECK-LLVM-GLOBAL: %[[#DeviceStorePtr:]] = bitcast ptr addrspace(1) %dst to
ptr addrspace(1)
+; CHECK-LLVM-GLOBAL: store [8 x i8] zeroinitializer, ptr addrspace(1)
%[[#DeviceStorePtr]], align 4
+; CHECK-LLVM-GLOBAL: define spir_kernel void @fill_host(ptr addrspace(1) %dst)
+; CHECK-LLVM-GLOBAL: %[[#HostStorePtr:]] = bitcast ptr addrspace(1) %dst to
ptr addrspace(1)
+; CHECK-LLVM-GLOBAL: store [8 x i8] zeroinitializer, ptr addrspace(1)
%[[#HostStorePtr]], align 4
+
+; With SPV_INTEL_usm_storage_classes enabled each target pointer keeps its own
+; storage class, DeviceOnlyINTEL (5936) and HostOnlyINTEL (5937), and so does
+; its store pointer.
+; CHECK-SPIRV-USM: TypePointer [[#DeviceBytePtrTy:]] 5936 [[#]]
+; CHECK-SPIRV-USM: TypeArray [[#UsmArrayTyE:]] [[#]] [[#]]
+; CHECK-SPIRV-USM: TypePointer [[#DeviceStorePtrTy:]] 5936 [[#UsmArrayTyE]]
+; CHECK-SPIRV-USM: TypePointer [[#HostBytePtrTy:]] 5937 [[#]]
+; CHECK-SPIRV-USM: TypePointer [[#HostStorePtrTy:]] 5937 [[#UsmArrayTyE]]
+; CHECK-SPIRV-USM: FunctionParameter [[#DeviceBytePtrTy]] [[#DeviceE:]]
+; CHECK-SPIRV-USM: Bitcast [[#DeviceStorePtrTy]] [[#DeviceStorePtrE:]]
[[#DeviceE]]
+; CHECK-SPIRV-USM: Store [[#DeviceStorePtrE]] [[#]] 2 4
+; CHECK-SPIRV-USM: FunctionParameter [[#HostBytePtrTy]] [[#HostE:]]
+; CHECK-SPIRV-USM: Bitcast [[#HostStorePtrTy]] [[#HostStorePtrE:]] [[#HostE]]
+; CHECK-SPIRV-USM: Store [[#HostStorePtrE]] [[#]] 2 4
+
+; CHECK-LLVM-USM: define spir_kernel void @fill_device(ptr addrspace(5) %dst)
+; CHECK-LLVM-USM: %[[#DeviceStorePtrE:]] = bitcast ptr addrspace(5) %dst to
ptr addrspace(5)
+; CHECK-LLVM-USM: store [8 x i8] zeroinitializer, ptr addrspace(5)
%[[#DeviceStorePtrE]], align 4
+; CHECK-LLVM-USM: define spir_kernel void @fill_host(ptr addrspace(6) %dst)
+; CHECK-LLVM-USM: %[[#HostStorePtrE:]] = bitcast ptr addrspace(6) %dst to ptr
addrspace(6)
+; CHECK-LLVM-USM: store [8 x i8] zeroinitializer, ptr addrspace(6)
%[[#HostStorePtrE]], align 4
+
+target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+define spir_kernel void @fill(ptr addrspace(1) %base) {
+entry:
+ %dst = getelementptr i8, ptr addrspace(1) %base, i64 1
+ call void @llvm.memset.p1.i64(ptr addrspace(1) align 1 %dst, i8 42, i64 3,
i1 true)
+ ret void
+}
+
+define spir_kernel void @fill_device(ptr addrspace(5) %dst) {
+entry:
+ call void @llvm.memset.p5.i64(ptr addrspace(5) align 4 %dst, i8 0, i64 8, i1
false)
+ ret void
+}
+
+define spir_kernel void @fill_host(ptr addrspace(6) %dst) {
+entry:
+ call void @llvm.memset.p6.i64(ptr addrspace(6) align 4 %dst, i8 0, i64 8, i1
false)
+ ret void
+}
+
+declare void @llvm.memset.p1.i64(ptr addrspace(1), i8, i64, i1 immarg)
+declare void @llvm.memset.p5.i64(ptr addrspace(5), i8, i64, i1 immarg)
+declare void @llvm.memset.p6.i64(ptr addrspace(6), i8, i64, i1 immarg)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/zero-length-mem-intrinsics.ll
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/zero-length-mem-intrinsics.ll
---
old/SPIRV-LLVM-Translator-23.1.2/test/llvm-intrinsics/zero-length-mem-intrinsics.ll
2026-09-29 15:35:16.000000000 +0200
+++
new/SPIRV-LLVM-Translator-23.1.3/test/llvm-intrinsics/zero-length-mem-intrinsics.ll
2026-10-29 16:45:41.000000000 +0100
@@ -1,15 +1,16 @@
; Constant zero-sized memcpy/memmove/memset are no-ops. Emitting
-; OpCopyMemorySized with a Size operand of 0 is invalid SPIR-V, so the
+; OpCopyMemorySized or OpTypeArray with a Size operand of 0 is invalid SPIR-V,
so the
; translator must drop these intrinsics. A non-zero copy is unaffected.
-; RUN: llvm-spirv %s -spirv-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %s -spirv-text -o - | FileCheck %s
--check-prefix=CHECK-SPIRV --implicit-check-not=Store
; RUN: llvm-spirv %s -o %t.spv
; RUN: spirv-val %t.spv
target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
target triple = "spir-unknown-unknown"
-; A single CopyMemorySized is emitted, for the non-zero memcpy only.
+; A single CopyMemorySized is emitted, for the non-zero memcpy only, and the
+; dropped zero-sized memset leaves no Store behind.
; CHECK-SPIRV-COUNT-1: CopyMemorySized
define spir_func void @zero_memcpy(ptr %dst, ptr %src) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-23.1.2/test/transcoding/intrinsic_result_store.ll
new/SPIRV-LLVM-Translator-23.1.3/test/transcoding/intrinsic_result_store.ll
--- old/SPIRV-LLVM-Translator-23.1.2/test/transcoding/intrinsic_result_store.ll
2026-09-29 15:35:16.000000000 +0200
+++ new/SPIRV-LLVM-Translator-23.1.3/test/transcoding/intrinsic_result_store.ll
2026-10-29 16:45:41.000000000 +0100
@@ -10,18 +10,15 @@
target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir64-unknown-unknown"
-; CHECK-LLVM: %[[ZERO_INIT:[0-9]+]] = alloca [8 x i8], align 8
-; CHECK-LLVM: store [8 x i8] zeroinitializer, ptr %[[ZERO_INIT]], align 1
-
; Function Attrs: convergent noinline nounwind optnone
define spir_kernel void @test_memset(ptr addrspace(1) %data, i32 %input) #0
!kernel_arg_addr_space !1 !kernel_arg_access_qual !5 !kernel_arg_type !6
!kernel_arg_base_type !6 !kernel_arg_type_qual !7 {
entry:
-; CHECK-LLVM: %[[BITCAST_RES:[[:alnum:].]+]] = bitcast ptr addrspace(1)
%{{[[:alnum:].]+}} to ptr addrspace(1)
+; CHECK-LLVM: %[[B:.+]] = bitcast ptr addrspace(1) %data to ptr addrspace(1)
%ptr = bitcast ptr addrspace(1) %data to ptr addrspace(1)
-; CHECK-LLVM: %[[#ZERO_INIT_BITCAST:]] = bitcast ptr %[[ZERO_INIT]] to ptr
-; CHECK-LLVM: call void @llvm.memcpy.p1.p0.i64(ptr addrspace(1) align 8
%[[BITCAST_RES]], ptr align 8 %[[#ZERO_INIT_BITCAST]], i64 8, i1 false)
+; CHECK-LLVM: %[[#ArrayPtr:]] = bitcast ptr addrspace(1) %[[B]] to ptr
addrspace(1)
+; CHECK-LLVM: store [8 x i8] zeroinitializer, ptr addrspace(1) %[[#ArrayPtr]],
align 8
call void @llvm.memset.p1.i64(ptr addrspace(1) align 8 %ptr, i8 0, i64 8, i1
false)
-; CHECK-LLVM: store i8 0, ptr addrspace(1) %[[BITCAST_RES]]
+; CHECK-LLVM: store i8 0, ptr addrspace(1) %[[B]]
store i8 0, ptr addrspace(1) %ptr
ret void
}
