Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package cpupower for openSUSE:Factory
checked in at 2021-07-20 15:39:22
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/cpupower (Old)
and /work/SRC/openSUSE:Factory/.cpupower.new.2632 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpupower"
Tue Jul 20 15:39:22 2021 rev:51 rq:907255 version:5.14
Changes:
--------
--- /work/SRC/openSUSE:Factory/cpupower/cpupower.changes 2020-12-03
18:38:31.101731340 +0100
+++ /work/SRC/openSUSE:Factory/.cpupower.new.2632/cpupower.changes
2021-07-20 15:40:05.781540229 +0200
@@ -1,0 +2,10 @@
+Mon Jul 19 12:17:54 UTC 2021 - Thomas Renninger <tr...@suse.de>
+
+- Update (jsc#SLE-18392, jsc#SLE-18906, jsc#SLE-18393, jsc#SLE-18410):
+ * turbostat to 21.05.04
+ * intel speed select to 1.10
+ * cpupower to 5.14-rcX (kernel sources state)
+- Already upstream and included in the update:
+D intel-speed-select_remove_DATE_TIME.patch
+
+-------------------------------------------------------------------
Old:
----
cpupower-5.10.tar.bz2
intel-speed-select-1.6.tar.bz2
intel-speed-select_remove_DATE_TIME.patch
turbostat-20.09.30.tar.bz2
New:
----
cpupower-5.14.tar.bz2
intel-speed-select-1.10.tar.bz2
turbostat-21.05.04.tar.bz2
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ cpupower.spec ++++++
--- /var/tmp/diff_new_pack.BVtrJL/_old 2021-07-20 15:40:06.385541309 +0200
+++ /var/tmp/diff_new_pack.BVtrJL/_new 2021-07-20 15:40:06.385541309 +0200
@@ -1,7 +1,7 @@
#
# spec file for package cpupower
#
-# Copyright (c) 2020 SUSE LLC
+# Copyright (c) 2021 SUSE LLC
# Author: Thomas Renninger <tr...@suse.de>
#
# All modifications and additions to the file contributed by third parties
@@ -20,14 +20,14 @@
# Use this as version when things are in mainline kernel
%define version %(rpm -q --qf '%{VERSION}' kernel-source)
-%define tsversion 20.09.30
+%define tsversion 21.05.04
%define pbversion 17.05.11
-%define ssversion 1.6
+%define ssversion 1.10
Name: cpupower
# Use this as version when things are in mainline kernel
%define version %(rpm -q --qf '%VERSION' kernel-source)
-Version: 5.10
+Version: 5.14
Release: 0
Summary: Tools to determine and set CPU Power related Settings
License: GPL-2.0-only
@@ -52,9 +52,6 @@
# Fixes bsc#1048546:
Patch30: x86_perf_makefile_fix_asm_header.patch
-# intel-speed-select patches
-Patch50: intel-speed-select_remove_DATE_TIME.patch
-
BuildRequires: gettext-tools
BuildRequires: libcap-devel
BuildRequires: pciutils
@@ -104,11 +101,11 @@
%patch23 -p1
cd ../x86_energy_perf_policy-%{pbversion}
+%patch23 -p1
%patch30 -p1
cd ../intel-speed-select-%{ssversion}
cp %{SOURCE5} Makefile
-%patch50 -p1
%build
CONF="PACKAGE_BUGREPORT=https://bugs.opensuse.org mandir=%{_mandir}
libdir=%{_libdir} CPUFRQ_BENCH=true VERSION=%{version}"
@@ -117,7 +114,7 @@
%ifarch ix86 x86_64
cd ../turbostat-%{tsversion}
-export CFLAGS="%{optflags} -fcommon -I ."
+export CFLAGS="%{optflags} -fcommon -I ../turbostat-%{tsversion}/include"
make %{?_smp_mflags}
cd ../x86_energy_perf_policy-%{pbversion}
make %{?_smp_mflags}
++++++ amd_do_not_show_amount_of_boost_states_if_zero.patch ++++++
--- /var/tmp/diff_new_pack.BVtrJL/_old 2021-07-20 15:40:06.433541395 +0200
+++ /var/tmp/diff_new_pack.BVtrJL/_new 2021-07-20 15:40:06.433541395 +0200
@@ -4,7 +4,7 @@
--- a/utils/cpufreq-info.c
+++ b/utils/cpufreq-info.c
-@@ -191,7 +191,9 @@
+@@ -190,7 +190,9 @@
if (ret)
return ret;
++++++ cpupower-5.10.tar.bz2 -> cpupower-5.14.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/Makefile new/cpupower-5.14/Makefile
--- old/cpupower-5.10/Makefile 2020-11-12 20:06:53.000000000 +0100
+++ new/cpupower-5.14/Makefile 2021-07-18 20:27:25.000000000 +0200
@@ -270,14 +270,14 @@
$(MAKE) -C bench O=$(OUTPUT) clean
-install-lib:
+install-lib: libcpupower
$(INSTALL) -d $(DESTDIR)${libdir}
$(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/
$(INSTALL) -d $(DESTDIR)${includedir}
$(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h
$(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h
-install-tools:
+install-tools: $(OUTPUT)cpupower
$(INSTALL) -d $(DESTDIR)${bindir}
$(INSTALL_PROGRAM) $(OUTPUT)cpupower $(DESTDIR)${bindir}
$(INSTALL) -d $(DESTDIR)${bash_completion_dir}
@@ -293,14 +293,14 @@
$(INSTALL_DATA) -D man/cpupower-info.1
$(DESTDIR)${mandir}/man1/cpupower-info.1
$(INSTALL_DATA) -D man/cpupower-monitor.1
$(DESTDIR)${mandir}/man1/cpupower-monitor.1
-install-gmo:
+install-gmo: create-gmo
$(INSTALL) -d $(DESTDIR)${localedir}
for HLANG in $(LANGUAGES); do \
echo '$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo
$(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo'; \
$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo
$(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \
done;
-install-bench:
+install-bench: compile-bench
@#DESTDIR must be set from outside to survive
@sbindir=$(sbindir) bindir=$(bindir) docdir=$(docdir)
confdir=$(confdir) $(MAKE) -C bench O=$(OUTPUT) install
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/bench/Makefile
new/cpupower-5.14/bench/Makefile
--- old/cpupower-5.10/bench/Makefile 2020-11-12 20:06:53.000000000 +0100
+++ new/cpupower-5.14/bench/Makefile 2021-07-18 20:27:25.000000000 +0200
@@ -27,7 +27,7 @@
all: $(OUTPUT)cpufreq-bench
-install:
+install: $(OUTPUT)cpufreq-bench
mkdir -p $(DESTDIR)/$(sbindir)
mkdir -p $(DESTDIR)/$(bindir)
mkdir -p $(DESTDIR)/$(docdir)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/lib/cpupower.c
new/cpupower-5.14/lib/cpupower.c
--- old/cpupower-5.10/lib/cpupower.c 2020-11-12 20:06:53.000000000 +0100
+++ new/cpupower-5.14/lib/cpupower.c 2021-07-18 20:27:25.000000000 +0200
@@ -16,8 +16,8 @@
unsigned int cpupower_read_sysfs(const char *path, char *buf, size_t buflen)
{
- int fd;
ssize_t numread;
+ int fd;
fd = open(path, O_RDONLY);
if (fd == -1)
@@ -35,6 +35,27 @@
return (unsigned int) numread;
}
+unsigned int cpupower_write_sysfs(const char *path, char *buf, size_t buflen)
+{
+ ssize_t numwritten;
+ int fd;
+
+ fd = open(path, O_WRONLY);
+ if (fd == -1)
+ return 0;
+
+ numwritten = write(fd, buf, buflen - 1);
+ if (numwritten < 1) {
+ perror(path);
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return (unsigned int) numwritten;
+}
+
/*
* Detect whether a CPU is online
*
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/lib/cpupower_intern.h
new/cpupower-5.14/lib/cpupower_intern.h
--- old/cpupower-5.10/lib/cpupower_intern.h 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/lib/cpupower_intern.h 2021-07-18 20:27:25.000000000
+0200
@@ -1,6 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define PATH_TO_CPU "/sys/devices/system/cpu/"
+
+#ifndef MAX_LINE_LEN
#define MAX_LINE_LEN 4096
+#endif
+
#define SYSFS_PATH_MAX 255
unsigned int cpupower_read_sysfs(const char *path, char *buf, size_t buflen);
+unsigned int cpupower_write_sysfs(const char *path, char *buf, size_t buflen);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/cpufreq-info.c
new/cpupower-5.14/utils/cpufreq-info.c
--- old/cpupower-5.10/utils/cpufreq-info.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/cpufreq-info.c 2021-07-18 20:27:25.000000000
+0200
@@ -186,8 +186,7 @@
if ((cpupower_cpu_info.vendor == X86_VENDOR_AMD &&
cpupower_cpu_info.family >= 0x10) ||
cpupower_cpu_info.vendor == X86_VENDOR_HYGON) {
- ret = decode_pstates(cpu, cpupower_cpu_info.family, b_states,
- pstates, &pstate_no);
+ ret = decode_pstates(cpu, b_states, pstates, &pstate_no);
if (ret)
return ret;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/cpufreq-set.c
new/cpupower-5.14/utils/cpufreq-set.c
--- old/cpupower-5.10/utils/cpufreq-set.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/cpufreq-set.c 2021-07-18 20:27:25.000000000
+0200
@@ -315,6 +315,7 @@
}
}
+ get_cpustate();
/* loop over CPUs */
for (cpu = bitmask_first(cpus_chosen);
@@ -332,5 +333,7 @@
}
}
+ print_offline_cpus();
+
return 0;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/cpuidle-set.c
new/cpupower-5.14/utils/cpuidle-set.c
--- old/cpupower-5.10/utils/cpuidle-set.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/cpuidle-set.c 2021-07-18 20:27:25.000000000
+0200
@@ -95,6 +95,8 @@
exit(EXIT_FAILURE);
}
+ get_cpustate();
+
/* Default is: set all CPUs */
if (bitmask_isallclear(cpus_chosen))
bitmask_setall(cpus_chosen);
@@ -181,5 +183,7 @@
break;
}
}
+
+ print_offline_cpus();
return EXIT_SUCCESS;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/cpupower-info.c
new/cpupower-5.14/utils/cpupower-info.c
--- old/cpupower-5.10/utils/cpupower-info.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/cpupower-info.c 2021-07-18 20:27:25.000000000
+0200
@@ -101,7 +101,7 @@
}
if (params.perf_bias) {
- ret = msr_intel_get_perf_bias(cpu);
+ ret = cpupower_intel_get_perf_bias(cpu);
if (ret < 0) {
fprintf(stderr,
_("Could not read perf-bias value[%d]\n"), ret);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/cpupower-set.c
new/cpupower-5.14/utils/cpupower-set.c
--- old/cpupower-5.10/utils/cpupower-set.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/cpupower-set.c 2021-07-18 20:27:25.000000000
+0200
@@ -95,7 +95,7 @@
}
if (params.perf_bias) {
- ret = msr_intel_set_perf_bias(cpu, perf_bias);
+ ret = cpupower_intel_set_perf_bias(cpu, perf_bias);
if (ret) {
fprintf(stderr, _("Error setting perf-bias "
"value on CPU %d\n"), cpu);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/cpupower.c
new/cpupower-5.14/utils/cpupower.c
--- old/cpupower-5.10/utils/cpupower.c 2020-11-12 20:06:53.000000000 +0100
+++ new/cpupower-5.14/utils/cpupower.c 2021-07-18 20:27:25.000000000 +0200
@@ -34,6 +34,8 @@
int base_cpu;
/* Affected cpus chosen by -c/--cpu param */
struct bitmask *cpus_chosen;
+struct bitmask *online_cpus;
+struct bitmask *offline_cpus;
#ifdef DEBUG
int be_verbose;
@@ -178,6 +180,8 @@
char pathname[32];
cpus_chosen = bitmask_alloc(sysconf(_SC_NPROCESSORS_CONF));
+ online_cpus = bitmask_alloc(sysconf(_SC_NPROCESSORS_CONF));
+ offline_cpus = bitmask_alloc(sysconf(_SC_NPROCESSORS_CONF));
argc--;
argv += 1;
@@ -230,6 +234,10 @@
ret = p->main(argc, argv);
if (cpus_chosen)
bitmask_free(cpus_chosen);
+ if (online_cpus)
+ bitmask_free(online_cpus);
+ if (offline_cpus)
+ bitmask_free(offline_cpus);
return ret;
}
print_help();
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/helpers/amd.c
new/cpupower-5.14/utils/helpers/amd.c
--- old/cpupower-5.10/utils/helpers/amd.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/helpers/amd.c 2021-07-18 20:27:25.000000000
+0200
@@ -13,7 +13,8 @@
#define MSR_AMD_PSTATE 0xc0010064
#define MSR_AMD_PSTATE_LIMIT 0xc0010061
-union msr_pstate {
+union core_pstate {
+ /* pre fam 17h: */
struct {
unsigned fid:6;
unsigned did:3;
@@ -26,7 +27,8 @@
unsigned idddiv:2;
unsigned res3:21;
unsigned en:1;
- } bits;
+ } pstate;
+ /* since fam 17h: */
struct {
unsigned fid:8;
unsigned did:6;
@@ -35,37 +37,37 @@
unsigned idddiv:2;
unsigned res1:31;
unsigned en:1;
- } fam17h_bits;
+ } pstatedef;
unsigned long long val;
};
-static int get_did(int family, union msr_pstate pstate)
+static int get_did(union core_pstate pstate)
{
int t;
- if (family == 0x12)
+ if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATEDEF)
+ t = pstate.pstatedef.did;
+ else if (cpupower_cpu_info.family == 0x12)
t = pstate.val & 0xf;
- else if (family == 0x17 || family == 0x18)
- t = pstate.fam17h_bits.did;
else
- t = pstate.bits.did;
+ t = pstate.pstate.did;
return t;
}
-static int get_cof(int family, union msr_pstate pstate)
+static int get_cof(union core_pstate pstate)
{
int t;
int fid, did, cof;
- did = get_did(family, pstate);
- if (family == 0x17 || family == 0x18) {
- fid = pstate.fam17h_bits.fid;
+ did = get_did(pstate);
+ if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_PSTATEDEF) {
+ fid = pstate.pstatedef.fid;
cof = 200 * fid / did;
} else {
t = 0x10;
- fid = pstate.bits.fid;
- if (family == 0x11)
+ fid = pstate.pstate.fid;
+ if (cpupower_cpu_info.family == 0x11)
t = 0x8;
cof = (100 * (fid + t)) >> did;
}
@@ -74,8 +76,7 @@
/* Needs:
* cpu -> the cpu that gets evaluated
- * cpu_family -> The cpu's family (0x10, 0x12,...)
- * boots_states -> how much boost states the machines support
+ * boost_states -> how much boost states the machines support
*
* Fills up:
* pstates -> a pointer to an array of size MAX_HW_PSTATES
@@ -85,31 +86,23 @@
*
* returns zero on success, -1 on failure
*/
-int decode_pstates(unsigned int cpu, unsigned int cpu_family,
- int boost_states, unsigned long *pstates, int *no)
+int decode_pstates(unsigned int cpu, int boost_states,
+ unsigned long *pstates, int *no)
{
- int i, psmax, pscur;
- union msr_pstate pstate;
+ int i, psmax;
+ union core_pstate pstate;
unsigned long long val;
- /* Only read out frequencies from HW when CPU might be boostable
- to keep the code as short and clean as possible.
- Otherwise frequencies are exported via ACPI tables.
- */
- if (cpu_family < 0x10 || cpu_family == 0x14)
+ /* Only read out frequencies from HW if HW Pstate is supported,
+ * otherwise frequencies are exported via ACPI tables.
+ */
+ if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_HW_PSTATE))
return -1;
if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val))
return -1;
psmax = (val >> 4) & 0x7;
-
- if (read_msr(cpu, MSR_AMD_PSTATE_STATUS, &val))
- return -1;
-
- pscur = val & 0x7;
-
- pscur += boost_states;
psmax += boost_states;
for (i = 0; i <= psmax; i++) {
if (i >= MAX_HW_PSTATES) {
@@ -119,12 +112,12 @@
}
if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val))
return -1;
- if ((cpu_family == 0x17) && (!pstate.fam17h_bits.en))
- continue;
- else if (!pstate.bits.en)
+
+ /* The enabled bit (bit 63) is common for all families */
+ if (!pstate.pstatedef.en)
continue;
- pstates[i] = get_cof(cpu_family, pstate);
+ pstates[i] = get_cof(pstate);
}
*no = i;
return 0;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/helpers/cpuid.c
new/cpupower-5.14/utils/helpers/cpuid.c
--- old/cpupower-5.10/utils/helpers/cpuid.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/helpers/cpuid.c 2021-07-18 20:27:25.000000000
+0200
@@ -128,9 +128,23 @@
/* AMD or Hygon Boost state enable/disable register */
if (cpu_info->vendor == X86_VENDOR_AMD ||
cpu_info->vendor == X86_VENDOR_HYGON) {
- if (ext_cpuid_level >= 0x80000007 &&
- (cpuid_edx(0x80000007) & (1 << 9)))
- cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
+ if (ext_cpuid_level >= 0x80000007) {
+ if (cpuid_edx(0x80000007) & (1 << 9)) {
+ cpu_info->caps |= CPUPOWER_CAP_AMD_CPB;
+
+ if (cpu_info->family >= 0x17)
+ cpu_info->caps |=
CPUPOWER_CAP_AMD_CPB_MSR;
+ }
+
+ if ((cpuid_edx(0x80000007) & (1 << 7)) &&
+ cpu_info->family != 0x14) {
+ /* HW pstate was not implemented in family 0x14
*/
+ cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE;
+
+ if (cpu_info->family >= 0x17)
+ cpu_info->caps |=
CPUPOWER_CAP_AMD_PSTATEDEF;
+ }
+ }
if (ext_cpuid_level >= 0x80000008 &&
cpuid_ebx(0x80000008) & (1 << 4))
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/helpers/helpers.h
new/cpupower-5.14/utils/helpers/helpers.h
--- old/cpupower-5.10/utils/helpers/helpers.h 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/helpers/helpers.h 2021-07-18 20:27:25.000000000
+0200
@@ -64,12 +64,15 @@
#define CPUPOWER_CAP_INV_TSC 0x00000001
#define CPUPOWER_CAP_APERF 0x00000002
-#define CPUPOWER_CAP_AMD_CBP 0x00000004
+#define CPUPOWER_CAP_AMD_CPB 0x00000004
#define CPUPOWER_CAP_PERF_BIAS 0x00000008
#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
#define CPUPOWER_CAP_IS_SNB 0x00000020
#define CPUPOWER_CAP_INTEL_IDA 0x00000040
#define CPUPOWER_CAP_AMD_RDPRU 0x00000080
+#define CPUPOWER_CAP_AMD_HW_PSTATE 0x00000100
+#define CPUPOWER_CAP_AMD_PSTATEDEF 0x00000200
+#define CPUPOWER_CAP_AMD_CPB_MSR 0x00000400
#define CPUPOWER_AMD_CPBDIS 0x02000000
@@ -94,6 +97,8 @@
*/
extern int get_cpu_info(struct cpupower_cpu_info *cpu_info);
extern struct cpupower_cpu_info cpupower_cpu_info;
+
+
/* cpuid and cpuinfo helpers **************************/
/* X86 ONLY ****************************************/
@@ -105,8 +110,8 @@
extern int read_msr(int cpu, unsigned int idx, unsigned long long *val);
extern int write_msr(int cpu, unsigned int idx, unsigned long long val);
-extern int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val);
-extern int msr_intel_get_perf_bias(unsigned int cpu);
+extern int cpupower_intel_set_perf_bias(unsigned int cpu, unsigned int val);
+extern int cpupower_intel_get_perf_bias(unsigned int cpu);
extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu);
/* Read/Write msr ****************************/
@@ -123,8 +128,8 @@
/* AMD HW pstate decoding **************************/
-extern int decode_pstates(unsigned int cpu, unsigned int cpu_family,
- int boost_states, unsigned long *pstates, int *no);
+extern int decode_pstates(unsigned int cpu, int boost_states,
+ unsigned long *pstates, int *no);
/* AMD HW pstate decoding **************************/
@@ -141,18 +146,17 @@
/* cpuid and cpuinfo helpers **************************/
/* X86 ONLY ********************************************/
#else
-static inline int decode_pstates(unsigned int cpu, unsigned int cpu_family,
- int boost_states, unsigned long *pstates,
- int *no)
+static inline int decode_pstates(unsigned int cpu, int boost_states,
+ unsigned long *pstates, int *no)
{ return -1; };
static inline int read_msr(int cpu, unsigned int idx, unsigned long long *val)
{ return -1; };
static inline int write_msr(int cpu, unsigned int idx, unsigned long long val)
{ return -1; };
-static inline int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val)
+static inline int cpupower_intel_set_perf_bias(unsigned int cpu, unsigned int
val)
{ return -1; };
-static inline int msr_intel_get_perf_bias(unsigned int cpu)
+static inline int cpupower_intel_get_perf_bias(unsigned int cpu)
{ return -1; };
static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
{ return 0; };
@@ -171,4 +175,14 @@
static inline unsigned int cpuid_edx(unsigned int op) { return 0; };
#endif /* defined(__i386__) || defined(__x86_64__) */
+/*
+ * CPU State related functions
+ */
+extern struct bitmask *online_cpus;
+extern struct bitmask *offline_cpus;
+
+void get_cpustate(void);
+void print_online_cpus(void);
+void print_offline_cpus(void);
+
#endif /* __CPUPOWERUTILS_HELPERS__ */
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/helpers/misc.c
new/cpupower-5.14/utils/helpers/misc.c
--- old/cpupower-5.10/utils/helpers/misc.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/helpers/misc.c 2021-07-18 20:27:25.000000000
+0200
@@ -1,24 +1,27 @@
// SPDX-License-Identifier: GPL-2.0
-#if defined(__i386__) || defined(__x86_64__)
+
+#include <stdio.h>
+#include <errno.h>
+#include <stdlib.h>
#include "helpers/helpers.h"
+#include "helpers/sysfs.h"
+
+#if defined(__i386__) || defined(__x86_64__)
+
+#include "cpupower_intern.h"
#define MSR_AMD_HWCR 0xc0010015
int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
int *states)
{
- struct cpupower_cpu_info cpu_info;
int ret;
unsigned long long val;
*support = *active = *states = 0;
- ret = get_cpu_info(&cpu_info);
- if (ret)
- return ret;
-
- if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
+ if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CPB) {
*support = 1;
/* AMD Family 0x17 does not utilize PCI D18F4 like prior
@@ -26,7 +29,7 @@
* has Hardware determined variable increments instead.
*/
- if (cpu_info.family == 0x17 || cpu_info.family == 0x18) {
+ if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CPB_MSR) {
if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
if (!(val & CPUPOWER_AMD_CPBDIS))
*active = 1;
@@ -40,4 +43,104 @@
*support = *active = 1;
return 0;
}
+
+int cpupower_intel_get_perf_bias(unsigned int cpu)
+{
+ char linebuf[MAX_LINE_LEN];
+ char path[SYSFS_PATH_MAX];
+ unsigned long val;
+ char *endp;
+
+ if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_PERF_BIAS))
+ return -1;
+
+ snprintf(path, sizeof(path), PATH_TO_CPU
"cpu%u/power/energy_perf_bias", cpu);
+
+ if (cpupower_read_sysfs(path, linebuf, MAX_LINE_LEN) == 0)
+ return -1;
+
+ val = strtol(linebuf, &endp, 0);
+ if (endp == linebuf || errno == ERANGE)
+ return -1;
+
+ return val;
+}
+
+int cpupower_intel_set_perf_bias(unsigned int cpu, unsigned int val)
+{
+ char path[SYSFS_PATH_MAX];
+ char linebuf[3] = {};
+
+ if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_PERF_BIAS))
+ return -1;
+
+ snprintf(path, sizeof(path), PATH_TO_CPU
"cpu%u/power/energy_perf_bias", cpu);
+ snprintf(linebuf, sizeof(linebuf), "%d", val);
+
+ if (cpupower_write_sysfs(path, linebuf, 3) <= 0)
+ return -1;
+
+ return 0;
+}
+
#endif /* #if defined(__i386__) || defined(__x86_64__) */
+
+/* get_cpustate
+ *
+ * Gather the information of all online CPUs into bitmask struct
+ */
+void get_cpustate(void)
+{
+ unsigned int cpu = 0;
+
+ bitmask_clearall(online_cpus);
+ bitmask_clearall(offline_cpus);
+
+ for (cpu = bitmask_first(cpus_chosen);
+ cpu <= bitmask_last(cpus_chosen); cpu++) {
+
+ if (cpupower_is_cpu_online(cpu) == 1)
+ bitmask_setbit(online_cpus, cpu);
+ else
+ bitmask_setbit(offline_cpus, cpu);
+
+ continue;
+ }
+}
+
+/* print_online_cpus
+ *
+ * Print the CPU numbers of all CPUs that are online currently
+ */
+void print_online_cpus(void)
+{
+ int str_len = 0;
+ char *online_cpus_str = NULL;
+
+ str_len = online_cpus->size * 5;
+ online_cpus_str = (void *)malloc(sizeof(char) * str_len);
+
+ if (!bitmask_isallclear(online_cpus)) {
+ bitmask_displaylist(online_cpus_str, str_len, online_cpus);
+ printf(_("Following CPUs are online:\n%s\n"), online_cpus_str);
+ }
+}
+
+/* print_offline_cpus
+ *
+ * Print the CPU numbers of all CPUs that are offline currently
+ */
+void print_offline_cpus(void)
+{
+ int str_len = 0;
+ char *offline_cpus_str = NULL;
+
+ str_len = offline_cpus->size * 5;
+ offline_cpus_str = (void *)malloc(sizeof(char) * str_len);
+
+ if (!bitmask_isallclear(offline_cpus)) {
+ bitmask_displaylist(offline_cpus_str, str_len, offline_cpus);
+ printf(_("Following CPUs are offline:\n%s\n"),
offline_cpus_str);
+ printf(_("cpupower set operation was not performed on them\n"));
+ }
+}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpupower-5.10/utils/helpers/msr.c
new/cpupower-5.14/utils/helpers/msr.c
--- old/cpupower-5.10/utils/helpers/msr.c 2020-11-12 20:06:53.000000000
+0100
+++ new/cpupower-5.14/utils/helpers/msr.c 2021-07-18 20:27:25.000000000
+0200
@@ -11,7 +11,6 @@
/* Intel specific MSRs */
#define MSR_IA32_PERF_STATUS 0x198
#define MSR_IA32_MISC_ENABLES 0x1a0
-#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1ad
/*
@@ -73,33 +72,6 @@
return -1;
}
-int msr_intel_get_perf_bias(unsigned int cpu)
-{
- unsigned long long val;
- int ret;
-
- if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_PERF_BIAS))
- return -1;
-
- ret = read_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &val);
- if (ret)
- return ret;
- return val;
-}
-
-int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val)
-{
- int ret;
-
- if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_PERF_BIAS))
- return -1;
-
- ret = write_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, val);
- if (ret)
- return ret;
- return 0;
-}
-
unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
{
unsigned long long val;
++++++ cpupower_rapl.patch ++++++
--- /var/tmp/diff_new_pack.BVtrJL/_old 2021-07-20 15:40:06.577541653 +0200
+++ /var/tmp/diff_new_pack.BVtrJL/_new 2021-07-20 15:40:06.577541653 +0200
@@ -25,11 +25,19 @@
Signed-off-by: Thomas Renninger <tr...@suse.com>
-Index: cpupower-5.5/Makefile
-===================================================================
---- cpupower-5.5.orig/Makefile 2019-11-28 02:45:48.000000000 +0100
-+++ cpupower-5.5/Makefile 2019-11-28 14:27:56.753759105 +0100
-@@ -133,7 +133,7 @@ UTIL_OBJS = utils/helpers/amd.o utils/h
+---
+ Makefile | 11 +
+ lib/powercap.c | 290
+++++++++++++++++++++++++++++++++++++++++++
+ lib/powercap.h | 54 ++++++++
+ man/cpupower-powercap-info.1 | 25 +++
+ utils/builtin.h | 2
+ utils/cpupower.c | 1
+ utils/powercap-info.c | 113 ++++++++++++++++
+ 7 files changed, 492 insertions(+), 4 deletions(-)
+
+--- a/Makefile
++++ b/Makefile
+@@ -133,7 +133,7 @@
utils/idle_monitor/mperf_monitor.o
utils/idle_monitor/cpupower-monitor.o \
utils/cpupower.o utils/cpufreq-info.o utils/cpufreq-set.o \
utils/cpupower-set.o utils/cpupower-info.o utils/cpuidle-info.o \
@@ -38,7 +46,7 @@
UTIL_SRC := $(UTIL_OBJS:.o=.c)
-@@ -143,9 +143,9 @@ UTIL_HEADERS = utils/helpers/helpers.h u
+@@ -143,9 +143,9 @@
utils/helpers/bitmask.h \
utils/idle_monitor/idle_monitors.h utils/idle_monitor/idle_monitors.def
@@ -51,23 +59,23 @@
LIB_OBJS := $(addprefix $(OUTPUT),$(LIB_OBJS))
override CFLAGS += -pipe
-@@ -276,6 +276,7 @@ install-lib:
+@@ -276,6 +276,7 @@
$(INSTALL) -d $(DESTDIR)${includedir}
$(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h
$(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h
+ $(INSTALL_DATA) lib/powercap.h $(DESTDIR)${includedir}/powercap.h
- install-tools:
+ install-tools: $(OUTPUT)cpupower
$(INSTALL) -d $(DESTDIR)${bindir}
-@@ -292,6 +293,7 @@ install-man:
+@@ -292,6 +293,7 @@
$(INSTALL_DATA) -D man/cpupower-set.1
$(DESTDIR)${mandir}/man1/cpupower-set.1
$(INSTALL_DATA) -D man/cpupower-info.1
$(DESTDIR)${mandir}/man1/cpupower-info.1
$(INSTALL_DATA) -D man/cpupower-monitor.1
$(DESTDIR)${mandir}/man1/cpupower-monitor.1
+ $(INSTALL_DATA) -D man/cpupower-powercap-info.1
$(DESTDIR)${mandir}/man1/cpupower-powercap-info.1
- install-gmo:
+ install-gmo: create-gmo
$(INSTALL) -d $(DESTDIR)${localedir}
-@@ -321,6 +323,7 @@ uninstall:
+@@ -321,6 +323,7 @@
- rm -f $(DESTDIR)${mandir}/man1/cpupower-set.1
- rm -f $(DESTDIR)${mandir}/man1/cpupower-info.1
- rm -f $(DESTDIR)${mandir}/man1/cpupower-monitor.1
@@ -75,10 +83,8 @@
- for HLANG in $(LANGUAGES); do \
rm -f $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \
done;
-Index: cpupower-5.5/lib/powercap.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ cpupower-5.5/lib/powercap.c 2019-11-28 14:27:56.753759105 +0100
+--- /dev/null
++++ b/lib/powercap.c
@@ -0,0 +1,290 @@
+/*
+ * (C) 2016 Thomas Renninger <tr...@suse.com>
@@ -370,10 +376,8 @@
+ }
+ return 0;
+}
-Index: cpupower-5.5/lib/powercap.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ cpupower-5.5/lib/powercap.h 2019-11-28 14:27:56.753759105 +0100
+--- /dev/null
++++ b/lib/powercap.h
@@ -0,0 +1,54 @@
+/*
+ * (C) 2016 Thomas Renninger <tr...@suse.com>
@@ -429,11 +433,37 @@
+
+
+#endif /* __CPUPOWER_RAPL_H__ */
-Index: cpupower-5.5/utils/builtin.h
-===================================================================
---- cpupower-5.5.orig/utils/builtin.h 2019-11-28 02:45:48.000000000 +0100
-+++ cpupower-5.5/utils/builtin.h 2019-11-28 14:27:56.753759105 +0100
-@@ -8,6 +8,8 @@ extern int cmd_freq_set(int argc, const
+--- /dev/null
++++ b/man/cpupower-powercap-info.1
+@@ -0,0 +1,25 @@
++.TH CPUPOWER\-POWERCAP\-INFO "1" "05/08/2016" "" "cpupower Manual"
++.SH NAME
++cpupower\-powercap\-info \- Shows powercapping related kernel and hardware
configurations
++.SH SYNOPSIS
++.ft B
++.B cpupower powercap-info
++
++.SH DESCRIPTION
++\fBcpupower powercap-info \fP shows kernel powercapping subsystem information.
++This needs hardware support and a loaded powercapping driver (at this time
only
++intel_rapl driver exits) exporting hardware values userspace via sysfs.
++
++Some options are platform wide, some affect single cores. By default values
++of core zero are displayed only. cpupower --cpu all cpuinfo will show the
++settings of all cores, see cpupower(1) how to choose specific cores.
++
++.SH "DOCUMENTATION"
++
++kernel sources:
++Documentation/power/powercap/powercap.txt
++
++
++.SH "SEE ALSO"
++
++cpupower(1)
+--- a/utils/builtin.h
++++ b/utils/builtin.h
+@@ -8,6 +8,8 @@
extern int cmd_freq_info(int argc, const char **argv);
extern int cmd_idle_set(int argc, const char **argv);
extern int cmd_idle_info(int argc, const char **argv);
@@ -442,11 +472,9 @@
extern int cmd_monitor(int argc, const char **argv);
#endif
-Index: cpupower-5.5/utils/cpupower.c
-===================================================================
---- cpupower-5.5.orig/utils/cpupower.c 2019-11-28 02:45:48.000000000 +0100
-+++ cpupower-5.5/utils/cpupower.c 2019-11-28 14:27:56.753759105 +0100
-@@ -52,6 +52,7 @@ static struct cmd_struct commands[] = {
+--- a/utils/cpupower.c
++++ b/utils/cpupower.c
+@@ -54,6 +54,7 @@
{ "frequency-set", cmd_freq_set, 1 },
{ "idle-info", cmd_idle_info, 0 },
{ "idle-set", cmd_idle_set, 1 },
@@ -454,10 +482,8 @@
{ "set", cmd_set, 1 },
{ "info", cmd_info, 0 },
{ "monitor", cmd_monitor, 0 },
-Index: cpupower-5.5/utils/powercap-info.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ cpupower-5.5/utils/powercap-info.c 2019-11-28 14:27:56.753759105 +0100
+--- /dev/null
++++ b/utils/powercap-info.c
@@ -0,0 +1,113 @@
+#include <unistd.h>
+#include <stdio.h>
@@ -572,33 +598,3 @@
+ powercap_show();
+ return 0;
+}
-Index: cpupower-5.5/man/cpupower-powercap-info.1
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ cpupower-5.5/man/cpupower-powercap-info.1 2019-11-28 14:27:56.753759105
+0100
-@@ -0,0 +1,25 @@
-+.TH CPUPOWER\-POWERCAP\-INFO "1" "05/08/2016" "" "cpupower Manual"
-+.SH NAME
-+cpupower\-powercap\-info \- Shows powercapping related kernel and hardware
configurations
-+.SH SYNOPSIS
-+.ft B
-+.B cpupower powercap-info
-+
-+.SH DESCRIPTION
-+\fBcpupower powercap-info \fP shows kernel powercapping subsystem information.
-+This needs hardware support and a loaded powercapping driver (at this time
only
-+intel_rapl driver exits) exporting hardware values userspace via sysfs.
-+
-+Some options are platform wide, some affect single cores. By default values
-+of core zero are displayed only. cpupower --cpu all cpuinfo will show the
-+settings of all cores, see cpupower(1) how to choose specific cores.
-+
-+.SH "DOCUMENTATION"
-+
-+kernel sources:
-+Documentation/power/powercap/powercap.txt
-+
-+
-+.SH "SEE ALSO"
-+
-+cpupower(1)
++++++ intel-speed-select-1.6.tar.bz2 -> intel-speed-select-1.10.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/intel-speed-select-1.6/isst-config.c
new/intel-speed-select-1.10/isst-config.c
--- old/intel-speed-select-1.6/isst-config.c 2020-11-12 20:06:53.000000000
+0100
+++ new/intel-speed-select-1.10/isst-config.c 2021-07-18 20:27:25.000000000
+0200
@@ -15,7 +15,7 @@
int arg;
};
-static const char *version_str = "v1.6";
+static const char *version_str = "v1.10";
static const int supported_api_ver = 1;
static struct isst_if_platform_info isst_platform_info;
static char *progname;
@@ -106,6 +106,22 @@
return 0;
}
+int is_spr_platform(void)
+{
+ if (cpu_model == 0x8F)
+ return 1;
+
+ return 0;
+}
+
+int is_icx_platform(void)
+{
+ if (cpu_model == 0x6A || cpu_model == 0x6C)
+ return 1;
+
+ return 0;
+}
+
static int update_cpu_model(void)
{
unsigned int ebx, ecx, edx;
@@ -328,8 +344,12 @@
int core_id, pkg_id, die_id;
ret = get_stored_topology_info(cpu, &core_id, &pkg_id, &die_id);
- if (!ret)
+ if (!ret) {
+ if (die_id < 0)
+ die_id = 0;
+
return die_id;
+ }
}
if (ret < 0)
@@ -377,6 +397,18 @@
close(fd);
}
+static void force_all_cpus_online(void)
+{
+ int i;
+
+ fprintf(stderr, "Forcing all CPUs online\n");
+
+ for (i = 0; i < topo_max_cpus; ++i)
+ set_cpu_online_offline(i, 1);
+
+ unlink("/var/run/isst_cpu_topology.dat");
+}
+
#define MAX_PACKAGE_COUNT 8
#define MAX_DIE_PER_PACKAGE 2
static void for_each_online_package_in_set(void (*callback)(int, void *, void
*,
@@ -955,6 +987,10 @@
fprintf(outf, "Intel(R) SST-BF (feature base-freq) is not
supported\n");
ret = isst_read_pm_config(i, &cp_state, &cp_cap);
+ if (ret) {
+ fprintf(outf, "Intel(R) SST-CP (feature core-power) status is
unknown\n");
+ return;
+ }
if (cp_cap)
fprintf(outf, "Intel(R) SST-CP (feature core-power) is
supported\n");
else
@@ -1245,6 +1281,8 @@
isst_ctdp_display_information_end(outf);
}
+static void adjust_scaling_max_from_base_freq(int cpu);
+
static void set_tdp_level_for_cpu(int cpu, void *arg1, void *arg2, void *arg3,
void *arg4)
{
@@ -1263,6 +1301,9 @@
int pkg_id = get_physical_package_id(cpu);
int die_id = get_physical_die_id(cpu);
+ /* Wait for updated base frequencies */
+ usleep(2000);
+
fprintf(stderr, "Option is set to online/offline\n");
ctdp_level.core_cpumask_size =
alloc_cpu_set(&ctdp_level.core_cpumask);
@@ -1279,6 +1320,7 @@
if (CPU_ISSET_S(i,
ctdp_level.core_cpumask_size, ctdp_level.core_cpumask)) {
fprintf(stderr, "online cpu
%d\n", i);
set_cpu_online_offline(i, 1);
+
adjust_scaling_max_from_base_freq(i);
} else {
fprintf(stderr, "offline cpu
%d\n", i);
set_cpu_online_offline(i, 0);
@@ -1436,6 +1478,31 @@
return 0;
}
+static int no_turbo(void)
+{
+ return parse_int_file(0,
"/sys/devices/system/cpu/intel_pstate/no_turbo");
+}
+
+static void adjust_scaling_max_from_base_freq(int cpu)
+{
+ int base_freq, scaling_max_freq;
+
+ scaling_max_freq = parse_int_file(0,
"/sys/devices/system/cpu/cpu%d/cpufreq/scaling_max_freq", cpu);
+ base_freq = get_cpufreq_base_freq(cpu);
+ if (scaling_max_freq < base_freq || no_turbo())
+ set_cpufreq_scaling_min_max(cpu, 1, base_freq);
+}
+
+static void adjust_scaling_min_from_base_freq(int cpu)
+{
+ int base_freq, scaling_min_freq;
+
+ scaling_min_freq = parse_int_file(0,
"/sys/devices/system/cpu/cpu%d/cpufreq/scaling_min_freq", cpu);
+ base_freq = get_cpufreq_base_freq(cpu);
+ if (scaling_min_freq < base_freq)
+ set_cpufreq_scaling_min_max(cpu, 0, base_freq);
+}
+
static int set_clx_pbf_cpufreq_scaling_min_max(int cpu)
{
struct isst_pkg_ctdp_level_info *ctdp_level;
@@ -1533,6 +1600,7 @@
continue;
set_cpufreq_scaling_min_max_from_cpuinfo(i, 1, 0);
+ adjust_scaling_min_from_base_freq(i);
}
}
@@ -2268,6 +2336,102 @@
isst_ctdp_display_information_end(outf);
}
+static void set_turbo_mode_for_cpu(int cpu, int status)
+{
+ int base_freq;
+
+ if (status) {
+ base_freq = get_cpufreq_base_freq(cpu);
+ set_cpufreq_scaling_min_max(cpu, 1, base_freq);
+ } else {
+ set_scaling_max_to_cpuinfo_max(cpu);
+ }
+
+ if (status) {
+ isst_display_result(cpu, outf, "turbo-mode", "enable", 0);
+ } else {
+ isst_display_result(cpu, outf, "turbo-mode", "disable", 0);
+ }
+}
+
+static void set_turbo_mode(int arg)
+{
+ int i, enable = arg;
+
+ if (cmd_help) {
+ if (enable)
+ fprintf(stderr, "Set turbo mode enable\n");
+ else
+ fprintf(stderr, "Set turbo mode disable\n");
+ exit(0);
+ }
+
+ isst_ctdp_display_information_start(outf);
+
+ for (i = 0; i < topo_max_cpus; ++i) {
+ int online;
+
+ if (i)
+ online = parse_int_file(
+ 1, "/sys/devices/system/cpu/cpu%d/online", i);
+ else
+ online =
+ 1; /* online entry for CPU 0 needs some special
configs */
+
+ if (online)
+ set_turbo_mode_for_cpu(i, enable);
+
+ }
+ isst_ctdp_display_information_end(outf);
+}
+
+static void get_set_trl(int cpu, void *arg1, void *arg2, void *arg3,
+ void *arg4)
+{
+ unsigned long long trl;
+ int set = *(int *)arg4;
+ int ret;
+
+ if (set && !fact_trl) {
+ isst_display_error_info_message(1, "Invalid TRL. Specify with
[-t|--trl]", 0, 0);
+ exit(0);
+ }
+
+ if (set) {
+ ret = isst_set_trl(cpu, fact_trl);
+ isst_display_result(cpu, outf, "turbo-mode", "set-trl", ret);
+ return;
+ }
+
+ ret = isst_get_trl(cpu, &trl);
+ if (ret)
+ isst_display_result(cpu, outf, "turbo-mode", "get-trl", ret);
+ else
+ isst_trl_display_information(cpu, outf, trl);
+}
+
+static void process_trl(int arg)
+{
+ if (cmd_help) {
+ if (arg) {
+ fprintf(stderr, "Set TRL (turbo ratio limits)\n");
+ fprintf(stderr, "\t t|--trl: Specify turbo ratio limit
for setting TRL\n");
+ } else {
+ fprintf(stderr, "Get TRL (turbo ratio limits)\n");
+ }
+ exit(0);
+ }
+
+ isst_ctdp_display_information_start(outf);
+ if (max_target_cpus)
+ for_each_online_target_cpu_in_set(get_set_trl, NULL,
+ NULL, NULL, &arg);
+ else
+ for_each_online_package_in_set(get_set_trl, NULL,
+ NULL, NULL, &arg);
+ isst_ctdp_display_information_end(outf);
+}
+
static struct process_cmd_struct clx_n_cmds[] = {
{ "perf-profile", "info", dump_isst_config, 0 },
{ "base-freq", "info", dump_pbf_config, 0 },
@@ -2298,6 +2462,10 @@
{ "core-power", "get-config", dump_clos_config, 0 },
{ "core-power", "assoc", set_clos_assoc, 0 },
{ "core-power", "get-assoc", get_clos_assoc, 0 },
+ { "turbo-mode", "enable", set_turbo_mode, 0 },
+ { "turbo-mode", "disable", set_turbo_mode, 1 },
+ { "turbo-mode", "get-trl", process_trl, 0 },
+ { "turbo-mode", "set-trl", process_trl, 1 },
{ NULL, NULL, NULL }
};
@@ -2513,6 +2681,16 @@
printf("\tcommand : disable\n");
}
+static void turbo_mode_help(void)
+{
+ printf("turbo-mode:\tEnables users to enable/disable turbo mode by
adjusting frequency settings. Also allows to get and set turbo ratio limits
(TRL).\n");
+ printf("\tcommand : enable\n");
+ printf("\tcommand : disable\n");
+ printf("\tcommand : get-trl\n");
+ printf("\tcommand : set-trl\n");
+}
+
+
static void core_power_help(void)
{
printf("core-power:\tInterface that allows user to define per
core/tile\n\
@@ -2537,6 +2715,7 @@
{ "base-freq", pbf_help },
{ "turbo-freq", fact_help },
{ "core-power", core_power_help },
+ { "turbo-mode", turbo_mode_help },
{ NULL, NULL }
};
@@ -2600,7 +2779,7 @@
if (is_clx_n_platform())
printf("\nFEATURE : [perf-profile|base-freq]\n");
else
- printf("\nFEATURE :
[perf-profile|base-freq|turbo-freq|core-power]\n");
+ printf("\nFEATURE :
[perf-profile|base-freq|turbo-freq|core-power|turbo-mode]\n");
printf("\nFor help on each feature, use -h|--help\n");
printf("\tFor example: intel-speed-select perf-profile -h\n");
@@ -2616,6 +2795,7 @@
printf("\t[-f|--format] : output format [json|text]. Default: text\n");
printf("\t[-h|--help] : Print help\n");
printf("\t[-i|--info] : Print platform information\n");
+ printf("\t[-a|--all-cpus-online] : Force online every CPU in the
system\n");
printf("\t[-o|--out] : Output file\n");
printf("\t\t\tDefault : stderr\n");
printf("\t[-p|--pause] : Delay between two mail box commands in
milliseconds\n");
@@ -2644,7 +2824,6 @@
static void print_version(void)
{
fprintf(outf, "Version %s\n", version_str);
- fprintf(outf, "Build date %s time %s\n", __DATE__, __TIME__);
exit(0);
}
@@ -2653,11 +2832,12 @@
const char *pathname = "/dev/isst_interface";
char *ptr;
FILE *fp;
- int opt;
+ int opt, force_cpus_online = 0;
int option_index = 0;
int ret;
static struct option long_options[] = {
+ { "all-cpus-online", no_argument, 0, 'a' },
{ "cpu", required_argument, 0, 'c' },
{ "debug", no_argument, 0, 'd' },
{ "format", required_argument, 0, 'f' },
@@ -2693,9 +2873,12 @@
}
progname = argv[0];
- while ((opt = getopt_long_only(argc, argv, "+c:df:hio:v", long_options,
+ while ((opt = getopt_long_only(argc, argv, "+c:df:hio:va", long_options,
&option_index)) != -1) {
switch (opt) {
+ case 'a':
+ force_cpus_online = 1;
+ break;
case 'c':
parse_cpu_command(optarg);
break;
@@ -2745,6 +2928,8 @@
exit(0);
}
set_max_cpu_num();
+ if (force_cpus_online)
+ force_all_cpus_online();
store_cpu_topology();
set_cpu_present_cpu_mask();
set_cpu_target_cpu_mask();
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/intel-speed-select-1.6/isst-core.c
new/intel-speed-select-1.10/isst-core.c
--- old/intel-speed-select-1.6/isst-core.c 2020-11-12 20:06:53.000000000
+0100
+++ new/intel-speed-select-1.10/isst-core.c 2021-07-18 20:27:25.000000000
+0200
@@ -201,6 +201,7 @@
{
unsigned int resp;
int ret;
+
ret = isst_send_mbox_command(cpu, CONFIG_TDP, CONFIG_TDP_GET_MEM_FREQ,
0, config_index, &resp);
if (ret) {
@@ -209,6 +210,20 @@
}
ctdp_level->mem_freq = resp & GENMASK(7, 0);
+ if (is_spr_platform()) {
+ ctdp_level->mem_freq *= 200;
+ } else if (is_icx_platform()) {
+ if (ctdp_level->mem_freq < 7) {
+ ctdp_level->mem_freq = (12 - ctdp_level->mem_freq) *
133.33 * 2 * 10;
+ ctdp_level->mem_freq /= 10;
+ if (ctdp_level->mem_freq % 10 > 5)
+ ctdp_level->mem_freq++;
+ } else {
+ ctdp_level->mem_freq = 0;
+ }
+ } else {
+ ctdp_level->mem_freq = 0;
+ }
debug_printf(
"cpu:%d ctdp:%d CONFIG_TDP_GET_MEM_FREQ resp:%x uncore
mem_freq:%d\n",
cpu, config_index, resp, ctdp_level->mem_freq);
@@ -665,6 +680,17 @@
return 0;
}
+int isst_get_trl(int cpu, unsigned long long *trl)
+{
+ int ret;
+
+ ret = isst_send_msr_command(cpu, 0x1AD, 0, trl);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
int isst_set_trl(int cpu, unsigned long long trl)
{
int ret;
@@ -804,7 +830,7 @@
return ret;
}
- if (!pkg_dev->enabled) {
+ if (!pkg_dev->enabled && is_skx_based_platform()) {
int freq;
freq = get_cpufreq_base_freq(cpu);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/intel-speed-select-1.6/isst-display.c
new/intel-speed-select-1.10/isst-display.c
--- old/intel-speed-select-1.6/isst-display.c 2020-11-12 20:06:53.000000000
+0100
+++ new/intel-speed-select-1.10/isst-display.c 2021-07-18 20:27:25.000000000
+0200
@@ -25,10 +25,14 @@
index = snprintf(&str[curr_index],
str_len - curr_index, ",");
curr_index += index;
+ if (curr_index >= str_len)
+ break;
}
index = snprintf(&str[curr_index], str_len - curr_index, "%d",
i);
curr_index += index;
+ if (curr_index >= str_len)
+ break;
first = 0;
}
}
@@ -64,10 +68,14 @@
index = snprintf(&str[curr_index], str_len - curr_index, "%08x",
mask[i]);
curr_index += index;
+ if (curr_index >= str_len)
+ break;
if (i) {
strncat(&str[curr_index], ",", str_len - curr_index);
curr_index++;
}
+ if (curr_index >= str_len)
+ break;
}
free(mask);
@@ -185,7 +193,7 @@
int disp_level)
{
char header[256];
- char value[256];
+ char value[512];
snprintf(header, sizeof(header), "speed-select-base-freq-properties");
format_and_print(outf, disp_level, header, NULL);
@@ -349,7 +357,7 @@
struct isst_pkg_ctdp *pkg_dev)
{
char header[256];
- char value[256];
+ char value[512];
static int level;
int i;
@@ -438,7 +446,7 @@
if (ctdp_level->mem_freq) {
snprintf(header, sizeof(header), "mem-frequency(MHz)");
snprintf(value, sizeof(value), "%d",
- ctdp_level->mem_freq * DISP_FREQ_MULTIPLIER);
+ ctdp_level->mem_freq);
format_and_print(outf, level + 2, header, value);
}
@@ -763,3 +771,21 @@
if (!start)
format_and_print(outf, 0, NULL, NULL);
}
+
+void isst_trl_display_information(int cpu, FILE *outf, unsigned long long trl)
+{
+ char header[256];
+ char value[256];
+ int level;
+
+ level = print_package_info(cpu, outf);
+
+ snprintf(header, sizeof(header), "get-trl");
+ format_and_print(outf, level + 1, header, NULL);
+
+ snprintf(header, sizeof(header), "trl");
+ snprintf(value, sizeof(value), "0x%llx", trl);
+ format_and_print(outf, level + 2, header, value);
+
+ format_and_print(outf, level, NULL, NULL);
+}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/intel-speed-select-1.6/isst.h
new/intel-speed-select-1.10/isst.h
--- old/intel-speed-select-1.6/isst.h 2020-11-12 20:06:53.000000000 +0100
+++ new/intel-speed-select-1.10/isst.h 2021-07-18 20:27:25.000000000 +0200
@@ -228,6 +228,7 @@
int fact_bucket, int fact_avx,
struct isst_fact_info *fact_info);
extern int isst_set_trl(int cpu, unsigned long long trl);
+extern int isst_get_trl(int cpu, unsigned long long *trl);
extern int isst_set_trl_from_current_tdp(int cpu, unsigned long long trl);
extern int isst_get_config_tdp_lock_status(int cpu);
@@ -255,4 +256,8 @@
extern int get_cpufreq_base_freq(int cpu);
extern int isst_read_pm_config(int cpu, int *cp_state, int *cp_cap);
extern void isst_display_error_info_message(int error, char *msg, int
arg_valid, int arg);
+extern int is_skx_based_platform(void);
+extern int is_spr_platform(void);
+extern int is_icx_platform(void);
+extern void isst_trl_display_information(int cpu, FILE *outf, unsigned long
long trl);
#endif
++++++ turbostat-20.09.30.tar.bz2 -> turbostat-21.05.04.tar.bz2 ++++++
++++ 3398 lines of diff (skipped)
++++++ x86_energy_perf_policy-17.05.11.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/x86_energy_perf_policy-17.05.11/Makefile
new/x86_energy_perf_policy-17.05.11/Makefile
--- old/x86_energy_perf_policy-17.05.11/Makefile 2019-05-06
02:42:58.000000000 +0200
+++ new/x86_energy_perf_policy-17.05.11/Makefile 2021-07-18
20:27:25.000000000 +0200
@@ -9,8 +9,9 @@
endif
x86_energy_perf_policy : x86_energy_perf_policy.c
-override CFLAGS += -Wall
+override CFLAGS += -O2 -Wall -I../../../include
override CFLAGS +=
-DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
+override CFLAGS += -D_FORTIFY_SOURCE=2
%: %.c
@mkdir -p $(BUILD_OUTPUT)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/x86_energy_perf_policy-17.05.11/msr-index.h
new/x86_energy_perf_policy-17.05.11/msr-index.h
--- old/x86_energy_perf_policy-17.05.11/msr-index.h 2019-06-05
13:11:18.275908733 +0200
+++ new/x86_energy_perf_policy-17.05.11/msr-index.h 2021-07-18
21:27:00.462043252 +0200
@@ -2,6 +2,8 @@
#ifndef _ASM_X86_MSR_INDEX_H
#define _ASM_X86_MSR_INDEX_H
+#include <linux/bits.h>
+
/*
* CPU model specific register (MSR) numbers.
*
@@ -39,15 +41,19 @@
/* Intel MSRs. Some also available on other CPUs */
+#define MSR_TEST_CTRL 0x00000033
+#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
+#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT
BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
+
#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
-#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch
Restricted Speculation */
+#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch
Restricted Speculation */
#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect
Branch Predictor (STIBP) bit */
-#define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT)
/* STIBP mask */
+#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT)
/* STIBP mask */
#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass
Disable bit */
-#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /*
Speculative Store Bypass Disable */
+#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /*
Speculative Store Bypass Disable */
#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
-#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch
Prediction Barrier */
+#define PRED_CMD_IBPB BIT(0) /* Indirect Branch
Prediction Barrier */
#define MSR_PPIN_CTL 0x0000004e
#define MSR_PPIN 0x0000004f
@@ -59,6 +65,20 @@
#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
#define MSR_PLATFORM_INFO_CPUID_FAULT
BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
+#define MSR_IA32_UMWAIT_CONTROL 0xe1
+#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
+#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
+/*
+ * The time field is bit[31:2], but representing a 32bit value with
+ * bit[1:0] zero.
+ */
+#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
+
+/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
+#define MSR_IA32_CORE_CAPS 0x000000cf
+#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
+#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT
BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
+
#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
@@ -69,24 +89,49 @@
#define MSR_MTRRcap 0x000000fe
#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
-#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to
Meltdown */
-#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
-#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry
*/
-#define ARCH_CAP_SSB_NO (1 << 4) /*
- * Not susceptible to
Speculative Store Bypass
- * attack, so no Speculative
Store Bypass
- * control required.
- */
+#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown
*/
+#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
+#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
+#define ARCH_CAP_SSB_NO BIT(4) /*
+ * Not susceptible to
Speculative Store Bypass
+ * attack, so no Speculative
Store Bypass
+ * control required.
+ */
+#define ARCH_CAP_MDS_NO BIT(5) /*
+ * Not susceptible to
+ * Microarchitectural Data
+ * Sampling (MDS)
vulnerabilities.
+ */
+#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
+ * The processor is not
susceptible to a
+ * machine check error due to
modifying the
+ * code page size along with
either the
+ * physical address or cache
type
+ * without TLB invalidation.
+ */
+#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is
available. */
+#define ARCH_CAP_TAA_NO BIT(8) /*
+ * Not susceptible to
+ * TSX Async Abort (TAA)
vulnerabilities.
+ */
#define MSR_IA32_FLUSH_CMD 0x0000010b
-#define L1D_FLUSH (1 << 0) /*
- * Writeback and invalidate
the
- * L1 data cache.
- */
+#define L1D_FLUSH BIT(0) /*
+ * Writeback and invalidate the
+ * L1 data cache.
+ */
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
+#define MSR_IA32_TSX_CTRL 0x00000122
+#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
+#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
+
+/* SRBDS support */
+#define MSR_IA32_MCU_OPT_CTRL 0x00000123
+#define RNGDS_MITG_DIS BIT(0)
+
#define MSR_IA32_SYSENTER_CS 0x00000174
#define MSR_IA32_SYSENTER_ESP 0x00000175
#define MSR_IA32_SYSENTER_EIP 0x00000176
@@ -94,6 +139,7 @@
#define MSR_IA32_MCG_CAP 0x00000179
#define MSR_IA32_MCG_STATUS 0x0000017a
#define MSR_IA32_MCG_CTL 0x0000017b
+#define MSR_ERROR_CONTROL 0x0000017f
#define MSR_IA32_MCG_EXT_CTL 0x000004d0
#define MSR_OFFCORE_RSP_0 0x000001a6
@@ -104,6 +150,10 @@
#define MSR_LBR_SELECT 0x000001c8
#define MSR_LBR_TOS 0x000001c9
+
+#define MSR_IA32_POWER_CTL 0x000001fc
+#define MSR_IA32_POWER_CTL_BIT_EE 19
+
#define MSR_LBR_NHM_FROM 0x00000680
#define MSR_LBR_NHM_TO 0x000006c0
#define MSR_LBR_CORE_FROM 0x00000040
@@ -113,11 +163,31 @@
#define LBR_INFO_MISPRED BIT_ULL(63)
#define LBR_INFO_IN_TX BIT_ULL(62)
#define LBR_INFO_ABORT BIT_ULL(61)
+#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
#define LBR_INFO_CYCLES 0xffff
+#define LBR_INFO_BR_TYPE_OFFSET 56
+#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
+
+#define MSR_ARCH_LBR_CTL 0x000014ce
+#define ARCH_LBR_CTL_LBREN BIT(0)
+#define ARCH_LBR_CTL_CPL_OFFSET 1
+#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
+#define ARCH_LBR_CTL_STACK_OFFSET 3
+#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
+#define ARCH_LBR_CTL_FILTER_OFFSET 16
+#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
+#define MSR_ARCH_LBR_DEPTH 0x000014cf
+#define MSR_ARCH_LBR_FROM_0 0x00001500
+#define MSR_ARCH_LBR_TO_0 0x00001600
+#define MSR_ARCH_LBR_INFO_0 0x00001200
#define MSR_IA32_PEBS_ENABLE 0x000003f1
+#define MSR_PEBS_DATA_CFG 0x000003f2
#define MSR_IA32_DS_AREA 0x00000600
#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define PERF_CAP_METRICS_IDX 15
+#define PERF_CAP_PT_IDX 16
+
#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
#define MSR_IA32_RTIT_CTL 0x00000570
@@ -191,10 +261,14 @@
#define MSR_IA32_LASTINTFROMIP 0x000001dd
#define MSR_IA32_LASTINTTOIP 0x000001de
+#define MSR_IA32_PASID 0x00000d93
+#define MSR_IA32_PASID_VALID BIT_ULL(31)
+
/* DEBUGCTLMSR bits (others vary by model): */
#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch
recording */
#define DEBUGCTLMSR_BTF_SHIFT 1
#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on
branches */
+#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
#define DEBUGCTLMSR_TR (1UL << 6)
#define DEBUGCTLMSR_BTS (1UL << 7)
#define DEBUGCTLMSR_BTINT (1UL << 8)
@@ -207,8 +281,6 @@
#define MSR_PEBS_FRONTEND 0x000003f7
-#define MSR_IA32_POWER_CTL 0x000001fc
-
#define MSR_IA32_MC0_CTL 0x00000400
#define MSR_IA32_MC0_STATUS 0x00000401
#define MSR_IA32_MC0_ADDR 0x00000402
@@ -259,6 +331,10 @@
#define MSR_PP1_ENERGY_STATUS 0x00000641
#define MSR_PP1_POLICY 0x00000642
+#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
+#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
+#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
+
/* Config TDP MSRs */
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
@@ -358,15 +434,26 @@
/* Alternative perfctr range with full access. */
#define MSR_IA32_PMC0 0x000004c1
-/* AMD64 MSRs. Not complete. See the architecture manual for a more
- complete list. */
+/* Auto-reload via MSR instead of DS area */
+#define MSR_RELOAD_PMC0 0x000014c1
+#define MSR_RELOAD_FIXED_CTR0 0x00001309
+/*
+ * AMD64 MSRs. Not complete. See the architecture manual for a more
+ * complete list.
+ */
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_PATCH_LOADER 0xc0010020
+#define MSR_AMD_PERF_CTL 0xc0010062
+#define MSR_AMD_PERF_STATUS 0xc0010063
+#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
+#define MSR_AMD_PPIN_CTL 0xc00102f0
+#define MSR_AMD_PPIN 0xc00102f1
+#define MSR_AMD64_CPUID_FN_1 0xc0011004
#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
#define MSR_AMD64_BU_CFG2 0xc001102a
@@ -386,11 +473,16 @@
#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
#define MSR_AMD64_IBSCTL 0xc001103a
#define MSR_AMD64_IBSBRTARGET 0xc001103b
+#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
#define MSR_AMD64_IBSOPDATA4 0xc001103d
#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
+#define MSR_AMD64_SEV_ES_GHCB 0xc0010130
#define MSR_AMD64_SEV 0xc0010131
#define MSR_AMD64_SEV_ENABLED_BIT 0
+#define MSR_AMD64_SEV_ES_ENABLED_BIT 1
#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
+#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
@@ -406,6 +498,8 @@
#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
/* Fam 15h MSRs */
+#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
@@ -443,9 +537,9 @@
/* K8 MSRs */
#define MSR_K8_TOP_MEM1 0xc001001a
#define MSR_K8_TOP_MEM2 0xc001001d
-#define MSR_K8_SYSCFG 0xc0010010
-#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23
-#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
+#define MSR_AMD64_SYSCFG 0xc0010010
+#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
+#define MSR_AMD64_SYSCFG_MEM_ENCRYPT
BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
#define MSR_K8_INT_PENDING_MSG 0xc0010055
/* C1E active bits in int pending message */
#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
@@ -468,6 +562,8 @@
#define MSR_K7_HWCR 0xc0010015
#define MSR_K7_HWCR_SMMLOCK_BIT 0
#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
+#define MSR_K7_HWCR_IRPERF_EN_BIT 30
+#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
#define MSR_K7_FID_VID_CTL 0xc0010041
#define MSR_K7_FID_VID_STATUS 0xc0010042
@@ -514,7 +610,16 @@
#define MSR_IA32_EBL_CR_POWERON 0x0000002a
#define MSR_EBC_FREQUENCY_ID 0x0000002c
#define MSR_SMI_COUNT 0x00000034
-#define MSR_IA32_FEATURE_CONTROL 0x0000003a
+
+/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
+#define MSR_IA32_FEAT_CTL 0x0000003a
+#define FEAT_CTL_LOCKED BIT(0)
+#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
+#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
+#define FEAT_CTL_SGX_LC_ENABLED BIT(17)
+#define FEAT_CTL_SGX_ENABLED BIT(18)
+#define FEAT_CTL_LMCE_ENABLED BIT(20)
+
#define MSR_IA32_TSC_ADJUST 0x0000003b
#define MSR_IA32_BNDCFGS 0x00000d90
@@ -522,30 +627,26 @@
#define MSR_IA32_XSS 0x00000da0
-#define FEATURE_CONTROL_LOCKED (1<<0)
-#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
-#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
-#define FEATURE_CONTROL_LMCE (1<<20)
-
#define MSR_IA32_APICBASE 0x0000001b
#define MSR_IA32_APICBASE_BSP (1<<8)
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
-#define MSR_IA32_TSCDEADLINE 0x000006e0
-
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_UCODE_REV 0x0000008b
+/* Intel SGX Launch Enclave Public Key Hash MSRs */
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
+
#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
#define MSR_IA32_SMBASE 0x0000009e
#define MSR_IA32_PERF_STATUS 0x00000198
#define MSR_IA32_PERF_CTL 0x00000199
#define INTEL_PERF_CTL_MASK 0xffff
-#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
-#define MSR_AMD_PERF_STATUS 0xc0010063
-#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
@@ -671,6 +772,10 @@
#define MSR_TFA_RTM_FORCE_ABORT_BIT 0
#define MSR_TFA_RTM_FORCE_ABORT
BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
+#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
+#define MSR_TFA_TSX_CPUID_CLEAR
BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
+#define MSR_TFA_SDV_ENABLE_RTM_BIT 2
+#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
@@ -776,11 +881,22 @@
#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
+#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
+#define MSR_PERF_METRICS 0x00000329
+
+/* PERF_GLOBAL_OVF_CTL bits */
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL <<
MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL <<
MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL
<< MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
+
/* Geode defined MSRs */
#define MSR_GEODE_BUSCONT_CONF0 0x00001900
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.8
new/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.8
--- old/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.8
2019-05-06 02:42:58.000000000 +0200
+++ new/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.8
2021-07-18 20:27:25.000000000 +0200
@@ -40,7 +40,7 @@
Hardware P-States (HWP) are effectively an expansion of hardware
P-state control from the opportunistic turbo-mode P-state range
to include the entire range of available P-states.
-On Broadwell Xeon, the initial HWP implementation, EBP influenced HWP.
+On Broadwell Xeon, the initial HWP implementation, EPB influenced HWP.
That influence was removed in subsequent generations,
where it was moved to the
Energy_Performance_Preference (EPP) field in
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.c
new/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.c
--- old/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.c
2019-05-06 02:42:58.000000000 +0200
+++ new/x86_energy_perf_policy-17.05.11/x86_energy_perf_policy.c
2021-07-18 20:27:25.000000000 +0200
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* x86_energy_perf_policy -- set the energy versus performance
* policy preference bias on recent X86 processors.
@@ -5,8 +6,6 @@
/*
* Copyright (c) 2010 - 2017 Intel Corporation.
* Len Brown <len.br...@intel.com>
- *
- * This program is released under GPL v2
*/
#define _GNU_SOURCE
@@ -92,6 +91,9 @@
unsigned int bdx_highest_ratio;
+#define PATH_TO_CPU "/sys/devices/system/cpu/"
+#define SYSFS_PATH_MAX 255
+
/*
* maintain compatibility with original implementation, but don't document it:
*/
@@ -546,7 +548,7 @@
progname = argv[0];
- while ((opt = getopt_long_only(argc, argv, "+a:c:dD:E:e:f:m:M:rt:u:vw",
+ while ((opt = getopt_long_only(argc, argv, "+a:c:dD:E:e:f:m:M:rt:u:vw:",
long_options, &option_index)) != -1) {
switch (opt) {
case 'a':
@@ -623,6 +625,57 @@
}
}
+/*
+ * Open a file, and exit on failure
+ */
+FILE *fopen_or_die(const char *path, const char *mode)
+{
+ FILE *filep = fopen(path, "r");
+
+ if (!filep)
+ err(1, "%s: open failed", path);
+ return filep;
+}
+
+void err_on_hypervisor(void)
+{
+ FILE *cpuinfo;
+ char *flags, *hypervisor;
+ char *buffer;
+
+ /* On VMs /proc/cpuinfo contains a "flags" entry for hypervisor */
+ cpuinfo = fopen_or_die("/proc/cpuinfo", "ro");
+
+ buffer = malloc(4096);
+ if (!buffer) {
+ fclose(cpuinfo);
+ err(-ENOMEM, "buffer malloc fail");
+ }
+
+ if (!fread(buffer, 1024, 1, cpuinfo)) {
+ fclose(cpuinfo);
+ free(buffer);
+ err(1, "Reading /proc/cpuinfo failed");
+ }
+
+ flags = strstr(buffer, "flags");
+ rewind(cpuinfo);
+ fseek(cpuinfo, flags - buffer, SEEK_SET);
+ if (!fgets(buffer, 4096, cpuinfo)) {
+ fclose(cpuinfo);
+ free(buffer);
+ err(1, "Reading /proc/cpuinfo failed");
+ }
+ fclose(cpuinfo);
+
+ hypervisor = strstr(buffer, "hypervisor");
+
+ free(buffer);
+
+ if (hypervisor)
+ err(-1,
+ "not supported on this virtual machine");
+}
int get_msr(int cpu, int offset, unsigned long long *msr)
{
@@ -636,8 +689,10 @@
err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr,
or run as root", pathname);
retval = pread(fd, msr, sizeof(*msr), offset);
- if (retval != sizeof(*msr))
+ if (retval != sizeof(*msr)) {
+ err_on_hypervisor();
err(-1, "%s offset 0x%llx read failed", pathname, (unsigned
long long)offset);
+ }
if (debug > 1)
fprintf(stderr, "get_msr(cpu%d, 0x%X, 0x%llX)\n", cpu, offset,
*msr);
@@ -669,6 +724,48 @@
return 0;
}
+static unsigned int read_sysfs(const char *path, char *buf, size_t buflen)
+{
+ ssize_t numread;
+ int fd;
+
+ fd = open(path, O_RDONLY);
+ if (fd == -1)
+ return 0;
+
+ numread = read(fd, buf, buflen - 1);
+ if (numread < 1) {
+ close(fd);
+ return 0;
+ }
+
+ buf[numread] = '\0';
+ close(fd);
+
+ return (unsigned int) numread;
+}
+
+static unsigned int write_sysfs(const char *path, char *buf, size_t buflen)
+{
+ ssize_t numwritten;
+ int fd;
+
+ fd = open(path, O_WRONLY);
+ if (fd == -1)
+ return 0;
+
+ numwritten = write(fd, buf, buflen - 1);
+ if (numwritten < 1) {
+ perror("write failed\n");
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return (unsigned int) numwritten;
+}
+
void print_hwp_cap(int cpu, struct msr_hwp_cap *cap, char *str)
{
if (cpu != -1)
@@ -746,17 +843,61 @@
put_msr(cpu, msr_offset, msr);
}
+static int get_epb(int cpu)
+{
+ char path[SYSFS_PATH_MAX];
+ char linebuf[3];
+ char *endp;
+ long val;
+
+ if (!has_epb)
+ return -1;
+
+ snprintf(path, sizeof(path), PATH_TO_CPU
"cpu%u/power/energy_perf_bias", cpu);
+
+ if (!read_sysfs(path, linebuf, 3))
+ return -1;
+
+ val = strtol(linebuf, &endp, 0);
+ if (endp == linebuf || errno == ERANGE)
+ return -1;
+
+ return (int)val;
+}
+
+static int set_epb(int cpu, int val)
+{
+ char path[SYSFS_PATH_MAX];
+ char linebuf[3];
+ char *endp;
+ int ret;
+
+ if (!has_epb)
+ return -1;
+
+ snprintf(path, sizeof(path), PATH_TO_CPU
"cpu%u/power/energy_perf_bias", cpu);
+ snprintf(linebuf, sizeof(linebuf), "%d", val);
+
+ ret = write_sysfs(path, linebuf, 3);
+ if (ret <= 0)
+ return -1;
+
+ val = strtol(linebuf, &endp, 0);
+ if (endp == linebuf || errno == ERANGE)
+ return -1;
+
+ return (int)val;
+}
+
int print_cpu_msrs(int cpu)
{
- unsigned long long msr;
struct msr_hwp_request req;
struct msr_hwp_cap cap;
+ int epb;
- if (has_epb) {
- get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
-
- printf("cpu%d: EPB %u\n", cpu, (unsigned int) msr);
- }
+ epb = get_epb(cpu);
+ if (epb >= 0)
+ printf("cpu%d: EPB %u\n", cpu, (unsigned int) epb);
if (!has_hwp)
return 0;
@@ -1039,15 +1180,15 @@
int update_cpu_msrs(int cpu)
{
unsigned long long msr;
-
+ int epb;
if (update_epb) {
- get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
- put_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, new_epb);
+ epb = get_epb(cpu);
+ set_epb(cpu, new_epb);
if (verbose)
printf("cpu%d: ENERGY_PERF_BIAS old: %d new: %d\n",
- cpu, (unsigned int) msr, (unsigned int)
new_epb);
+ cpu, epb, (unsigned int) new_epb);
}
if (update_turbo) {
@@ -1087,18 +1228,6 @@
return 0;
}
-/*
- * Open a file, and exit on failure
- */
-FILE *fopen_or_die(const char *path, const char *mode)
-{
- FILE *filep = fopen(path, "r");
-
- if (!filep)
- err(1, "%s: open failed", path);
- return filep;
-}
-
unsigned int get_pkg_num(int cpu)
{
FILE *fp;
@@ -1260,6 +1389,15 @@
if (system("/sbin/modprobe msr > /dev/null 2>&1"))
err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
}
+
+static void get_cpuid_or_exit(unsigned int leaf,
+ unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ if (!__get_cpuid(leaf, eax, ebx, ecx, edx))
+ errx(1, "Processor not supported\n");
+}
+
/*
* early_cpuid()
* initialize turbo_is_enabled, has_hwp, has_epb
@@ -1267,15 +1405,10 @@
*/
void early_cpuid(void)
{
- unsigned int eax, ebx, ecx, edx, max_level;
+ unsigned int eax, ebx, ecx, edx;
unsigned int fms, family, model;
- __get_cpuid(0, &max_level, &ebx, &ecx, &edx);
-
- if (max_level < 6)
- errx(1, "Processor not supported\n");
-
- __get_cpuid(1, &fms, &ebx, &ecx, &edx);
+ get_cpuid_or_exit(1, &fms, &ebx, &ecx, &edx);
family = (fms >> 8) & 0xf;
model = (fms >> 4) & 0xf;
if (family == 6 || family == 0xf)
@@ -1289,7 +1422,7 @@
bdx_highest_ratio = msr & 0xFF;
}
- __get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
+ get_cpuid_or_exit(0x6, &eax, &ebx, &ecx, &edx);
turbo_is_enabled = (eax >> 1) & 1;
has_hwp = (eax >> 7) & 1;
has_epb = (ecx >> 3) & 1;
@@ -1307,7 +1440,7 @@
eax = ebx = ecx = edx = 0;
- __get_cpuid(0, &max_level, &ebx, &ecx, &edx);
+ get_cpuid_or_exit(0, &max_level, &ebx, &ecx, &edx);
if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
genuine_intel = 1;
@@ -1316,7 +1449,7 @@
fprintf(stderr, "CPUID(0): %.4s%.4s%.4s ",
(char *)&ebx, (char *)&edx, (char *)&ecx);
- __get_cpuid(1, &fms, &ebx, &ecx, &edx);
+ get_cpuid_or_exit(1, &fms, &ebx, &ecx, &edx);
family = (fms >> 8) & 0xf;
model = (fms >> 4) & 0xf;
stepping = fms & 0xf;
@@ -1341,7 +1474,7 @@
errx(1, "CPUID: no MSR");
- __get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
+ get_cpuid_or_exit(0x6, &eax, &ebx, &ecx, &edx);
/* turbo_is_enabled already set */
/* has_hwp already set */
has_hwp_notify = eax & (1 << 8);
++++++ x86_perf_makefile_fix_asm_header.patch ++++++
--- /var/tmp/diff_new_pack.BVtrJL/_old 2021-07-20 15:40:06.801542053 +0200
+++ /var/tmp/diff_new_pack.BVtrJL/_new 2021-07-20 15:40:06.801542053 +0200
@@ -1,13 +1,15 @@
-Index: x86_energy_perf_policy-17.05.11/Makefile
-===================================================================
---- x86_energy_perf_policy-17.05.11.orig/Makefile 2019-04-08
16:05:22.534455032 +0200
-+++ x86_energy_perf_policy-17.05.11/Makefile 2019-04-08 16:05:52.306456636
+0200
-@@ -10,7 +10,7 @@ endif
+---
+ Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Makefile
++++ b/Makefile
+@@ -10,7 +10,7 @@
x86_energy_perf_policy : x86_energy_perf_policy.c
- override CFLAGS += -Wall
+ override CFLAGS += -O2 -Wall -I../../../include
-override CFLAGS +=
-DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
+override CFLAGS += -DMSRHEADER='"msr-index.h"'
+ override CFLAGS += -D_FORTIFY_SOURCE=2
%: %.c
- @mkdir -p $(BUILD_OUTPUT)
