Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package rshim for openSUSE:Factory checked
in at 2022-09-19 16:04:19
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/rshim (Old)
and /work/SRC/openSUSE:Factory/.rshim.new.2083 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "rshim"
Mon Sep 19 16:04:19 2022 rev:9 rq:1004722 version:2.0.6.13.7
Changes:
--------
--- /work/SRC/openSUSE:Factory/rshim/rshim.changes 2022-07-21
11:35:10.627053251 +0200
+++ /work/SRC/openSUSE:Factory/.rshim.new.2083/rshim.changes 2022-09-19
16:04:28.406332551 +0200
@@ -1,0 +2,12 @@
+Thu Sep 15 08:56:34 UTC 2022 - Matthias Brugger <mbrug...@suse.com>
+
+- update to 2.0.6.13.7
+ * make use of rshim with several devices more efficient
+ * support 32 bit CR space possible on BF3 USB access
+ * support more transfer sizes
+ * add new device ID for BF3
+ * allow to en/disable VFIO/UIO support via rshim.conf
+ * make restart of rshim process more robust fixing potential race
+ * set default boot timeout to 150 seconds
+
+-------------------------------------------------------------------
Old:
----
rshim-2.0.6.11.5.tar
New:
----
rshim-2.0.6.13.7.tar
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ rshim.spec ++++++
--- /var/tmp/diff_new_pack.Yxd1oy/_old 2022-09-19 16:04:28.842333716 +0200
+++ /var/tmp/diff_new_pack.Yxd1oy/_new 2022-09-19 16:04:28.846333727 +0200
@@ -18,7 +18,7 @@
Name: rshim
-Version: 2.0.6.11.5
+Version: 2.0.6.13.7
Release: 0
Summary: User-space driver for Mellanox BlueField SoC
License: GPL-2.0-only
++++++ rshim-2.0.6.11.5.tar -> rshim-2.0.6.13.7.tar ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/debian/changelog
new/rshim-2.0.6.13.7/debian/changelog
--- old/rshim-2.0.6.11.5/debian/changelog 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/debian/changelog 2022-09-12 18:05:02.000000000
+0200
@@ -1,3 +1,10 @@
+rshim (2.0.6-13) UNRELEASED; urgency=low
+
+ * BF3: Support 32-bit CR-space access via USB
+ * Avoid kernel-modules-extra dependency on ctyunos
+
+ -- Liming Sun <limi...@nvidia.com> Sun, 17 Jul 2022 17:01:15 -0400
+
rshim (2.0.6-12) UNRELEASED; urgency=low
* Optimize the rshim_work_fd
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/etc/rshim.conf
new/rshim-2.0.6.13.7/etc/rshim.conf
--- old/rshim-2.0.6.11.5/etc/rshim.conf 2022-07-13 19:15:52.000000000 +0200
+++ new/rshim-2.0.6.13.7/etc/rshim.conf 2022-09-12 18:05:02.000000000 +0200
@@ -6,11 +6,13 @@
# Default configuration for a rshim device
#
#DISPLAY_LEVEL 0
-#BOOT_TIMEOUT 100
+#BOOT_TIMEOUT 150
#DROP_MODE 0
#USB_RESET_DELAY 3
#PCIE_RESET_DELAY 10
#PCIE_INTR_POLL_INTERVAL 10
+#PCIE_HAS_VFIO 1
+#PCIE_HAS_UIO 1
#
# Static mapping of rshim name and device.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/rhel/rshim.spec.in
new/rshim-2.0.6.13.7/rhel/rshim.spec.in
--- old/rshim-2.0.6.11.5/rhel/rshim.spec.in 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/rhel/rshim.spec.in 2022-09-12 18:05:02.000000000
+0200
@@ -4,7 +4,7 @@
Name: rshim
Version: @VERSION@
-Release: 12%{?dist}
+Release: 13%{?dist}
Summary: User-space driver for Mellanox BlueField SoC
License: GPLv2
@@ -54,6 +54,10 @@
%{_mandir}/man8/rshim.8.gz
%changelog
+* Sun Jul 17 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-13
+- BF3: Support 32-bit CR-space access via USB
+- Avoid kernel-modules-extra dependency on ctyunos
+
* Thu Jun 16 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-12
- Optimize the rshim_work_fd
- Detect new USB/rshim hot plugin
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/rshim.spec.in
new/rshim-2.0.6.13.7/rshim.spec.in
--- old/rshim-2.0.6.11.5/rshim.spec.in 2022-07-13 19:15:52.000000000 +0200
+++ new/rshim-2.0.6.13.7/rshim.spec.in 2022-09-12 18:05:02.000000000 +0200
@@ -4,7 +4,7 @@
Name: rshim
Version: @VERSION@
-Release: 12%{?dist}
+Release: 13%{?dist}
Summary: User-space driver for Mellanox BlueField SoC
License: GPLv2
@@ -95,6 +95,10 @@
%{_mandir}/man8/bfb-install.8.gz
%changelog
+* Sun Jul 17 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-13
+- BF3: Support 32-bit CR-space access via USB
+- Avoid kernel-modules-extra dependency on ctyunos
+
* Thu Jun 16 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-12
- Optimize the rshim_work_fd
- Detect new USB/rshim hot plugin
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim.c
new/rshim-2.0.6.13.7/src/rshim.c
--- old/rshim-2.0.6.11.5/src/rshim.c 2022-07-13 19:15:52.000000000 +0200
+++ new/rshim-2.0.6.13.7/src/rshim.c 2022-09-12 18:05:02.000000000 +0200
@@ -23,7 +23,7 @@
#include "rshim.h"
-#define REVISION "12"
+#define REVISION "13"
/* Maximum number of devices supported (currently it's limited to 64). */
#define RSHIM_MAX_DEV 64
@@ -184,10 +184,13 @@
/* Default configuration file. */
const char *rshim_cfg_file = DEFAULT_RSHIM_CONFIG_FILE;
static int rshim_display_level = 0;
-static int rshim_boot_timeout = 100;
+static int rshim_boot_timeout = 150;
int rshim_drop_mode = -1;
int rshim_usb_reset_delay = 5;
int rshim_pcie_reset_delay = 10;
+int rshim_pcie_enable_vfio = 1;
+int rshim_pcie_enable_uio = 1;
+int rshim_pcie_intr_poll_interval = 10; /* Interrupt polling in milliseconds
*/
/* Array of devices and device names. */
rshim_backend_t *rshim_devs[RSHIM_MAX_DEV];
@@ -316,14 +319,14 @@
while (total < count) {
if (avail == 0) {
reg = 0;
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_sts, ®);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_sts, ®,
RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(reg))
break;
avail = reg & RSH_TM_TILE_TO_HOST_STS__COUNT_MASK;
if (avail == 0)
break;
}
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_data, ®);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_tth_data, ®,
RSHIM_REG_SIZE_8B);
if (rc < 0)
break;
@@ -400,17 +403,19 @@
time(&t0);
while (avail <= 0) {
/* Calculate available space in words. */
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, size_addr, ®);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, size_addr, ®,
RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(reg)) {
- RSHIM_ERR("read_rshim error %d\n", rc);
- break;
+ RSHIM_ERR("rshim%d read_rshim error addr=0x%x, reg=0x%lx, rc=%d\n",
+ bd->index, size_addr, (long unsigned int)reg, rc);
+ usleep(10000);
+ return count;
}
avail = max_size - (int)(reg & size_mask) - RSHIM_FIFO_SPACE_RESERV;
if (avail > 0)
break;
if (devtype == RSH_DEV_TYPE_BOOT)
- return (byte_cnt > count) ? count : byte_cnt;
+ goto done;
time(&t1);
if (difftime(t1, t0) > 3) {
@@ -427,7 +432,7 @@
* receiving side should call le64toh() to convert it back.
*/
reg = htole64(reg);
- rc = bd->write_rshim(bd, RSHIM_CHANNEL, data_addr, reg);
+ rc = bd->write_rshim(bd, RSHIM_CHANNEL, data_addr, reg, RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("write_rshim error %d\n", rc);
break;
@@ -440,6 +445,7 @@
}
/* Return number shouldn't count the padded bytes. */
+done:
return (byte_cnt > count) ? count : byte_cnt;
}
@@ -541,7 +547,7 @@
uint64_t count;
while (retries--) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &count);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &count,
RSHIM_REG_SIZE_8B);
if (rc)
return rc;
if (count != resp_count)
@@ -556,19 +562,19 @@
{
uint64_t reg, resp_count;
- bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, ®);
+ bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, ®,
RSHIM_REG_SIZE_8B);
reg |= 0x1ULL << bd->regs->device_mstr_priv_lvl_shift;
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, reg);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, reg,
RSHIM_REG_SIZE_8B);
- bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &resp_count);
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_data_first_word, data);
+ bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &resp_count,
RSHIM_REG_SIZE_8B);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_data_first_word, data,
RSHIM_REG_SIZE_8B);
reg = (((uint64_t)pa & RSH_MEM_ACC_CTL__ADDRESS_RMASK) <<
RSH_MEM_ACC_CTL__ADDRESS_SHIFT) |
(((uint64_t)size & RSH_MEM_ACC_CTL__SIZE_RMASK) <<
RSH_MEM_ACC_CTL__SIZE_SHIFT) |
(1ULL << RSH_MEM_ACC_CTL__WRITE_SHIFT) |
(1ULL << RSH_MEM_ACC_CTL__SEND_SHIFT);
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_ctl, reg);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_ctl, reg,
RSHIM_REG_SIZE_8B);
return rshim_reg_indirect_wait(bd, resp_count);
}
@@ -577,23 +583,23 @@
{
uint64_t reg, resp_count;
- bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, ®);
+ bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, ®,
RSHIM_REG_SIZE_8B);
reg |= 0x1ULL << bd->regs->device_mstr_priv_lvl_shift;
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, reg);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->device_mstr_priv_lvl, reg,
RSHIM_REG_SIZE_8B);
- bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &resp_count);
+ bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_rsp_cnt, &resp_count,
RSHIM_REG_SIZE_8B);
reg = (((uint64_t)pa & RSH_MEM_ACC_CTL__ADDRESS_RMASK) <<
RSH_MEM_ACC_CTL__ADDRESS_SHIFT) |
(((uint64_t)size & RSH_MEM_ACC_CTL__SIZE_RMASK) <<
RSH_MEM_ACC_CTL__SIZE_SHIFT) |
(1ULL << RSH_MEM_ACC_CTL__SEND_SHIFT);
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_ctl, reg);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_ctl, reg,
RSHIM_REG_SIZE_8B);
if (rshim_reg_indirect_wait(bd, resp_count))
return -1;
- bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_data_first_word, ®);
+ bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->mem_acc_data_first_word, ®,
RSHIM_REG_SIZE_8B);
*data = reg;
return 0;
@@ -647,7 +653,7 @@
uint8_t shift;
int rc;
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control, ®);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control, ®,
RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("failed to read rshim reset control error %d\n", rc);
return rc;
@@ -666,7 +672,7 @@
* in theory this should not impact the behavior of the RShim
* driver.
*/
- rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control, reg);
+ rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control, reg,
RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("failed to write rshim reset control error %d\n", rc);
return rc;
@@ -723,7 +729,7 @@
/* Set RShim (external) boot mode. */
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control,
- RSH_BOOT_CONTROL__BOOT_MODE_VAL_NONE);
+ RSH_BOOT_CONTROL__BOOT_MODE_VAL_NONE,
RSHIM_REG_SIZE_8B);
if (rc) {
RSHIM_ERR("boot_open: error %d writing boot control\n", rc);
bd->is_booting = 0;
@@ -738,7 +744,7 @@
* the BlueField SoC so far.
*/
bd->write_rshim(bd, RSH_MMIO_ADDRESS_SPACE__CHANNEL_VAL_WDOG1,
- bd->regs->arm_wdg_control_wcs, 0);
+ bd->regs->arm_wdg_control_wcs, 0, RSHIM_REG_SIZE_8B);
if (bd->skip_boot_reset)
goto boot_open_done;
@@ -879,7 +885,8 @@
/* Restore the boot mode register. */
rc = bd->write_rshim(bd, RSHIM_CHANNEL,
bd->regs->boot_control,
- RSH_BOOT_CONTROL__BOOT_MODE_VAL_EMMC);
+ RSH_BOOT_CONTROL__BOOT_MODE_VAL_EMMC,
+ RSHIM_REG_SIZE_8B);
if (rc)
RSHIM_ERR("couldn't set boot_control, err %d\n", rc);
@@ -888,7 +895,7 @@
memset((uint8_t *)&bd->boot_rem_data + bd->boot_rem_cnt, 0,
sizeof(uint64_t) - bd->boot_rem_cnt);
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_fifo_data,
- bd->boot_rem_data);
+ bd->boot_rem_data, RSHIM_REG_SIZE_8B);
}
bd->is_boot_open = 0;
bd->boot_rem_cnt = 0;
@@ -926,9 +933,10 @@
max_size = RSH_TM_FIFO_SIZE;
/* Calculate available size. */
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_htt_sts, &word);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_htt_sts, &word,
RSHIM_REG_SIZE_8B);
if (rc < 0 || RSHIM_BAD_CTRL_REG(word)) {
- RSHIM_ERR("read_rshim error %d\n", rc);
+ RSHIM_ERR("rshim%d read_rshim error %d\n", bd->index, rc);
+ usleep(10000);
return rc;
}
avail = max_size - (int)(word & RSH_TM_HOST_TO_TILE_STS__COUNT_MASK) -
@@ -951,7 +959,7 @@
for (i = 0; i < avail; i++) {
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->tm_htt_data,
- hdr.data);
+ hdr.data, RSHIM_REG_SIZE_8B);
if (rc)
return rc;
}
@@ -1630,7 +1638,7 @@
if (bd->keepalive && bd->has_rshim) {
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1,
- RSHIM_KEEPALIVE_MAGIC_NUM);
+ RSHIM_KEEPALIVE_MAGIC_NUM, RSHIM_REG_SIZE_8B);
bd->keepalive = 0;
}
@@ -2072,7 +2080,7 @@
return;
/* Check boot mode 0, which supposes to be set externally. */
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control, &value);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control, &value,
RSHIM_REG_SIZE_8B);
if (rc || value != RSH_BOOT_CONTROL__BOOT_MODE_VAL_NONE)
return;
@@ -2086,17 +2094,18 @@
* If boot mode is 0 after hard-reset, we update the boot mode and
* initiate sw reset so the chip could boot up.
*/
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->uptime_por, &uptime_hw);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->uptime_por, &uptime_hw,
RSHIM_REG_SIZE_8B);
if (rc)
return;
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->uptime, &uptime_sw);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->uptime, &uptime_sw,
RSHIM_REG_SIZE_8B);
if (rc)
return;
if (uptime_sw - uptime_hw < 1000000000ULL) {
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control,
- RSH_BOOT_CONTROL__BOOT_MODE_VAL_EMMC);
+ RSH_BOOT_CONTROL__BOOT_MODE_VAL_EMMC,
+ RSHIM_REG_SIZE_8B);
if (!rc) {
/* SW reset. */
rc = rshim_reset_control(bd);
@@ -2195,7 +2204,7 @@
* rshim device.
*/
for (i = 0; i < 10; i++) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->fabric_dim, &value);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->fabric_dim, &value,
RSHIM_REG_SIZE_8B);
if (!rc && value && !RSHIM_BAD_CTRL_REG(value))
break;
usleep(100000);
@@ -2217,14 +2226,15 @@
* since it's not reliable when doing reset.
*/
bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->reset_control,
- RSH_RESET_CONTROL__RESET_CHIP_VAL_KEY);
+ RSH_RESET_CONTROL__RESET_CHIP_VAL_KEY,
+ RSHIM_REG_SIZE_8B);
sleep(1);
rshim_bf2_a0_wa(bd);
}
}
/* Write value 0 to RSH_SCRATCHPAD1. */
- rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, 0);
+ rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, 0,
RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("failed to write rshim rc=%d\n", rc);
return -ENODEV;
@@ -2237,7 +2247,7 @@
continue;
pthread_mutex_lock(&other_bd->mutex);
other_bd->write_rshim(other_bd, RSHIM_CHANNEL, bd->regs->scratchpad1,
- RSHIM_KEEPALIVE_MAGIC_NUM);
+ RSHIM_KEEPALIVE_MAGIC_NUM, RSHIM_REG_SIZE_8B);
pthread_mutex_unlock(&other_bd->mutex);
}
@@ -2248,7 +2258,7 @@
*/
value = 0;
for (i = 0; i < 10; i++) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, &value);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, &value,
RSHIM_REG_SIZE_8B);
if (!rc && value == RSHIM_KEEPALIVE_MAGIC_NUM) {
RSHIM_INFO("another backend already attached\n");
@@ -2259,7 +2269,7 @@
}
/* One more read to make sure it's ready. */
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, &value);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, &value,
RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("access_check: failed to read rshim\n");
return -ENODEV;
@@ -2718,15 +2728,21 @@
} else if (!strcmp(key, "DROP_MODE")) {
rshim_drop_mode = (atoi(value) > 0) ? 1 : 0;
continue;
- } else if (!strcmp(key, "PCIE_RESET_DELAY")) {
- rshim_pcie_reset_delay = atoi(value);
- continue;
} else if (!strcmp(key, "USB_RESET_DELAY")) {
rshim_usb_reset_delay = atoi(value);
continue;
+ } else if (!strcmp(key, "PCIE_RESET_DELAY")) {
+ rshim_pcie_reset_delay = atoi(value);
+ continue;
} else if (!strcmp(key, "PCIE_INTR_POLL_INTERVAL")) {
rshim_pcie_intr_poll_interval = atoi(value);
continue;
+ } else if (!strcmp(key, "PCIE_HAS_VFIO")) {
+ rshim_pcie_enable_vfio = atoi(value);
+ continue;
+ } else if (!strcmp(key, "PCIE_HAS_UIO")) {
+ rshim_pcie_enable_uio = atoi(value);
+ continue;
}
if (strncmp(key, "rshim", 5) && strcmp(key, "none"))
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim.h
new/rshim-2.0.6.13.7/src/rshim.h
--- old/rshim-2.0.6.11.5/src/rshim.h 2022-07-13 19:15:52.000000000 +0200
+++ new/rshim-2.0.6.13.7/src/rshim.h 2022-09-12 18:05:02.000000000 +0200
@@ -43,6 +43,8 @@
extern int rshim_usb_reset_delay;
extern int rshim_pcie_reset_delay;
extern int rshim_pcie_intr_poll_interval;
+extern int rshim_pcie_enable_vfio;
+extern int rshim_pcie_enable_uio;
#ifndef offsetof
#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER)
@@ -411,13 +413,13 @@
/* API to destroy the backend. */
void (*destroy)(rshim_backend_t *bd);
- /* API to read 8 bytes from RShim. */
+ /* API to read <size> bytes from RShim. */
int (*read_rshim)(rshim_backend_t *bd, int chan, int addr,
- uint64_t *value);
+ uint64_t *value, int size);
- /* API to write 8 bytes to RShim. */
+ /* API to write <size> bytes to RShim. */
int (*write_rshim)(rshim_backend_t *bd, int chan, int addr,
- uint64_t value);
+ uint64_t value, int size);
/* API to enable the device. */
int (*enable_device)(rshim_backend_t *bd, bool enable);
@@ -426,6 +428,9 @@
const struct rshim_regs *regs;
};
+#define RSHIM_REG_SIZE_4B 4
+#define RSHIM_REG_SIZE_8B 8
+
struct rshim_regs {
uint32_t boot_fifo_data;
uint32_t boot_fifo_count;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim_fuse.c
new/rshim-2.0.6.13.7/src/rshim_fuse.c
--- old/rshim-2.0.6.11.5/src/rshim_fuse.c 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/src/rshim_fuse.c 2022-09-12 18:05:02.000000000
+0200
@@ -643,7 +643,7 @@
pthread_mutex_lock(&bd->mutex);
/* Boot mode. */
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control, &value);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control, &value,
RSHIM_REG_SIZE_8B);
if (rc) {
pthread_mutex_unlock(&bd->mutex);
RSHIM_ERR("couldn't read rshim register\n");
@@ -865,7 +865,8 @@
pthread_mutex_lock(&bd->mutex);
rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control,
- value & RSH_BOOT_CONTROL__BOOT_MODE_MASK);
+ value & RSH_BOOT_CONTROL__BOOT_MODE_MASK,
+ RSHIM_REG_SIZE_8B);
pthread_mutex_unlock(&bd->mutex);
} else if (strcmp(key, "SW_RESET") == 0) {
if (sscanf(p, "%x", &value) != 1)
@@ -1004,9 +1005,20 @@
uint64_t data;
} __attribute__((packed)) rshim_ioctl_msg;
+/* ioctl message header for Mustang. Unlike BF1 and BF2, Mustang
+ * HW enables different USB transfer sizes: 1B, 2B, 4B and 8B.
+ */
+typedef struct {
+ uint32_t addr;
+ uint64_t data;
+ uint8_t data_size;
+} __attribute__((packed)) rshim_ioctl_msg2;
+
enum {
RSHIM_IOC_READ = _IOWR('R', 0, rshim_ioctl_msg),
RSHIM_IOC_WRITE = _IOWR('R', 1, rshim_ioctl_msg),
+ RSHIM_IOC_READ2 = _IOWR('R', 0, rshim_ioctl_msg2),
+ RSHIM_IOC_WRITE2 = _IOWR('R', 1, rshim_ioctl_msg2),
};
#ifdef __linux__
@@ -1017,8 +1029,10 @@
{
rshim_backend_t *bd = fuse_req_userdata(req);
rshim_ioctl_msg msg;
+ rshim_ioctl_msg2 msg2;
struct iovec iov;
uint64_t data = 0;
+ uint16_t chan, offset;
int rc = 0;
if (!bd) {
@@ -1049,19 +1063,25 @@
memcpy(&msg, in_buf, sizeof(msg));
+ /*
+ * Get channel and offset from the 32-bit address.
+ * For BlueField-3 USB, it also supports passing the linear CR-space
+ * address where upper 16-bit is saved in 'chan' and lower 16-bit is
+ * saved in 'offset'.
+ */
+ chan = msg.addr >> 16;
+ offset = msg.addr & 0xFFFF;
+ if (bd->ver_id <= RSHIM_BLUEFIELD_2 || strncmp(bd->dev_name, "usb", 3)) {
+ chan &= 0xF;
+ }
+
if (cmd == RSHIM_IOC_WRITE) {
pthread_mutex_lock(&bd->mutex);
- rc = bd->write_rshim(bd,
- (msg.addr >> 16) & 0xF, /* channel # */
- msg.addr & 0xFFFF, /* addr */
- msg.data);
+ rc = bd->write_rshim(bd, chan, offset, msg.data, RSHIM_REG_SIZE_8B);
pthread_mutex_unlock(&bd->mutex);
} else {
pthread_mutex_lock(&bd->mutex);
- rc = bd->read_rshim(bd,
- (msg.addr >> 16) & 0xF, /* channel # */
- msg.addr & 0xFFFF, /* addr */
- &data);
+ rc = bd->read_rshim(bd, chan, offset, &data, RSHIM_REG_SIZE_8B);
msg.data = data;
pthread_mutex_unlock(&bd->mutex);
}
@@ -1072,6 +1092,57 @@
fuse_reply_err(req, -rc);
break;
+ case RSHIM_IOC_READ2:
+ case RSHIM_IOC_WRITE2:
+ iov.iov_base = arg;
+ iov.iov_len = sizeof(msg2);
+
+ if (!in_bufsz) {
+ fuse_reply_ioctl_retry(req, &iov, 1, NULL, 0);
+ return;
+ }
+
+ if (in_bufsz != sizeof(msg2)) {
+ fuse_reply_err(req, EINVAL);
+ return;
+ }
+
+ if (!out_bufsz) {
+ fuse_reply_ioctl_retry(req, &iov, 1, &iov, 1);
+ return;
+ }
+
+ memcpy(&msg2, in_buf, sizeof(msg2));
+
+ /*
+ * Get channel and offset from the 32-bit address.
+ * For BlueField-3 USB, it also supports passing the linear CR-space
+ * address where upper 16-bit is saved in 'chan' and lower 16-bit is
+ * saved in 'offset'.
+ */
+ chan = msg2.addr >> 16;
+ offset = msg2.addr & 0xFFFF;
+ if (bd->ver_id <= RSHIM_BLUEFIELD_2 || strncmp(bd->dev_name, "usb", 3)) {
+ chan &= 0xF;
+ }
+
+ if (cmd == RSHIM_IOC_WRITE2) {
+ pthread_mutex_lock(&bd->mutex);
+ rc = bd->write_rshim(bd, chan, offset, msg2.data, msg2.data_size);
+ pthread_mutex_unlock(&bd->mutex);
+ } else {
+ pthread_mutex_lock(&bd->mutex);
+ rc = bd->read_rshim(bd, chan, offset, &data, msg2.data_size);
+ msg2.data = data;
+ pthread_mutex_unlock(&bd->mutex);
+ }
+
+ if (!rc)
+ fuse_reply_ioctl(req, 0, &msg2, sizeof(msg2));
+ else
+ fuse_reply_err(req, -rc);
+ break;
+
default:
fuse_reply_err(req, ENOSYS);
break;
@@ -1084,6 +1155,7 @@
rshim_backend_t *bd = cuse_dev_get_priv0(cdev);
int rc = CUSE_ERR_INVALID;
rshim_ioctl_msg msg;
+ rshim_ioctl_msg2 msg2;
uint64_t data;
pthread_mutex_lock(&bd->mutex);
@@ -1096,7 +1168,7 @@
rc = bd->read_rshim(bd,
(msg.addr >> 16) & 0xF, /* channel # */
msg.addr & 0xFFFF, /* addr */
- &data);
+ &data, RSHIM_REG_SIZE_8B);
if (!rc)
rc = cuse_copy_out(&msg, peer_data, sizeof(msg));
else
@@ -1110,7 +1182,33 @@
rc = bd->write_rshim(bd,
(msg.addr >> 16) & 0xF, /* channel # */
msg.addr & 0xFFFF, /* addr */
- msg.data);
+ msg.data, RSHIM_REG_SIZE_8B);
+ if (rc)
+ rc = CUSE_ERR_INVALID;
+ break;
+
+ case RSHIM_IOC_READ2:
+ rc = cuse_copy_in(peer_data, &msg2, sizeof(msg2));
+ if (rc == CUSE_ERR_NONE) {
+ data = msg2.data;
+ rc = bd->read_rshim(bd,
+ (msg2.addr >> 16) & 0xF, /* channel # */
+ msg2.addr & 0xFFFF, /* addr */
+ &data, msg2.data_size);
+ if (!rc)
+ rc = cuse_copy_out(&msg2, peer_data, sizeof(msg2));
+ else
+ rc = CUSE_ERR_INVALID;
+ }
+ break;
+
+ case RSHIM_IOC_WRITE2:
+ rc = cuse_copy_in(peer_data, &msg2, sizeof(msg2));
+
+ rc = bd->write_rshim(bd,
+ (msg2.addr >> 16) & 0xF, /* channel # */
+ msg2.addr & 0xFFFF, /* addr */
+ msg2.data, msg2.data_size);
if (rc)
rc = CUSE_ERR_INVALID;
break;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim_log.c
new/rshim-2.0.6.13.7/src/rshim_log.c
--- old/rshim-2.0.6.11.5/src/rshim_log.c 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/src/rshim_log.c 2022-09-12 18:05:02.000000000
+0200
@@ -207,11 +207,11 @@
size -= n;
for (i = 0; i < len/2; i++) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &opcode);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &opcode,
RSHIM_REG_SIZE_8B);
if (rc)
break;
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &data);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &data,
RSHIM_REG_SIZE_8B);
if (rc)
break;
@@ -263,7 +263,7 @@
p = msg;
while (len--) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &data);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &data,
RSHIM_REG_SIZE_8B);
if (rc) {
free(msg);
return 0;
@@ -307,7 +307,7 @@
/* Take the semaphore. */
time(&t0);
while (true) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->semaphore0, &data);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->semaphore0, &data,
RSHIM_REG_SIZE_8B);
if (rc) {
RSHIM_ERR("couldn't read RSH_SEMAPHORE0\n");
return p - buf;
@@ -323,7 +323,7 @@
}
/* Read the current index. */
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_ctl, &idx);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_ctl, &idx,
RSHIM_REG_SIZE_8B);
if (rc) {
RSHIM_ERR("couldn't read RSH_SCRATCH_BUF_CTL\n");
goto done;
@@ -333,7 +333,7 @@
goto done;
/* Reset the index to 0. */
- rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_ctl, 0);
+ rc = bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_ctl, 0,
RSHIM_REG_SIZE_8B);
if (rc) {
RSHIM_ERR("couldn't write RSH_SCRATCH_BUF_CTL\n");
goto done;
@@ -341,7 +341,7 @@
i = 0;
while (i < idx) {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &hdr);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &hdr,
RSHIM_REG_SIZE_8B);
if (rc) {
RSHIM_ERR("couldn't read RSH_SCRATCH_BUF_DAT\n");
goto done;
@@ -369,17 +369,17 @@
default:
/* Drain this message. */
while (len--)
- bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &data);
+ bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_dat, &data,
RSHIM_REG_SIZE_8B);
break;
}
}
/* Restore the idx value. */
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_ctl, idx);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratch_buf_ctl, idx,
RSHIM_REG_SIZE_8B);
done:
/* Release the semaphore. */
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->semaphore0, 0);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->semaphore0, 0,
RSHIM_REG_SIZE_8B);
return p - buf;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim_pcie.c
new/rshim-2.0.6.13.7/src/rshim_pcie.c
--- old/rshim-2.0.6.11.5/src/rshim_pcie.c 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/src/rshim_pcie.c 2022-09-12 18:05:02.000000000
+0200
@@ -41,8 +41,8 @@
#define TILERA_VENDOR_ID 0x15b3
#define BLUEFIELD1_DEVICE_ID 0xc2d2
#define BLUEFIELD2_DEVICE_ID 0xc2d3
-#define BLUEFIELD2_DEVICE_ID2 0xc2d6
#define BLUEFIELD3_DEVICE_ID 0xc2d4
+#define BLUEFIELD3_DEVICE_ID2 0xc2d5
/* The offset in BAR2 of the RShim region. */
#define PCI_RSHIM_WINDOW_OFFSET 0x0
@@ -130,9 +130,6 @@
static bool rshim_pcie_has_uio(void);
#endif
-/* Interrupt polling interval in milliseconds for direct-mapping mode. */
-int rshim_pcie_intr_poll_interval = 10;
-
static inline uint64_t
readq(const volatile void *addr)
{
@@ -215,7 +212,8 @@
static bool rshim_is_bluefield3(uint16_t device_id)
{
- return (device_id == BLUEFIELD3_DEVICE_ID);
+ return ((device_id == BLUEFIELD3_DEVICE_ID) ||
+ (device_id == BLUEFIELD3_DEVICE_ID2));
}
#ifdef __linux__
@@ -225,11 +223,14 @@
/* Release pcie resource. */
static void rshim_pcie_mmap_release(rshim_pcie_t *dev)
{
+ volatile void *ptr;
rshim_pcie_enable_irq(dev, false);
- if (dev->rshim_regs) {
- munmap((void *)dev->rshim_regs, PCI_RSHIM_WINDOW_SIZE);
+ ptr = dev->rshim_regs;
+ if (ptr) {
dev->rshim_regs = NULL;
+ __sync_synchronize();
+ munmap((void *)ptr, PCI_RSHIM_WINDOW_SIZE);
}
if (dev->device_fd >= 0) {
@@ -678,7 +679,7 @@
if (dev->intr_cnt > RSHIM_PCIE_NIC_IRQ_RATE)
return;
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, &info.word);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, &info.word,
RSHIM_REG_SIZE_8B);
if (rc || RSHIM_BAD_CTRL_REG(info.word)) {
RSHIM_WARN("Failed to read irq request\n");
return;
@@ -699,12 +700,12 @@
info.rst_reply = RSHIM_PCIE_RST_REPLY_ACK;
dev->nic_reset = true;
__sync_synchronize();
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, info.word);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, info.word,
RSHIM_REG_SIZE_8B);
sleep(RSHIM_PCIE_NIC_RESET_WAIT);
dev->nic_reset = false;
}
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, &info.word);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, &info.word,
RSHIM_REG_SIZE_8B);
if (rc || RSHIM_BAD_CTRL_REG(info.word)) {
RSHIM_WARN("Failed to read irq request\n");
return;
@@ -713,7 +714,7 @@
if (info.rst_state == RSHIM_PCIE_RST_STATE_ABORT) {
RSHIM_INFO("NIC reset ABORT\n");
info.word &= 0xFFFFFFFFUL;
- bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, info.word);
+ bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, info.word,
RSHIM_REG_SIZE_8B);
} else if (info.rst_type == RSHIM_PCIE_RST_TYPE_DPU_RESET) {
/*
* Both NIC and ARM reset.
@@ -838,12 +839,12 @@
/* RShim read/write routines */
static int __attribute__ ((noinline))
-rshim_pcie_read(rshim_backend_t *bd, int chan, int addr, uint64_t *result)
+rshim_pcie_read(rshim_backend_t *bd, int chan, int addr, uint64_t *result, int
size)
{
rshim_pcie_t *dev = container_of(bd, rshim_pcie_t, bd);
int rc = 0;
- if (!bd->has_rshim || !bd->has_tm)
+ if (!bd->has_rshim || !bd->has_tm || !dev->rshim_regs)
return -ENODEV;
if (dev->nic_reset && addr != bd->regs->scratchpad6)
@@ -867,13 +868,13 @@
}
static int __attribute__ ((noinline))
-rshim_pcie_write(rshim_backend_t *bd, int chan, int addr, uint64_t value)
+rshim_pcie_write(rshim_backend_t *bd, int chan, int addr, uint64_t value, int
size)
{
rshim_pcie_t *dev = container_of(bd, rshim_pcie_t, bd);
uint64_t result;
int rc = 0;
- if (!bd->has_rshim || !bd->has_tm)
+ if (!bd->has_rshim || !bd->has_tm || !dev->rshim_regs)
return -ENODEV;
if (dev->nic_reset && addr != bd->regs->scratchpad6)
@@ -893,7 +894,7 @@
if (rshim_is_bluefield1(dev->pci_dev->device_id)) {
if (dev->write_count == 15) {
__sync_synchronize();
- rshim_pcie_read(bd, chan, RSH_SCRATCHPAD1, &result);
+ rshim_pcie_read(bd, chan, RSH_SCRATCHPAD1, &result, rc);
}
dev->write_count++;
}
@@ -928,7 +929,7 @@
* This needs to be done before the resources are unmapped.
*/
if (!enable)
- rshim_pcie_write(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, 0);
+ rshim_pcie_write(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, 0,
RSHIM_REG_SIZE_8B);
/* Unmap existing resource first. */
rshim_pcie_mmap(dev, false);
@@ -1028,6 +1029,7 @@
switch (pci_dev->device_id) {
case BLUEFIELD3_DEVICE_ID:
+ case BLUEFIELD3_DEVICE_ID2:
bd->regs = &bf3_rshim_regs;
bd->ver_id = RSHIM_BLUEFIELD_3;
break;
@@ -1047,7 +1049,9 @@
/* Enable the device and setup memory map. */
if (!bd->drop_mode) {
+ pthread_mutex_lock(&bd->mutex);
rc = bd->enable_device(bd, true);
+ pthread_mutex_unlock(&bd->mutex);
if (rc)
goto rshim_probe_failed;
}
@@ -1094,6 +1098,9 @@
DIR* dir;
int rc;
+ if (!rshim_pcie_enable_vfio)
+ return false;
+
rc = system("modprobe vfio_pci");
if (rc == -1)
RSHIM_DBG("Failed to load the vfio_pci module %m\n");
@@ -1119,6 +1126,9 @@
DIR* dir;
int rc;
+ if (!rshim_pcie_enable_uio)
+ return false;
+
rc = system("modprobe uio_pci_generic");
if (rc == -1)
RSHIM_DBG("Failed to load the uio_pci_generic module %m\n");
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim_pcie_lf.c
new/rshim-2.0.6.13.7/src/rshim_pcie_lf.c
--- old/rshim-2.0.6.11.5/src/rshim_pcie_lf.c 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/src/rshim_pcie_lf.c 2022-09-12 18:05:02.000000000
+0200
@@ -646,7 +646,7 @@
/* RShim read/write routines */
static int __attribute__ ((noinline))
-rshim_pcie_read(struct rshim_backend *bd, int chan, int addr, uint64_t *result)
+rshim_pcie_read(struct rshim_backend *bd, int chan, int addr, uint64_t
*result, int size)
{
rshim_pcie_lf_t *dev = container_of(bd, rshim_pcie_lf_t, bd);
struct pci_dev *pci_dev = dev->pci_dev;
@@ -673,7 +673,7 @@
}
static int __attribute__ ((noinline))
-rshim_pcie_write(struct rshim_backend *bd, int chan, int addr, uint64_t value)
+rshim_pcie_write(struct rshim_backend *bd, int chan, int addr, uint64_t value,
int size)
{
rshim_pcie_lf_t *dev = container_of(bd, rshim_pcie_lf_t, bd);
struct pci_dev *pci_dev = dev->pci_dev;
@@ -704,7 +704,7 @@
if (pci_dev->device_id == BLUEFIELD1_DEVICE_ID) {
if (dev->write_count == 7) {
__sync_synchronize();
- rshim_pcie_read(bd, chan, RSH_SCRATCHPAD1, &result);
+ rshim_pcie_read(bd, chan, RSH_SCRATCHPAD1, &result, rc);
}
dev->write_count++;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/rshim-2.0.6.11.5/src/rshim_usb.c
new/rshim-2.0.6.13.7/src/rshim_usb.c
--- old/rshim-2.0.6.11.5/src/rshim_usb.c 2022-07-13 19:15:52.000000000
+0200
+++ new/rshim-2.0.6.13.7/src/rshim_usb.c 2022-09-12 18:05:02.000000000
+0200
@@ -140,8 +140,13 @@
struct rshim_usb_addr rsh_usb_addr;
if (ver_id == RSHIM_BLUEFIELD_3) {
- rsh_usb_addr.wvalue = bf3_wvalue_widx_pair_map[chan].wvalue + BF_MMIO_BASE;
- rsh_usb_addr.windex = bf3_wvalue_widx_pair_map[chan].windex + addr;
+ if (chan <= 0xF) {
+ rsh_usb_addr.wvalue = bf3_wvalue_widx_pair_map[chan].wvalue +
BF_MMIO_BASE;
+ rsh_usb_addr.windex = bf3_wvalue_widx_pair_map[chan].windex + addr;
+ } else {
+ rsh_usb_addr.wvalue = chan;
+ rsh_usb_addr.windex = addr;
+ }
} else {
rsh_usb_addr.wvalue = chan;
rsh_usb_addr.windex = addr;
@@ -153,7 +158,7 @@
/* Rshim read/write routines */
static int rshim_usb_read_rshim(rshim_backend_t *bd, int chan, int addr,
- uint64_t *result)
+ uint64_t *result, int size)
{
rshim_usb_t *dev = container_of(bd, rshim_usb_t, bd);
struct rshim_usb_addr rsh_usb_addr;
@@ -162,6 +167,11 @@
if (!bd->has_rshim)
return -ENODEV;
+ if ((bd->ver_id == RSHIM_BLUEFIELD_3) && (size <= RSHIM_REG_SIZE_4B))
+ size = RSHIM_REG_SIZE_4B;
+ else
+ size = RSHIM_REG_SIZE_8B;
+
rsh_usb_addr = get_wvalue_windex(chan, addr, bd->ver_id);
/* Do a blocking control read and endian conversion. */
@@ -170,8 +180,7 @@
LIBUSB_REQUEST_TYPE_VENDOR |
LIBUSB_RECIPIENT_ENDPOINT,
0, rsh_usb_addr.wvalue, rsh_usb_addr.windex,
- (unsigned char *)&dev->ctrl_data,
- sizeof(dev->ctrl_data),
+ (unsigned char *)&dev->ctrl_data, size,
RSHIM_USB_TIMEOUT);
/*
@@ -180,7 +189,7 @@
* cores.
*/
*result = le64toh(dev->ctrl_data);
- if (rc == sizeof(dev->ctrl_data))
+ if (rc == size)
return 0;
/*
@@ -188,11 +197,11 @@
* the USB stack doesn't use so that we can identify short/long
* reads.
*/
- return rc >= 0 ? (rc > sizeof(dev->ctrl_data) ? -EINVAL : -ENXIO) : rc;
+ return rc >= 0 ? (rc > size ? -EINVAL : -ENXIO) : rc;
}
static int rshim_usb_write_rshim(rshim_backend_t *bd, int chan, int addr,
- uint64_t value)
+ uint64_t value, int size)
{
rshim_usb_t *dev = container_of(bd, rshim_usb_t, bd);
struct rshim_usb_addr rsh_usb_addr;
@@ -201,6 +210,11 @@
if (!bd->has_rshim)
return -ENODEV;
+ if ((bd->ver_id == RSHIM_BLUEFIELD_3) && (size <= RSHIM_REG_SIZE_4B))
+ size = RSHIM_REG_SIZE_4B;
+ else
+ size = RSHIM_REG_SIZE_8B;
+
rsh_usb_addr = get_wvalue_windex(chan, addr, bd->ver_id);
/* Convert the word to little endian and do blocking control write. */
@@ -210,11 +224,10 @@
LIBUSB_REQUEST_TYPE_VENDOR |
LIBUSB_RECIPIENT_ENDPOINT,
0, rsh_usb_addr.wvalue, rsh_usb_addr.windex,
- (unsigned char *)&dev->ctrl_data,
- sizeof(dev->ctrl_data),
+ (unsigned char *)&dev->ctrl_data, size,
RSHIM_USB_TIMEOUT);
- if (rc == sizeof(dev->ctrl_data))
+ if (rc == size)
return 0;
/*
@@ -222,7 +235,7 @@
* the USB stack doesn't use so that we can identify short/long
* writes.
*/
- return rc >= 0 ? (rc > sizeof(dev->ctrl_data) ? -EINVAL : -ENXIO) : rc;
+ return rc >= 0 ? (rc > size ? -EINVAL : -ENXIO) : rc;
}
static ssize_t rshim_usb_bf3_boot_write(rshim_backend_t *bd, const char *buf,
@@ -249,7 +262,7 @@
*/
do {
- rc = bd->read_rshim(bd, RSHIM_CHANNEL, size_addr, ®);
+ rc = bd->read_rshim(bd, RSHIM_CHANNEL, size_addr, ®,
RSHIM_REG_SIZE_8B);
if (rc < 0) {
RSHIM_ERR("read_rshim error %d\n", rc);
return rc;
