Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package cpuid for openSUSE:Factory checked
in at 2023-02-10 14:34:17
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/cpuid (Old)
and /work/SRC/openSUSE:Factory/.cpuid.new.1848 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid"
Fri Feb 10 14:34:17 2023 rev:17 rq:1064049 version:20230120
Changes:
--------
--- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2022-12-05
18:02:09.828896113 +0100
+++ /work/SRC/openSUSE:Factory/.cpuid.new.1848/cpuid.changes 2023-02-10
14:34:18.173555746 +0100
@@ -1,0 +2,50 @@
+Sat Jan 28 19:47:27 UTC 2023 - Dirk Müller <dmuel...@suse.com>
+
+- updaet to 20230120:
+ * Intel's 13th Generation Core datasheet provides stepping names as
+ well as numbers! So:
+ * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
+ * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
+ steppings, and clarified case for unknown stepping.
+ * cpuid.man: Added 743844: 13th Generation Core datasheet.
+ * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
+ * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
+ * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
+ * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
+ * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
+ * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
+ * cpuid.c: Added several 7/2/edx bits.
+ * cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
+ * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
+ relevant for XCR0.
+ * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
+ hex bitmask.
+ * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
+ * cpuid.c: Renamed 0x1a: Native Model ID.
+ * cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake
+ from MSR_CPUID_table*.
+ * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
+ based on instlatx64 sample.
+ * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
+ Emerald Rapids CPUs.
+ * cpuid.c: Added 7/1/eax LASS: linear address space separation.
+ * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
+ should use minus-one notation.
+ * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
+ i.e. without information about other leaves saved in the stash. For
+ example, the display for leaf 3 uses bits saved from leaf 1. If the
+ -l/--leaf option is used to restrict cpuid to reading only a single
+ leaf, such leaves now are displayed as raw hex, rather than with
+ incorrect information. This is handled by passing a NULL stash to
+ print_reg() and below, and by many new checks for a NULL stash.
+ * cpuid.c: Updated cache associativity strings used in 0x80000006 and
+ 0x80000019 leaves to use value ranges, as in AMD docs.
+ * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
+ 0x80000020/0 register EBX, not ECX.
+ * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
+ * cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from
+ AMD 57095 revision guide.
+ * cpuid.man: Added AMD 57095 revision guides, and some older guides that
+ I'd forgotten.
+
+-------------------------------------------------------------------
Old:
----
cpuid-20221201.src.tar.gz
New:
----
cpuid-20230120.src.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ cpuid.spec ++++++
--- /var/tmp/diff_new_pack.za4bVS/_old 2023-02-10 14:34:18.585558208 +0100
+++ /var/tmp/diff_new_pack.za4bVS/_new 2023-02-10 14:34:18.589558232 +0100
@@ -1,7 +1,7 @@
#
# spec file for package cpuid
#
-# Copyright (c) 2022 SUSE LLC
+# Copyright (c) 2023 SUSE LLC
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
@@ -17,7 +17,7 @@
Name: cpuid
-Version: 20221201
+Version: 20230120
Release: 0
Summary: x86 CPU identification tool
License: GPL-2.0-or-later
++++++ cpuid-20221201.src.tar.gz -> cpuid-20230120.src.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221201/ChangeLog new/cpuid-20230120/ChangeLog
--- old/cpuid-20221201/ChangeLog 2022-12-01 12:38:25.000000000 +0100
+++ new/cpuid-20230120/ChangeLog 2023-01-20 14:28:38.000000000 +0100
@@ -1,3 +1,68 @@
+Fri Jan 20 2023 Todd Allen <todd.al...@etallen.com>
+ * Made new release.
+
+Fri Jan 20 2023 Todd Allen <todd.al...@etallen.com>
+ * Eliminate reliance on "old" build system. Instead, for the cpuid.i386
+ and cpuid.x86_64, meant to be executable anywhere, including on old
+ hardware & distros, use static builds. They're much bigger, but
+ utterly immune to library changes.
+
+Wed Jan 18 2023 Todd Allen <todd.al...@etallen.com>
+ * Intel's 13th Generation Core datasheet provides stepping names as
+ well as numbers! So:
+ * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0
stepping.
+ * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
+ steppings, and clarified case for unknown stepping.
+ * cpuid.man: Added 743844: 13th Generation Core datasheet.
+ * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
+
+Tue Jan 17 2023 Todd Allen <todd.al...@etallen.com>
+ * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
+ * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
+ * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
+ * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
+ * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
+ * cpuid.c: Added several 7/2/edx bits.
+ * cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS.
+ * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
+ relevant for XCR0.
+ * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
+ hex bitmask.
+ * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
+ * cpuid.c: Renamed 0x1a: Native Model ID.
+ * cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake
+ from MSR_CPUID_table*.
+ * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
+ based on instlatx64 sample.
+ * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
+ Emerald Rapids CPUs.
+ * cpuid.c: Added 7/1/eax LASS: linear address space separation.
+ * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
+ should use minus-one notation.
+
+Tue Jan 17 2023 Todd Allen <todd.al...@etallen.com>
+ * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
+ i.e. without information about other leaves saved in the stash. For
+ example, the display for leaf 3 uses bits saved from leaf 1. If the
+ -l/--leaf option is used to restrict cpuid to reading only a single
+ leaf, such leaves now are displayed as raw hex, rather than with
+ incorrect information. This is handled by passing a NULL stash to
+ print_reg() and below, and by many new checks for a NULL stash.
+ Thanks to Bill Zissimopoulos for the bug report.
+
+Mon Jan 9 2023 Todd Allen <todd.al...@etallen.com>
+ * cpuid.c: Updated cache associativity strings used in 0x80000006 and
+ 0x80000019 leaves to use value ranges, as in AMD docs.
+ * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
+ 0x80000020/0 register EBX, not ECX.
+ * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
+
+Tue Dec 13 2022 Todd Allen <todd.al...@etallen.com>
+ * cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from
+ AMD 57095 revision guide.
+ * cpuid.man: Added AMD 57095 revision guides, and some older guides that
+ I'd forgotten.
+
Thu Dec 1 2022 Todd Allen <todd.al...@etallen.com>
* Made new release.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221201/Makefile new/cpuid-20230120/Makefile
--- old/cpuid-20221201/Makefile 2022-12-01 12:38:36.000000000 +0100
+++ new/cpuid-20230120/Makefile 2023-01-20 14:23:57.000000000 +0100
@@ -8,7 +8,7 @@
INSTALL_STRIP=-s
PACKAGE=cpuid
-VERSION=20221201
+VERSION=20230120
RELEASE=1
PROG=$(PACKAGE)
@@ -75,22 +75,11 @@
# Todd's Development rules
-OLD_DIR=/tmp/cpuid
-OLD_HOST_i386=raptor
-OLD_HOST_x86_64=iggy
-
-$(PROG).old: cpuid.c Makefile
- ssh $(OLD_HOST) "rm -rf $(OLD_DIR); mkdir -p $(OLD_DIR)"
- scp -p $^ $(OLD_HOST):$(OLD_DIR)
- ssh $(OLD_HOST) "cd $(OLD_DIR); make cpuid"
- scp -p $(OLD_HOST):$(OLD_DIR)/cpuid $(TARGET)
- ssh $(OLD_HOST) "rm -rf $(OLD_DIR)"
-
$(PROG).i386: cpuid.c Makefile
- $(MAKE) -$(MAKEFLAGS) $(PROG).old TARGET=$@ OLD_HOST=$(OLD_HOST_i386)
+ $(CC) -m32 -static $(CFL) $(LDFLAGS) -o $@ cpuid.c
$(PROG).x86_64: cpuid.c Makefile
- $(MAKE) -$(MAKEFLAGS) $(PROG).old TARGET=$@ OLD_HOST=$(OLD_HOST_x86_64)
+ $(CC) -static $(CFL) $(LDFLAGS) -o $@ cpuid.c
todd: $(PROG).i386 $(PROG).x86_64
rm -f ~/.bin/execs/i586/$(PROG)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221201/cpuid.c new/cpuid-20230120/cpuid.c
--- old/cpuid-20221201/cpuid.c 2022-11-30 15:11:48.000000000 +0100
+++ new/cpuid-20230120/cpuid.c 2023-01-20 14:27:21.000000000 +0100
@@ -1,7 +1,7 @@
/*
** cpuid dumps CPUID information for each CPU.
** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017,2018,
-** 2020,2021,2022 by Todd Allen.
+** 2020,2021,2022,2023 by Todd Allen.
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License
@@ -2181,10 +2181,11 @@
FM ( 0, 6, 10,15, *u = "Sierra Forest");
// MSR_CPUID_table*; LX*; (engr?)
sample via instlatx64 from Komachi_ENSAKA
FM ( 0, 6, 11, 5, *u = "Redwood Cove",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*
FM ( 0, 6, 11, 6, *u = "Crestmont",
*p = "Intel 7"); // MSR_CPUID_table*; LX*; (although
assumption that Grand Ridge is Crestmont)
- FM ( 0, 6, 11, 7, *u = "Raptor Cove",
*f = "Golden Cove", *p = "Intel 7"); // LX*, DPTF*
+ FM ( 0, 6, 11, 7, *u = "Raptor Cove",
*f = "Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF*
FM ( 0, 6, 11,10, *u = "Raptor Cove",
*f = "Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot*
FM ( 0, 6, 11,14, *u = "Golden Cove",
*p = "Intel 7"); // Coreboot*
- FM ( 0, 6, 12,15, *u = "Emerald Rapids",
*p = "Intel 7"); // LX*
+ FM ( 0, 6, 11,15, *u = "Raptor Cove",
*f = "Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*
+ FM ( 0, 6, 12,15, *u = "Emerald Rapids",
*p = "Intel 7"); // MSR_CPUID_table*; LX*
F ( 0, 7, *u = "Itanium");
FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu =
TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org
FM ( 0,11, 0, 1, *u = "Knights Corner", *ciu =
TRUE, *f = "K1OM", *p = "22nm");
@@ -2308,6 +2309,7 @@
FM (10,15, 0, 1, *u = "Zen 3", *p = "7nm");
FM (10,15, 0, 8, *u = "Zen 3", *p = "7nm"); //
undocumented, but sample via instlatx64 from @ExecuFix
FM (10,15, 1, 0, *u = "Zen 4", *p = "5nm"); //
undocumented, but sample via instlatx64 from @ExecuFix
+ FM (10,15, 1, 1, *u = "Zen 4", *p = "5nm");
FM (10,15, 1, 8, *u = "Zen 4", *p = "5nm"); //
undocumented, but sample via instlatx64 from @patrickschur_
FM (10,15, 2, 1, *u = "Zen 3", *p = "7nm");
FM (10,15, 3, 0, *u = "Zen 3", *p = "7nm"); //
undocumented, but sample via instlatx64 from @patrickschur_
@@ -3489,8 +3491,10 @@
FMSQ( 0, 6, 9, 7, 4, dc, "Intel Core i*-1200U (Alder Lake-U G0)");
FMS ( 0, 6, 9, 7, 4, "Intel (unknown type) (Alder Lake-U G0)");
FMSQ( 0, 6, 9, 7, 5, dc, "Intel Core i*-12000 (Alder Lake-S H0)");
+ FMSQ( 0, 6, 9, 7, 5, dP, "Intel Pentium Gold G7400 (Alder Lake-S H0)");
FMS ( 0, 6, 9, 7, 5, "Intel (unknown type) (Alder Lake-S H0)");
FMQ ( 0, 6, 9, 7, dc, "Intel Core i*-12000 (Alder Lake-S/P/H/U)");
+ FMQ ( 0, 6, 9, 7, dP, "Intel Pentium Gold G7400 (Alder Lake-S)");
// no docs on Pentium Gold version; instlatx64 sample
FM ( 0, 6, 9, 7, "Intel (unknown type) (Alder Lake-S/P/H/U)");
// MSR_CPUID_table*, Coreboot*. Coreboot* provides steppings.
FMSQ( 0, 6, 9,10, 0, dc, "Intel Core (Alder Lake J0)");
@@ -3600,14 +3604,22 @@
FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); //
MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA
FM ( 0, 6, 11, 5, "Intel (unknown type) (Meteor Lake)"); //
MSR_CPUID_table*
FM ( 0, 6, 11, 6, "Intel Atom (Grand Ridge)"); //
MSR_CPUID_table*
- FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 (Raptor Lake)"); //
MSR_CPUID_table*; LX*; DPTF* (which also says Raptor Lake-S); instlatx64 samples
- FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake)"); //
MSR_CPUID_table*; LX*; DPTF* (which also says Raptor Lake-S)
- FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-P J0)");
// Coreboot*
- FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)");
// Coreboot*
+ FMSQ( 0, 6, 11, 7, 1, dc, "Intel Core i*-13000 (Raptor Lake-S/HX B0)");
+ FMS ( 0, 6, 11, 7, 1, "Intel (unknown type) (Raptor Lake-S/HX B0)");
+ FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 (Raptor Lake-S/HX)");
+ FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake-S/HX)");
+ FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-P J0)");
+ FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)");
FM ( 0, 6, 11,10, "Intel (unknown type) (Raptor Lake-P)"); //
LX*; DPTF*; Coreboot*
FMS ( 0, 6, 11,14, 0, "Intel (unknown type) (Alder Lake-N A0)"); //
Coreboot*
FM ( 0, 6, 11,14, "Intel (unknown type) (Alder Lake-N)"); //
Coreboot*, LX*
- FM ( 0, 6, 11,15, "Intel (unknown type) (Alder Lake)"); //
MSR_CPUID_table* (or maybe Gracemont "little" cores tied to Alder Lake?); LX*
thinks it's Raptor Lake-S
+ FMSQ( 0, 6, 11,15, 2, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)");
+ FMS ( 0, 6, 11,15, 2, "Intel (unknown type) (Raptor Lake-S/HX C0)");
+ FMSQ( 0, 6, 11,15, 5, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)");
+ FMS ( 0, 6, 11,15, 5, "Intel (unknown type) (Raptor Lake-S/HX C0)");
+ FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/H)");
+ FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/H)");
+ FM ( 0, 6, 12,15, "Intel Xeon (unknown type) (Emerald
Rapids)"); // MSR_CPUID_table*, LX*
FQ ( 0, 6, sX, "Intel Xeon (unknown model)");
FQ ( 0, 6, se, "Intel Xeon (unknown model)");
FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)");
@@ -4565,6 +4577,8 @@
FMS (10,15, 1, 0, 0, "AMD EPYC (Genoa A0)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
FMS (10,15, 1, 0, 1, "AMD EPYC (Genoa A1)"); // undocumented, but
(engr?) sample via instlatx64 from @IanCutress
FM (10,15, 1, 0, "AMD EPYC (Genoa)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
+ FMS (10,15, 1, 1, 1, "AMD EPYC (Genoa B1)");
+ FM (10,15, 1, 1, "AMD EPYC (Genoa)");
FMS (10,15, 1, 8, 0, "AMD Ryzen (Storm Peak A0)"); // undocumented,
but (engr?) sample from @patrickschur_
FMS (10,15, 1, 8, 1, "AMD Ryzen (Storm Peak A1)"); // undocumented,
but engr sample via instlatx64 from einstein11.aei.uni-hannover.de (12981157)
FM (10,15, 1, 8, "AMD Ryzen (Storm Peak)"); // undocumented, but
(engr?) sample from @patrickschur_
@@ -5959,6 +5973,7 @@
{ "HW_FEEDBACK MSRs supported" , 19, 19, bools },
{ "ignoring idle logical processor HWP req" , 20, 20, bools },
{ "Thread Director" , 23, 23, bools },
+ { "IA32_HW_FEEDBACK_THREAD_CONFIG bit 25" , 24, 24, bools },
};
print_names(value, names, LENGTH(names),
@@ -6089,21 +6104,17 @@
static void
print_7_0_edx(unsigned int value)
{
- // Bit 9 (SRBDS_CTRL) described in Intel's "Special Register Buffer Data
- // Sampling", Last Updated 06/09/2020.
- // Bit 11 (RTM_ALWAYS_ABORT) described in "Intel Transactional
- // Synchronization Extensions (Intel TSX) Memory and Performance Monitoring
- // Update for Intel Processors", Last Reviewed 02/09/2022.
static named_item names[]
- = { { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools },
+ = { { "SGX-KEYS: SGX attestation services" , 1, 1, bools },
+ { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools },
{ "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools },
{ "fast short REP MOV" , 4, 4, bools },
{ "UINTR: user interrupts" , 5, 5, bools },
{ "AVX512_VP2INTERSECT: intersect mask regs", 8, 8, bools },
- { "SRBDS mitigation MSR available" , 9, 9, bools },
+ { "IA32_MCU_OPT_CTRL SRBDS mitigation MSR" , 9, 9, bools },
{ "VERW MD_CLEAR microcode support" , 10, 10, bools },
{ "RTM transaction always aborts" , 11, 11, bools },
- { "TSX_FORCE_ABORT" , 13, 13, bools },
+ { "IA32_TSX_FORCE_ABORT MSR" , 13, 13, bools },
{ "SERIALIZE instruction" , 14, 14, bools },
{ "hybrid part" , 15, 15, bools },
{ "TSXLDTRK: TSX suspend load addr tracking", 16, 16, bools },
@@ -6132,6 +6143,7 @@
= { { "RAO-INT atomic instructions" , 3, 3, bools },
{ "AVX-VNNI: AVX VNNI neural network instrs", 4, 4, bools },
{ "AVX512_BF16: bfloat16 instructions" , 5, 5, bools },
+ { "LASS: linear address space separation" , 6, 6, bools },
{ "CMPccXADD instructions" , 7, 7, bools },
{ "ArchPerfmonExt is valid" , 8, 8, bools },
{ "fast zero-length MOVSB" , 10, 10, bools },
@@ -6165,6 +6177,7 @@
= { { "AVX-VNNI-INT8 instructions" , 4, 4, bools },
{ "AVX-NE-CONVERT instructions" , 5, 5, bools },
{ "PREFETCHIT0, PREFETCHIT1 instructions" , 14, 14, bools },
+ { "CET_SSS: shadow stacks w/o page faults" , 18, 18, bools },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 40);
@@ -6173,13 +6186,13 @@
static void
print_7_2_edx(unsigned int value)
{
- // Described in Intel's "Branch History Injection and Intra-mode Branch
Target
- // Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598", Last Updated
- // 07/12/2022.
static named_item names[]
- = { { "IPRED_CTRL: IBP disable" , 1, 1, bools },
+ = { { "PSFD: fast store forwarding pred disable", 0, 0, bools },
+ { "IPRED_CTRL: IBP disable" , 1, 1, bools },
{ "RRSBA_CTRL: IBP bottomless RSB disable" , 2, 2, bools },
+ { "DDPD_U: data dep prefetcher disable" , 3, 3, bools },
{ "BHI_CTRL: IBP BHB-focused disable" , 4, 4, bools },
+ { "MCDT_NO: MCDT mitigation not needed" , 5, 5, bools },
};
print_names(value, names, LENGTH(names),
/* max_len => */ 40);
@@ -6292,7 +6305,6 @@
static void
print_d_0_eax(unsigned int value)
{
-
// State component bitmaps in general are described in 325462: Intel 64 and
// IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A,
// 2B, 2C, 3A, 3B, and 3C, Volume 1: Basic Architecture, section 13.1:
@@ -6306,24 +6318,17 @@
// See also print_12_1_ecx().
static named_item names[]
- = { { " XCR0 supported: x87 state" , 0, 0, bools },
- { " XCR0 supported: SSE state" , 1, 1, bools },
- { " XCR0 supported: AVX state" , 2, 2, bools },
- { " XCR0 supported: MPX BNDREGS" , 3, 3, bools },
- { " XCR0 supported: MPX BNDCSR" , 4, 4, bools },
- { " XCR0 supported: AVX-512 opmask" , 5, 5, bools },
- { " XCR0 supported: AVX-512 ZMM_Hi256" , 6, 6, bools },
- { " XCR0 supported: AVX-512 Hi16_ZMM" , 7, 7, bools },
- { " IA32_XSS supported: PT state" , 8, 8, bools },
- { " XCR0 supported: PKRU state" , 9, 9, bools },
- { " XCR0 supported: CET_U state" , 11, 11, bools },
- { " XCR0 supported: CET_S state" , 12, 12, bools },
- { " IA32_XSS supported: HDC state" , 13, 13, bools },
- { " IA32_XSS supported: UINTR state" , 14, 14, bools },
- { " LBR supported" , 15, 15, bools },
- { " IA32_XSS supported: HWP state" , 16, 16, bools },
- { " XTILECFG supported" , 17, 17, bools },
- { " XTILEDATA supported" , 18, 18, bools },
+ = { { " x87 state" , 0, 0, bools },
+ { " SSE state" , 1, 1, bools },
+ { " AVX state" , 2, 2, bools },
+ { " MPX BNDREGS" , 3, 3, bools },
+ { " MPX BNDCSR" , 4, 4, bools },
+ { " AVX-512 opmask" , 5, 5, bools },
+ { " AVX-512 ZMM_Hi256" , 6, 6, bools },
+ { " AVX-512 Hi16_ZMM" , 7, 7, bools },
+ { " PKRU state" , 9, 9, bools },
+ { " XTILECFG state" , 17, 17, bools },
+ { " XTILEDATA state" , 18, 18, bools },
};
print_names(value, names, LENGTH(names),
@@ -6350,7 +6355,26 @@
};
print_names(value, names, LENGTH(names),
- /* max_len => */ 43);
+ /* max_len => */ 39);
+}
+
+static void
+print_d_1_ecx(unsigned int value)
+{
+
+ static named_item names[]
+ = { { " PT state" , 8, 8, bools },
+ { " PASID state" , 10, 10, bools },
+ { " CET_U user state" , 11, 11, bools },
+ { " CET_S supervisor state" , 12, 12, bools },
+ { " HDC state" , 13, 13, bools },
+ { " UINTR state" , 14, 14, bools },
+ { " LBR state" , 15, 15, bools },
+ { " HWP state" , 16, 16, bools },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 39);
}
static void
@@ -6391,13 +6415,13 @@
/* 7 => */ "AVX-512 Hi16_ZMM",
/* 8 => */ "PT",
/* 9 => */ "PKRU",
- /* 10 => */ "unknown",
- /* 11 => */ "CET_U state",
- /* 12 => */ "CET_S state",
+ /* 10 => */ "PASID",
+ /* 11 => */ "CET_U user",
+ /* 12 => */ "CET_S supervisor",
/* 13 => */ "HDC",
/* 14 => */ "UINTR",
/* 15 => */ "LBR",
- /* 16 => */ "HWP state",
+ /* 16 => */ "HWP",
/* 17 => */ "XTILECFG",
/* 18 => */ "XTILEDATA",
/* 19 => */ "unknown",
@@ -6489,18 +6513,23 @@
unsigned int counter_size_raw = BIT_EXTRACT_LE(value, 0, 8);
unsigned int counter_size;
if (counter_size_raw == 0) {
- unsigned int synth_family = Synth_Family(stash->val_1_eax);
- unsigned int synth_model = Synth_Model(stash->val_1_eax);
- if (synth_family == 0x17 && 0x30 <= synth_model && synth_model <= 0x9f) {
- // V1.0 PQoS => 62
- counter_size = 62;
- } else if (synth_family == 0x19 && synth_model <= 0x0f) {
- // V2.0 PQoS => 44
- counter_size = 44;
- } else if (synth_family == 0x19
- && 0x20 <= synth_model && synth_model <= 0x5f) {
- // V2.0 PQoS => 44
- counter_size = 44;
+ if (stash) {
+ unsigned int synth_family = Synth_Family(stash->val_1_eax);
+ unsigned int synth_model = Synth_Model(stash->val_1_eax);
+ if (synth_family == 0x17 && 0x30 <= synth_model
+ && synth_model <= 0x9f) {
+ // V1.0 PQoS => 62
+ counter_size = 62;
+ } else if (synth_family == 0x19 && synth_model <= 0x0f) {
+ // V2.0 PQoS => 44
+ counter_size = 44;
+ } else if (synth_family == 0x19
+ && 0x20 <= synth_model && synth_model <= 0x5f) {
+ // V2.0 PQoS => 44
+ counter_size = 44;
+ } else {
+ counter_size = 0;
+ }
} else {
counter_size = 0;
}
@@ -6907,7 +6936,7 @@
= { { "translation cache type" , 0, 4, tlbs },
{ "translation cache level" , 5, 7, MINUS1_IMAGES
},
{ "fully associative" , 8, 8, bools },
- { "maximum number of addressible IDs" , 14, 25, NIL_IMAGES },
+ { "maximum number of addressible IDs" , 14, 25, MINUS1_IMAGES
},
};
print_names(value, names, LENGTH(names),
@@ -8238,17 +8267,17 @@
"direct mapped (1)",
"2-way (2)",
"3-way (3)",
- "4-way (4)",
- "6-way (5)",
- "8-way (6)",
+ "4 to 5-way (4)",
+ "6 to 7-way (5)",
+ "8 to 15-way (6)",
NULL,
- "16-way (8)",
+ "16 to 31-way (8)",
NULL,
- "32-way (10)",
- "48-way (11)",
- "64-way (12)",
- "96-way (13)",
- "128-way (14)",
+ "32 to 47-way (10)",
+ "48 to 63-way (11)",
+ "64 to 95-way (12)",
+ "96 to 127-way (13)",
+ "128 or more-way (14)",
"full (15)" };
static void
@@ -8297,10 +8326,12 @@
print_names(value, names, LENGTH(names),
/* max_len => */ 0);
- if (((value >> 12) & 0xf) == 4 && (value >> 16) == 256) {
- stash->L2_4w_256K = TRUE;
- } else if (((value >> 12) & 0xf) == 4 && (value >> 16) == 512) {
- stash->L2_4w_512K = TRUE;
+ if (stash) {
+ if (((value >> 12) & 0xf) == 4 && (value >> 16) == 256) {
+ stash->L2_4w_256K = TRUE;
+ } else if (((value >> 12) & 0xf) == 4 && (value >> 16) == 512) {
+ stash->L2_4w_512K = TRUE;
+ }
}
}
@@ -8423,10 +8454,12 @@
print_names(value, names, LENGTH(names),
/* max_len => */ 0);
- boolean not_vuln_BTC = (BIT_EXTRACT_LE(value, 29, 30)
- || Synth_Family(stash->val_80000001_eax) == 0x19);
- printf(" (vuln to branch type confusion synth) = %s\n",
- bools[!not_vuln_BTC]);
+ if (stash) {
+ boolean not_vuln_BTC = (BIT_EXTRACT_LE(value, 29, 30)
+ || Synth_Family(stash->val_80000001_eax) ==
0x19);
+ printf(" (vuln to branch type confusion synth) = %s\n",
+ bools[!not_vuln_BTC]);
+ }
}
static void
@@ -8823,21 +8856,11 @@
= { { "L3 external bandwidth" , 1, 1, bools },
{ "L3 external slow memory bandwidth" , 2, 2, bools },
{ "bandwidth monitoring event configuration", 3, 3, bools },
+ { "L3 range reservation support" , 4, 4, bools },
};
print_names(value, names, LENGTH(names),
- /* max_len => */ 40);
-}
-
-static void
-print_80000020_0_ecx(unsigned int value)
-{
- static named_item names[]
- = { { "L3 range reservation support" , 4, 4, bools },
- };
-
- print_names(value, names, LENGTH(names),
- /* max_len => */ 40);
+ /* max_len => */ 0);
}
static void
@@ -9103,7 +9126,9 @@
printf("\n");
- stash->transmeta_proc_rev = value;
+ if (stash) {
+ stash->transmeta_proc_rev = value;
+ }
}
}
@@ -9271,6 +9296,9 @@
" leaf.\n");
printf(" If -s/--subleaf is not specified, 0 is"
" assumed.\n");
+ printf(" NOTE: If a leaf cannot be interpreted"
+ " in isolation, it\n");
+ printf(" will be displayed as raw hex.\n");
printf(" -s V, --subleaf=V display information for the single
specified"
" subleaf.\n");
printf(" It requires -l/--leaf.\n");
@@ -9412,92 +9440,117 @@
unsigned int try,
code_stash_t* stash)
{
- if (reg == 0) {
- if (IS_VENDOR_ID(words, "GenuineIntel")) {
- stash->vendor = VENDOR_INTEL;
- } else if (IS_VENDOR_ID(words, "AuthenticAMD")) {
- stash->vendor = VENDOR_AMD;
- } else if (IS_VENDOR_ID(words, "CyrixInstead")) {
- stash->vendor = VENDOR_CYRIX;
- } else if (IS_VENDOR_ID(words, "CentaurHauls")) {
- stash->vendor = VENDOR_VIA;
- } else if (IS_VENDOR_ID(words, "UMC UMC UMC ")) {
- stash->vendor = VENDOR_UMC;
- } else if (IS_VENDOR_ID(words, "NexGenDriven")) {
- stash->vendor = VENDOR_NEXGEN;
- } else if (IS_VENDOR_ID(words, "RiseRiseRise")) {
- stash->vendor = VENDOR_RISE;
- } else if (IS_VENDOR_ID(words, "GenuineTMx86")) {
- stash->vendor = VENDOR_TRANSMETA;
- } else if (IS_VENDOR_ID(words, "SiS SiS SiS ")) {
- stash->vendor = VENDOR_SIS;
- } else if (IS_VENDOR_ID(words, "Geode by NSC")) {
- stash->vendor = VENDOR_NSC;
- } else if (IS_VENDOR_ID(words, "Vortex86 SoC")) {
- stash->vendor = VENDOR_VORTEX;
- } else if (IS_VENDOR_ID(words, "Genuine RDC")) {
- stash->vendor = VENDOR_RDC;
- } else if (IS_VENDOR_ID(words, "HygonGenuine")) {
- stash->vendor = VENDOR_HYGON;
- } else if (IS_VENDOR_ID(words, " Shanghai ")) {
- stash->vendor = VENDOR_ZHAOXIN;
- }
- } else if (reg == 1) {
- stash->val_1_eax = words[WORD_EAX];
- stash->val_1_ebx = words[WORD_EBX];
- stash->val_1_ecx = words[WORD_ECX];
- stash->val_1_edx = words[WORD_EDX];
- } else if (reg == 4) {
- stash->saw_4 = TRUE;
- if (try == 0) {
- stash->val_4_eax = words[WORD_EAX];
- }
- } else if (reg == 0xb) {
- stash->saw_b = TRUE;
- if (try < LENGTH(stash->val_b_eax)) {
- stash->val_b_eax[try] = words[WORD_EAX];
- }
- if (try < LENGTH(stash->val_b_ebx)) {
- stash->val_b_ebx[try] = words[WORD_EBX];
- }
- } else if (reg == 0x1f) {
- stash->saw_1f = TRUE;
- if (try < LENGTH(stash->val_1f_eax)) {
- stash->val_1f_eax[try] = words[WORD_EAX];
- }
- if (try < LENGTH(stash->val_1f_ebx)) {
- stash->val_1f_ebx[try] = words[WORD_EBX];
- }
- if (try < LENGTH(stash->val_1f_ecx)) {
- stash->val_1f_ecx[try] = words[WORD_ECX];
+ if (stash) {
+ if (reg == 0) {
+ stash->val_0_eax = words[WORD_EAX];
+ if (IS_VENDOR_ID(words, "GenuineIntel")) {
+ stash->vendor = VENDOR_INTEL;
+ } else if (IS_VENDOR_ID(words, "AuthenticAMD")) {
+ stash->vendor = VENDOR_AMD;
+ } else if (IS_VENDOR_ID(words, "CyrixInstead")) {
+ stash->vendor = VENDOR_CYRIX;
+ } else if (IS_VENDOR_ID(words, "CentaurHauls")) {
+ stash->vendor = VENDOR_VIA;
+ } else if (IS_VENDOR_ID(words, "UMC UMC UMC ")) {
+ stash->vendor = VENDOR_UMC;
+ } else if (IS_VENDOR_ID(words, "NexGenDriven")) {
+ stash->vendor = VENDOR_NEXGEN;
+ } else if (IS_VENDOR_ID(words, "RiseRiseRise")) {
+ stash->vendor = VENDOR_RISE;
+ } else if (IS_VENDOR_ID(words, "GenuineTMx86")) {
+ stash->vendor = VENDOR_TRANSMETA;
+ } else if (IS_VENDOR_ID(words, "SiS SiS SiS ")) {
+ stash->vendor = VENDOR_SIS;
+ } else if (IS_VENDOR_ID(words, "Geode by NSC")) {
+ stash->vendor = VENDOR_NSC;
+ } else if (IS_VENDOR_ID(words, "Vortex86 SoC")) {
+ stash->vendor = VENDOR_VORTEX;
+ } else if (IS_VENDOR_ID(words, "Genuine RDC")) {
+ stash->vendor = VENDOR_RDC;
+ } else if (IS_VENDOR_ID(words, "HygonGenuine")) {
+ stash->vendor = VENDOR_HYGON;
+ } else if (IS_VENDOR_ID(words, " Shanghai ")) {
+ stash->vendor = VENDOR_ZHAOXIN;
+ }
+ } else if (reg == 1) {
+ stash->val_1_eax = words[WORD_EAX];
+ stash->val_1_ebx = words[WORD_EBX];
+ stash->val_1_ecx = words[WORD_ECX];
+ stash->val_1_edx = words[WORD_EDX];
+ } else if (reg == 4) {
+ stash->saw_4 = TRUE;
+ if (try == 0) {
+ stash->val_4_eax = words[WORD_EAX];
+ }
+ } else if (reg == 0xb) {
+ stash->saw_b = TRUE;
+ if (try < LENGTH(stash->val_b_eax)) {
+ stash->val_b_eax[try] = words[WORD_EAX];
+ }
+ if (try < LENGTH(stash->val_b_ebx)) {
+ stash->val_b_ebx[try] = words[WORD_EBX];
+ }
+ } else if (reg == 0x17) {
+ if (try == 1) {
+ memcpy(&stash->soc_brand[0], words, sizeof(unsigned int)*WORD_NUM);
+ } else if (try == 2) {
+ memcpy(&stash->soc_brand[16], words, sizeof(unsigned
int)*WORD_NUM);
+ } else if (try == 3) {
+ memcpy(&stash->soc_brand[32], words, sizeof(unsigned
int)*WORD_NUM);
+ }
+ } else if (reg == 0x1f) {
+ stash->saw_1f = TRUE;
+ if (try < LENGTH(stash->val_1f_eax)) {
+ stash->val_1f_eax[try] = words[WORD_EAX];
+ }
+ if (try < LENGTH(stash->val_1f_ebx)) {
+ stash->val_1f_ebx[try] = words[WORD_EBX];
+ }
+ if (try < LENGTH(stash->val_1f_ecx)) {
+ stash->val_1f_ecx[try] = words[WORD_ECX];
+ }
+ } else if (IS_HYPERVISOR_LEAF(reg, 0)) {
+ stash->hypervisor = get_hypervisor(words);
+ } else if (reg == 0x80000001) {
+ stash->val_80000001_eax = words[WORD_EAX];
+ stash->val_80000001_ebx = words[WORD_EBX];
+ stash->val_80000001_ecx = words[WORD_ECX];
+ stash->val_80000001_edx = words[WORD_EDX];
+ } else if (reg == 0x80000002) {
+ memcpy(&stash->brand[0], words, sizeof(unsigned int)*WORD_NUM);
+ } else if (reg == 0x80000003) {
+ memcpy(&stash->brand[16], words, sizeof(unsigned int)*WORD_NUM);
+ } else if (reg == 0x80000004) {
+ memcpy(&stash->brand[32], words, sizeof(unsigned int)*WORD_NUM);
+ } else if (reg == 0x80000008) {
+ stash->val_80000008_ecx = words[WORD_ECX];
+ } else if (reg == 0x8000001e) {
+ stash->val_8000001e_ebx = words[WORD_EBX];
+ } else if (reg == 0x80860003) {
+ memcpy(&stash->transmeta_info[0], words,
+ sizeof(unsigned int)*WORD_NUM);
+ } else if (reg == 0x80860004) {
+ memcpy(&stash->transmeta_info[16], words,
+ sizeof(unsigned int)*WORD_NUM);
+ } else if (reg == 0x80860005) {
+ memcpy(&stash->transmeta_info[32], words,
+ sizeof(unsigned int)*WORD_NUM);
+ } else if (reg == 0x80860006) {
+ memcpy(&stash->transmeta_info[48], words,
+ sizeof(unsigned int)*WORD_NUM);
}
- } else if (IS_HYPERVISOR_LEAF(reg, 0)) {
- stash->hypervisor = get_hypervisor(words);
- } else if (reg == 0x80000008) {
- stash->val_80000008_ecx = words[WORD_ECX];
- } else if (reg == 0x8000001e) {
- stash->val_8000001e_ebx = words[WORD_EBX];
- } else if (reg == 0x80860003) {
- memcpy(&stash->transmeta_info[0], words, sizeof(unsigned int)*WORD_NUM);
- } else if (reg == 0x80860004) {
- memcpy(&stash->transmeta_info[16], words, sizeof(unsigned int)*WORD_NUM);
- } else if (reg == 0x80860005) {
- memcpy(&stash->transmeta_info[32], words, sizeof(unsigned int)*WORD_NUM);
- } else if (reg == 0x80860006) {
- memcpy(&stash->transmeta_info[48], words, sizeof(unsigned int)*WORD_NUM);
}
if (raw) {
print_reg_raw(reg, try, words);
} else if (reg == 0) {
- // max already set to words[WORD_EAX]
- stash->val_0_eax = words[WORD_EAX];
+ // max already set to words[WORD_EAX] in calling function
printf(" vendor_id = \"%-4.4s%-4.4s%-4.4s\"\n",
(const char*)&words[WORD_EBX],
(const char*)&words[WORD_EDX],
(const char*)&words[WORD_ECX]);
} else if (reg == 1) {
- print_1_eax(words[WORD_EAX], stash->vendor);
+ print_1_eax(words[WORD_EAX], (stash ? stash->vendor : VENDOR_UNKNOWN));
print_1_ebx(words[WORD_EBX]);
print_brand(words[WORD_EAX], words[WORD_EBX]);
print_1_edx(words[WORD_EDX]);
@@ -9506,24 +9559,34 @@
if (try == 0) {
printf(" cache and TLB information (2):\n");
}
- unsigned int word = 0;
- for (; word < 4; word++) {
- if ((words[word] & 0x80000000) == 0) {
- const unsigned char* bytes = (const unsigned char*)&words[word];
- unsigned int byte = (try == 0 && word == WORD_EAX ? 1
- : 0);
- for (; byte < 4; byte++) {
- print_2_byte(bytes[byte], stash->vendor, stash->val_1_eax);
- stash_intel_cache(stash, bytes[byte]);
+ if (stash) {
+ unsigned int word = 0;
+ for (; word < 4; word++) {
+ if ((words[word] & 0x80000000) == 0) {
+ const unsigned char* bytes = (const unsigned
char*)&words[word];
+ unsigned int byte = (try == 0 && word == WORD_EAX ? 1
+ :
0);
+ for (; byte < 4; byte++) {
+ print_2_byte(bytes[byte], stash->vendor, stash->val_1_eax);
+ stash_intel_cache(stash, bytes[byte]);
+ }
}
}
+ } else {
+ // Too many of the byte codes are vendor, family, or model dependent,
+ // so don't even try to decode.
+ print_reg_raw(reg, try, words);
}
} else if (reg == 3) {
- printf(" processor serial number ="
- " %04X-%04X-%04X-%04X-%04X-%04X\n",
- stash->val_1_eax >> 16, stash->val_1_eax & 0xffff,
- words[WORD_EDX] >> 16, words[WORD_EDX] & 0xffff,
- words[WORD_ECX] >> 16, words[WORD_ECX] & 0xffff);
+ if (stash) {
+ printf(" processor serial number ="
+ " %04X-%04X-%04X-%04X-%04X-%04X\n",
+ stash->val_1_eax >> 16, stash->val_1_eax & 0xffff,
+ words[WORD_EDX] >> 16, words[WORD_EDX] & 0xffff,
+ words[WORD_ECX] >> 16, words[WORD_ECX] & 0xffff);
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 4) {
if (try == 0) {
printf(" deterministic cache parameters (4):\n");
@@ -9605,17 +9668,13 @@
printf(" bytes required by XSAVE/XRSTOR area = 0x%08x
(%u)\n",
words[WORD_ECX], words[WORD_ECX]);
} else if (try == 1) {
- printf(" XSAVE features (0xd/1):\n");
print_d_1_eax(words[WORD_EAX]);
- printf(" SAVE area size in bytes "
- " = 0x%08x (%u)\n",
+ printf(" SAVE area size in bytes = 0x%08x
(%u)\n",
words[WORD_EBX], words[WORD_EBX]);
- printf(" IA32_XSS lower 32 bits valid bit field mask"
- " = 0x%08x\n",
- words[WORD_ECX]);
- printf(" IA32_XSS upper 32 bits valid bit field mask"
- " = 0x%08x\n",
- words[WORD_EDX]);
+ printf(" IA32_XSS valid bit field mask = 0x%08x%08x\n",
+ words[WORD_EDX], words[WORD_ECX]);
+ print_d_1_ecx(words[WORD_ECX]);
+ // edx could be used in the future, after ecx fills up.
} else if (try >= 2 && try < 63) {
print_d_n(words, try);
} else {
@@ -9732,12 +9791,23 @@
printf(" stepping id = 0x%08x (%u)\n",
words[WORD_EDX], words[WORD_EDX]);
} else if (try == 1) {
- memcpy(&stash->soc_brand[0], words, sizeof(unsigned int)*WORD_NUM);
+ if (stash) {
+ // DO NOTHING: saved in soc_brand above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (try == 2) {
- memcpy(&stash->soc_brand[16], words, sizeof(unsigned int)*WORD_NUM);
+ if (stash) {
+ // DO NOTHING: saved in soc_brand above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (try == 3) {
- memcpy(&stash->soc_brand[32], words, sizeof(unsigned int)*WORD_NUM);
- printf(" SoC brand = \"%s\"\n", stash->soc_brand);
+ if (stash) {
+ printf(" SoC brand = \"%s\"\n", stash->soc_brand);
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else {
print_reg_raw(reg, try, words);
}
@@ -9754,7 +9824,7 @@
print_19_ebx(words[WORD_EBX]);
print_19_ecx(words[WORD_ECX]);
} else if (reg == 0x1a) {
- printf(" Hybrid Information (0x1a/0):\n");
+ printf(" Native Model ID Information (0x1a/0):\n");
print_1a_0_eax(words[WORD_EAX]);
} else if (reg == 0x1b) {
printf(" PCONFIG information (0x1b/0x%x):\n", try);
@@ -9821,14 +9891,15 @@
} else if (try == 2) {
// All reserved
} else if (try == 3) {
- printf(" Architecture Performance Monitoring Extended Supported
Events"
+ printf(" Architecture Performance Monitoring"
+ " Extended Supported Events"
" (0x23/3):\n");
print_23_3_eax(words[WORD_EAX]);
} else {
print_reg_raw(reg, try, words);
}
} else if (reg == 0x20000000) {
- // max already set to words[WORD_EAX]
+ // max already set to words[WORD_EAX] in calling function
} else if (reg == 0x20000001) {
print_20000001_edx(words[WORD_EDX]);
} else if (IS_HYPERVISOR_LEAF(reg, 0)) {
@@ -9838,25 +9909,25 @@
print_esc_substring((const char*)&words[WORD_EDX], sizeof(words[0]));
printf("\"\n");
} else if (IS_HYPERVISOR_LEAF(reg, 1)
- && stash->hypervisor == HYPERVISOR_XEN) {
+ && stash && stash->hypervisor == HYPERVISOR_XEN) {
printf(" hypervisor version (0x%08x/eax):\n", reg);
printf(" version = %d.%d\n",
BIT_EXTRACT_LE(words[WORD_EAX], 16, 32),
BIT_EXTRACT_LE(words[WORD_EAX], 0, 16));
} else if (IS_HYPERVISOR_LEAF(reg, 1)
- && stash->hypervisor == HYPERVISOR_KVM) {
+ && stash && stash->hypervisor == HYPERVISOR_KVM) {
print_hypervisor_1_eax_kvm(reg, words[WORD_EAX]);
print_hypervisor_1_edx_kvm(reg, words[WORD_EDX]);
} else if (IS_HYPERVISOR_LEAF(reg, 1)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor interface identification (0x%08x/eax):\n", reg);
printf(" version = \"%-4.4s\"\n",
(const char*)&words[WORD_EAX]);
} else if (IS_HYPERVISOR_LEAF(reg, 1)
- && stash->hypervisor == HYPERVISOR_ACRN) {
+ && stash && stash->hypervisor == HYPERVISOR_ACRN) {
print_hypervisor_1_eax_acrn(reg, words[WORD_EAX]);
} else if (IS_HYPERVISOR_LEAF(reg, 2)
- && stash->hypervisor == HYPERVISOR_XEN) {
+ && stash && stash->hypervisor == HYPERVISOR_XEN) {
printf(" hypervisor features (0x%08x):\n", reg);
printf(" number of hypercall-transfer pages = 0x%0x (%u)\n",
words[WORD_EAX], words[WORD_EAX]);
@@ -9864,7 +9935,7 @@
words[WORD_EBX]);
print_hypervisor_2_ecx_xen(words[WORD_ECX]);
} else if (IS_HYPERVISOR_LEAF(reg, 2)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor system identity (0x%08x):\n", reg);
printf(" build = %d\n", words[WORD_EAX]);
printf(" version = %d.%d\n",
@@ -9875,7 +9946,8 @@
BIT_EXTRACT_LE(words[WORD_EDX], 24, 32));
printf(" service number = %d\n",
BIT_EXTRACT_LE(words[WORD_EDX], 0, 24));
- } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash->hypervisor == HYPERVISOR_XEN
+ } else if (IS_HYPERVISOR_LEAF(reg, 3)
+ && stash && stash->hypervisor == HYPERVISOR_XEN
&& try == 0) {
printf(" hypervisor time features (0x%08x/00):\n", reg);
print_hypervisor_3_eax_xen(words[WORD_EAX]);
@@ -9885,7 +9957,8 @@
words[WORD_ECX]);
printf(" incarnation = 0x%0x (%u)\n",
words[WORD_EDX], words[WORD_EDX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash->hypervisor == HYPERVISOR_XEN
+ } else if (IS_HYPERVISOR_LEAF(reg, 3)
+ && stash && stash->hypervisor == HYPERVISOR_XEN
&& try == 1) {
printf(" hypervisor time scale & offset (0x%08x/01):\n", reg);
unsigned long long vtsc_offset
@@ -9896,31 +9969,37 @@
words[WORD_ECX], words[WORD_ECX]);
printf(" vtsc shift = 0x%0x (%u)\n",
words[WORD_EDX], words[WORD_EDX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash->hypervisor == HYPERVISOR_XEN
+ } else if (IS_HYPERVISOR_LEAF(reg, 3)
+ && stash && stash->hypervisor == HYPERVISOR_XEN
&& try == 2) {
printf(" hypervisor time physical cpu frequency (0x%08x/02):\n", reg);
printf(" cpu frequency (kHZ) = %u\n", words[WORD_EAX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash->hypervisor ==
HYPERVISOR_MICROSOFT) {
+ } else if (IS_HYPERVISOR_LEAF(reg, 3)
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
print_hypervisor_3_eax_microsoft(reg, words[WORD_EAX]);
print_hypervisor_3_ebx_microsoft(reg, words[WORD_EBX]);
print_hypervisor_3_ecx_microsoft(reg, words[WORD_ECX]);
print_hypervisor_3_edx_microsoft(reg, words[WORD_EDX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 4) && stash->hypervisor ==
HYPERVISOR_XEN) {
+ } else if (IS_HYPERVISOR_LEAF(reg, 4)
+ && stash && stash->hypervisor == HYPERVISOR_XEN) {
print_hypervisor_4_eax_xen(reg, words[WORD_EAX]);
printf(" vcpu id = 0x%x (%u)\n",
words[WORD_EBX], words[WORD_EBX]);
printf(" domain id = 0x%x (%u)\n",
words[WORD_ECX], words[WORD_ECX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 4) && stash->hypervisor ==
HYPERVISOR_MICROSOFT) {
+ } else if (IS_HYPERVISOR_LEAF(reg, 4)
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor recommendations (0x%08x/eax):\n", reg);
print_hypervisor_4_eax_microsoft(words[WORD_EAX]);
print_hypervisor_4_ecx_microsoft(words[WORD_ECX]);
printf(" maximum number of spinlock retry attempts = 0x%0x (%u)\n",
words[WORD_EBX], words[WORD_EBX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 5) && stash->hypervisor == HYPERVISOR_XEN
+ } else if (IS_HYPERVISOR_LEAF(reg, 5)
+ && stash && stash->hypervisor == HYPERVISOR_XEN
&& try == 0) {
print_hypervisor_5_0_ebx_xen(reg, words[WORD_EBX]);
- } else if (IS_HYPERVISOR_LEAF(reg, 5) && stash->hypervisor ==
HYPERVISOR_MICROSOFT) {
+ } else if (IS_HYPERVISOR_LEAF(reg, 5)
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor implementation limits (0x%08x):\n", reg);
printf(" maximum number of virtual processors "
" = 0x%0x (%u)\n",
@@ -9932,30 +10011,30 @@
" = 0x%0x (%u)\n",
words[WORD_ECX], words[WORD_ECX]);
} else if (IS_HYPERVISOR_LEAF(reg, 6)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
print_hypervisor_6_eax_microsoft(reg, words[WORD_EAX]);
} else if (IS_HYPERVISOR_LEAF(reg, 7)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor root partition enlightenments (0x%08x):\n", reg);
print_hypervisor_7_eax_microsoft(words[WORD_EAX]);
print_hypervisor_7_ebx_microsoft(words[WORD_EBX]);
print_hypervisor_7_ecx_microsoft(words[WORD_ECX]);
} else if (IS_HYPERVISOR_LEAF(reg, 8)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor shared virtual memory (0x%08x):\n", reg);
print_hypervisor_8_eax_microsoft(words[WORD_EAX]);
} else if (IS_HYPERVISOR_LEAF(reg, 9)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor nested hypervisor features (0x%08x):\n", reg);
print_hypervisor_9_eax_microsoft(words[WORD_EAX]);
print_hypervisor_9_edx_microsoft(words[WORD_EDX]);
} else if (IS_HYPERVISOR_LEAF(reg, 0xa)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor nested virtualization features (0x%08x):\n", reg);
print_hypervisor_a_eax_microsoft(words[WORD_EAX]);
print_hypervisor_a_ebx_microsoft(words[WORD_EBX]);
} else if (IS_HYPERVISOR_LEAF(reg, 0xc)
- && stash->hypervisor == HYPERVISOR_MICROSOFT) {
+ && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) {
printf(" hypervisor isolation configuration (0x%08x):\n", reg);
print_hypervisor_c_eax_microsoft(words[WORD_EAX]);
print_hypervisor_c_ebx_microsoft(words[WORD_EBX]);
@@ -9986,23 +10065,34 @@
" (0x%08x):\n", reg);
print_hypervisor_82_eax_microsoft(words[WORD_EAX]);
} else if (reg == 0x80000000) {
- // max already set to words[WORD_EAX]
+ // max already set to words[WORD_EAX] in calling function
} else if (reg == 0x80000001) {
- print_80000001_eax(words[WORD_EAX], stash->vendor);
- print_80000001_edx(words[WORD_EDX], stash->vendor);
- print_80000001_ebx(words[WORD_EBX], stash->vendor, stash->val_1_eax);
- print_80000001_ecx(words[WORD_ECX], stash->vendor);
- stash->val_80000001_eax = words[WORD_EAX];
- stash->val_80000001_ebx = words[WORD_EBX];
- stash->val_80000001_ecx = words[WORD_ECX];
- stash->val_80000001_edx = words[WORD_EDX];
+ if (stash) {
+ print_80000001_eax(words[WORD_EAX], stash->vendor);
+ print_80000001_edx(words[WORD_EDX], stash->vendor);
+ print_80000001_ebx(words[WORD_EBX], stash->vendor, stash->val_1_eax);
+ print_80000001_ecx(words[WORD_ECX], stash->vendor);
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80000002) {
- memcpy(&stash->brand[0], words, sizeof(unsigned int)*WORD_NUM);
+ if (stash) {
+ // DO NOTHING: saved in brand above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80000003) {
- memcpy(&stash->brand[16], words, sizeof(unsigned int)*WORD_NUM);
+ if (stash) {
+ // DO NOTHING: saved in brand above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80000004) {
- memcpy(&stash->brand[32], words, sizeof(unsigned int)*WORD_NUM);
- printf(" brand = \"%s\"\n", stash->brand);
+ if (stash) {
+ printf(" brand = \"%s\"\n", stash->brand);
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80000005) {
print_80000005_eax(words[WORD_EAX]);
print_80000005_ebx(words[WORD_EBX]);
@@ -10021,15 +10111,17 @@
print_80000008_eax(words[WORD_EAX]);
print_80000008_ebx(words[WORD_EBX], stash);
printf(" Size Identifiers (0x80000008/ecx):\n");
- unsigned int num_thrs = BIT_EXTRACT_LE(stash->val_80000008_ecx, 0, 8);
- if (Synth_Family(stash->val_80000001_eax) > 0x16) {
- printf(" number of threads = 0x%llx (%llu)\n",
- (unsigned long long)num_thrs + 1ULL,
- (unsigned long long)num_thrs + 1ULL);
- } else {
- printf(" number of CPU cores = 0x%llx (%llu)\n",
- (unsigned long long)num_thrs + 1ULL,
- (unsigned long long)num_thrs + 1ULL);
+ if (stash) {
+ unsigned int num_thrs = BIT_EXTRACT_LE(stash->val_80000008_ecx, 0,
8);
+ if (Synth_Family(stash->val_80000001_eax) > 0x16) {
+ printf(" number of threads = 0x%llx
(%llu)\n",
+ (unsigned long long)num_thrs + 1ULL,
+ (unsigned long long)num_thrs + 1ULL);
+ } else {
+ printf(" number of CPU cores = 0x%llx
(%llu)\n",
+ (unsigned long long)num_thrs + 1ULL,
+ (unsigned long long)num_thrs + 1ULL);
+ }
}
print_80000008_ecx(words[WORD_ECX]);
print_80000008_edx(words[WORD_EDX]);
@@ -10066,10 +10158,12 @@
print_8000001d_synth(words);
} else if (reg == 0x8000001e) {
printf(" extended APIC ID = %u\n", words[WORD_EAX]);
- if (Synth_Family(stash->val_80000001_eax) > 0x16) {
- print_8000001e_ebx_gt_f16(words[WORD_EBX]);
- } else {
- print_8000001e_ebx_f16(words[WORD_EBX]);
+ if (stash) {
+ if (Synth_Family(stash->val_80000001_eax) > 0x16) {
+ print_8000001e_ebx_gt_f16(words[WORD_EBX]);
+ } else {
+ print_8000001e_ebx_f16(words[WORD_EBX]);
+ }
}
print_8000001e_ecx(words[WORD_ECX]);
} else if (reg == 0x8000001f) {
@@ -10084,7 +10178,6 @@
if (try == 0) {
printf(" PQoS Enforcement (0x80000020):\n");
print_80000020_0_ebx(words[WORD_EBX]);
- print_80000020_0_ecx(words[WORD_ECX]);
} else if (try == 1) {
printf(" PQoS Enforcement for L3 External Bandwidth"
" (0x80000020/1):\n");
@@ -10125,6 +10218,9 @@
/* Similar to 0xb & 0x1f, but with extra bit fields */
if (try == 0) {
printf(" AMD Extended CPU Topology (0x80000026):\n");
+ // This is invariant across subleaves, so print it only once
+ printf(" extended APIC ID = %u\n",
+ words[WORD_EDX]);
}
printf(" --- level %d ---\n", try);
print_80000026_ecx(words[WORD_ECX]);
@@ -10150,13 +10246,29 @@
(words[WORD_EBX] >> 0) & 0xff,
words[WORD_ECX]);
} else if (reg == 0x80860003) {
- // DO NOTHING
+ if (stash) {
+ // DO NOTHING: saved in transmeta_info above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80860004) {
- // DO NOTHING
+ if (stash) {
+ // DO NOTHING: saved in transmeta_info above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80860005) {
- // DO NOTHING
+ if (stash) {
+ // DO NOTHING: saved in transmeta_info above
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80860006) {
- printf(" Transmeta information = \"%s\"\n", stash->transmeta_info);
+ if (stash) {
+ printf(" Transmeta information = \"%s\"\n", stash->transmeta_info);
+ } else {
+ print_reg_raw(reg, try, words);
+ }
} else if (reg == 0x80860007) {
printf(" Transmeta core clock frequency = %u MHz\n",
words[WORD_EAX]);
@@ -10169,7 +10281,7 @@
} else if (reg == 0xc0000000) {
// max already set to words[WORD_EAX]
} else if (reg == 0xc0000001) {
- if (stash->vendor == VENDOR_VIA) {
+ if (stash && stash->vendor == VENDOR_VIA) {
/* TODO: figure out how to decode 0xc0000001:eax */
printf(" 0x%08x 0x%02x: eax=0x%08x\n",
(unsigned int)reg, try, words[WORD_EAX]);
@@ -10178,7 +10290,7 @@
print_reg_raw(reg, try, words);
}
} else if (reg == 0xc0000002) {
- if (stash->vendor == VENDOR_VIA) {
+ if (stash && stash->vendor == VENDOR_VIA) {
printf(" VIA C7 Current Performance Data (0xc0000002):\n");
if (BIT_EXTRACT_LE(words[WORD_EAX], 0, 8) != 0) {
printf(" core temperature (degrees C) = %f\n",
@@ -10194,7 +10306,7 @@
print_reg_raw(reg, try, words);
}
} else if (reg == 0xc0000004) {
- if (stash->vendor == VENDOR_VIA) {
+ if (stash && stash->vendor == VENDOR_VIA) {
printf(" VIA Temperature (0xc0000004/eax):\n");
print_c0000004_eax(words[WORD_EAX]);
printf(" VIA MSR 198 Mirror (0xc0000004):\n");
@@ -10334,7 +10446,7 @@
} else {
#ifdef USE_CPUID_MODULE
int cpuid_fd = -1;
- char cpuid_name[20];
+ char cpuid_name[32];
if (cpuid_fd == -1 && cpu == 0) {
cpuid_fd = open("/dev/cpuid", O_RDONLY);
@@ -10509,8 +10621,7 @@
unsigned int cpu;
for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
- int cpuid_fd = -1;
- code_stash_t stash = NIL_STASH;
+ int cpuid_fd = -1;
if (one_cpu && cpu > 0) break;
@@ -10525,7 +10636,7 @@
unsigned int words[WORD_NUM];
real_get(cpuid_fd, reg, words, try, FALSE);
- print_reg(reg, words, raw, try, &stash);
+ print_reg(reg, words, raw, try, NULL);
}
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221201/cpuid.man new/cpuid-20230120/cpuid.man
--- old/cpuid-20221201/cpuid.man 2022-12-01 12:39:18.000000000 +0100
+++ new/cpuid-20230120/cpuid.man 2023-01-20 13:30:19.000000000 +0100
@@ -1,7 +1,7 @@
.\"
-.\" $Id: cpuid.man,v 20221201 2022/12/01 04:38:20 todd $
+.\" $Id: cpuid.man,v 20230120 2023/01/20 05:30:01 todd $
.\"
-.TH CPUID 1 "1 Dec 2022" "20221201"
+.TH CPUID 1 "20 Jan 2023" "20230120"
.SH NAME
cpuid \- Dump CPUID information for each CPU
.SH SYNOPSIS
@@ -523,6 +523,10 @@
Supporting 12th Generation Intel Core Processor for S Processor Line Platforms,
formerly known as Alder Lake
.br
+743844: 13th Generation Intel Core Processors Datasheet, Volume 1 of 2
+Supporting 13th Generation Intel Core Processor for S/P/PX/H/HX/U Processor
Line
+Platforms, formerly known as Raptor Lake
+.br
Intel Microcode Update Guidance
.br
Branch History Injection and Intra-mode Branch Target Injection /
@@ -619,6 +623,18 @@
55772-A1: Processor Programming Reference (PPR) for AMD Family 17h Model 20h,
Revision A1 Processors
.br
+55898: Preliminary Processor Programming Reference (PPR) for AMD Family 19h
+Model 01h, Revision B1 Processors
+.br
+56214: Processor Programming Reference (PPR) for AMD Family 19h Model 21h,
+Revision B0 Processors
+.br
+56569: Processor Programming Reference (PPR) for AMD Family 19h Model 51h,
+Revision A1 Processors
+.br
+55901: Preliminary Processor Programming Reference (PPR) for AMD Family 19h
+Model 11h, Revision B1 Processors
+.br
55922-A1: Processor Programming Reference (PPR) for AMD Family 17h Model 60h,
Revision A1 Processors
.br
@@ -630,6 +646,8 @@
.br
56375: AMD64 Technology Platform Quality of Service Extensions
.br
+57095: Revision Guide for AMD Family 19h Models 10h-1Fh Processors
+.br
AMD64 Technology Indirect Branch Control Extension (White Paper),
Revision 4.10.18
.br
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221201/cpuid.spec
new/cpuid-20230120/cpuid.spec
--- old/cpuid-20221201/cpuid.spec 2022-12-01 12:41:02.000000000 +0100
+++ new/cpuid-20230120/cpuid.spec 2023-01-20 14:28:48.000000000 +0100
@@ -1,4 +1,4 @@
-%define version 20221201
+%define version 20230120
%define release 1
Summary: dumps CPUID information about the CPU(s)
Name: cpuid
