Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package spirv-headers for openSUSE:Factory checked in at 2023-03-31 21:13:58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/spirv-headers (Old) and /work/SRC/openSUSE:Factory/.spirv-headers.new.31432 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "spirv-headers" Fri Mar 31 21:13:58 2023 rev:35 rq:1075345 version:1.6.1+sdk243 Changes: -------- --- /work/SRC/openSUSE:Factory/spirv-headers/spirv-headers.changes 2023-01-30 17:16:40.858372599 +0100 +++ /work/SRC/openSUSE:Factory/.spirv-headers.new.31432/spirv-headers.changes 2023-03-31 21:14:00.590048094 +0200 @@ -1,0 +2,9 @@ +Wed Mar 29 18:40:35 UTC 2023 - Jan Engelhardt <jeng...@inai.de> + +- Update to release 1.6.1/SDK-1.3.243.0 + * Added SPRIV_INTEL_argument_interfaces, RegisterMapInterfaceINTEL, + SPV_QCOM_image_processing + * Added support for SPV_INTEL_fpga_latency_control extension + * Headers support for SPV_INTEL_bfloat16_conversion + +------------------------------------------------------------------- Old: ---- sdk-1.3.239.0.tar.gz New: ---- sdk-1.3.243.0.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ spirv-headers.spec ++++++ --- /var/tmp/diff_new_pack.hBJRUC/_old 2023-03-31 21:14:01.126050006 +0200 +++ /var/tmp/diff_new_pack.hBJRUC/_new 2023-03-31 21:14:01.130050019 +0200 @@ -24,13 +24,14 @@ # and the independently increasing toolchain release number (239). Name: spirv-headers -Version: 1.6.1+sdk239 +Version: 1.6.1+sdk243 +%define innerver 1.3.243.0 Release: 0 Summary: Machine-readable files from the SPIR-V registry License: MIT Group: Development/Libraries/C and C++ URL: https://github.com/KhronosGroup/SPIRV-Headers -Source: https://github.com/KhronosGroup/SPIRV-Headers/archive/sdk-1.3.239.0.tar.gz +Source: https://github.com/KhronosGroup/SPIRV-Headers/archive/sdk-%innerver.tar.gz BuildArch: noarch BuildRequires: cmake >= 2.8 BuildRequires: fdupes @@ -47,7 +48,7 @@ * The XML registry file. %prep -%autosetup -n SPIRV-Headers-sdk-1.3.239.0 +%autosetup -n SPIRV-Headers-sdk-%innerver %build %cmake ++++++ sdk-1.3.239.0.tar.gz -> sdk-1.3.243.0.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/NonSemanticDebugBreak.h new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/NonSemanticDebugBreak.h --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/NonSemanticDebugBreak.h 1970-01-01 01:00:00.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/NonSemanticDebugBreak.h 2023-03-08 18:22:35.000000000 +0100 @@ -0,0 +1,50 @@ +// Copyright (c) 2020 The Khronos Group Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and/or associated documentation files (the +// "Materials"), to deal in the Materials without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Materials, and to +// permit persons to whom the Materials are furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Materials. +// +// MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS +// KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS +// SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT +// https://www.khronos.org/registry/ +// +// THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. +// + +#ifndef SPIRV_UNIFIED1_NonSemanticDebugBreak_H_ +#define SPIRV_UNIFIED1_NonSemanticDebugBreak_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + NonSemanticDebugBreakRevision = 1, + NonSemanticDebugBreakRevision_BitWidthPadding = 0x7fffffff +}; + +enum NonSemanticDebugBreakInstructions { + NonSemanticDebugBreakDebugBreak = 1, + NonSemanticDebugBreakInstructionsMax = 0x7fffffff +}; + + +#ifdef __cplusplus +} +#endif + +#endif // SPIRV_UNIFIED1_NonSemanticDebugBreak_H_ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json 1970-01-01 01:00:00.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/extinst.nonsemantic.debugbreak.grammar.json 2023-03-08 18:22:35.000000000 +0100 @@ -0,0 +1,9 @@ +{ + "revision" : 1, + "instructions" : [ + { + "opname" : "DebugBreak", + "opcode" : 1 + } + ] +} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.bf new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.bf --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.bf 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.bf 2023-03-08 18:22:35.000000000 +0100 @@ -193,6 +193,7 @@ NumSIMDWorkitemsINTEL = 5896, SchedulerTargetFmaxMhzINTEL = 5903, StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, } @@ -507,6 +508,8 @@ MaxByteOffsetId = 47, NoSignedWrap = 4469, NoUnsignedWrap = 4470, + WeightTextureQCOM = 4487, + BlockMatchTextureQCOM = 4488, ExplicitInterpAMD = 4999, OverrideCoverageNV = 5248, PassthroughNV = 5250, @@ -575,6 +578,17 @@ SingleElementVectorINTEL = 6085, VectorComputeCallableFunctionINTEL = 6087, MediaBlockIOINTEL = 6140, + LatencyControlLabelINTEL = 6172, + LatencyControlConstraintINTEL = 6173, + ConduitKernelArgumentINTEL = 6175, + RegisterMapKernelArgumentINTEL = 6176, + MMHostInterfaceAddressWidthINTEL = 6177, + MMHostInterfaceDataWidthINTEL = 6178, + MMHostInterfaceLatencyINTEL = 6179, + MMHostInterfaceReadWriteModeINTEL = 6180, + MMHostInterfaceMaxBurstINTEL = 6181, + MMHostInterfaceWaitRequestINTEL = 6182, + StableKernelArgumentINTEL = 6183, } [AllowDuplicates, CRepr] public enum BuiltIn @@ -1010,6 +1024,9 @@ RayQueryKHR = 4472, RayTraversalPrimitiveCullingKHR = 4478, RayTracingKHR = 4479, + TextureSampleWeightedQCOM = 4484, + TextureBoxFilterQCOM = 4485, + TextureBlockMatchQCOM = 4486, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, FragmentMaskAMD = 5010, @@ -1137,7 +1154,11 @@ OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, + FPGAKernelAttributesv2INTEL = 6161, + FPGALatencyControlINTEL = 6171, + FPGAArgumentInterfacesINTEL = 6174, GroupUniformArithmeticKHR = 6400, } @@ -1624,6 +1645,10 @@ OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryProceedKHR = 4477, OpRayQueryGetIntersectionTypeKHR = 4479, + OpImageSampleWeightedQCOM = 4480, + OpImageBoxFilterQCOM = 4481, + OpImageBlockMatchSSDQCOM = 4482, + OpImageBlockMatchSADQCOM = 4483, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -1941,6 +1966,8 @@ OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.core.grammar.json new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.core.grammar.json --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.core.grammar.json 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.core.grammar.json 2023-03-08 18:22:35.000000000 +0100 @@ -4593,6 +4593,66 @@ "version" : "None" }, { + "opname" : "OpImageSampleWeightedQCOM", + "class" : "Image", + "opcode" : 4480, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Texture'" }, + { "kind" : "IdRef", "name" : "'Coordinates'" }, + { "kind" : "IdRef", "name" : "'Weights'" } + ], + "capabilities" : [ "TextureSampleWeightedQCOM" ], + "version" : "None" + }, + { + "opname" : "OpImageBoxFilterQCOM", + "class" : "Image", + "opcode" : 4481, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Texture'" }, + { "kind" : "IdRef", "name" : "'Coordinates'" }, + { "kind" : "IdRef", "name" : "'Box Size'" } + ], + "capabilities" : [ "TextureBoxFilterQCOM" ], + "version" : "None" + }, + { + "opname" : "OpImageBlockMatchSSDQCOM", + "class" : "Image", + "opcode" : 4482, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Target'" }, + { "kind" : "IdRef", "name" : "'Target Coordinates'" }, + { "kind" : "IdRef", "name" : "'Reference'" }, + { "kind" : "IdRef", "name" : "'Reference Coordinates'" }, + { "kind" : "IdRef", "name" : "'Block Size'" } + ], + "capabilities" : [ "TextureBlockMatchQCOM" ], + "version" : "None" + }, + { + "opname" : "OpImageBlockMatchSADQCOM", + "class" : "Image", + "opcode" : 4483, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Target'" }, + { "kind" : "IdRef", "name" : "'Target Coordinates'" }, + { "kind" : "IdRef", "name" : "'Reference'" }, + { "kind" : "IdRef", "name" : "'Reference Coordinates'" }, + { "kind" : "IdRef", "name" : "'Block Size'" } + ], + "capabilities" : [ "TextureBlockMatchQCOM" ], + "version" : "None" + }, + { "opname" : "OpGroupIAddNonUniformAMD", "class" : "Group", "opcode" : 5000, @@ -4751,7 +4811,6 @@ { "kind" : "IdScope", "name" : "'Scope'" } ], "capabilities" : [ "ShaderClockKHR" ], - "extensions" : [ "SPV_KHR_shader_clock" ], "version" : "None" }, { @@ -9045,6 +9104,30 @@ "version" : "None" }, { + "opname" : "OpConvertFToBF16INTEL", + "class" : "Conversion", + "opcode" : 6116, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Float Value'" } + ], + "capabilities" : [ "BFloat16ConversionINTEL" ], + "version" : "None" + }, + { + "opname" : "OpConvertBF16ToFINTEL", + "class" : "Conversion", + "opcode" : 6117, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'BFloat16 Value'" } + ], + "capabilities" : [ "BFloat16ConversionINTEL" ], + "version" : "None" + }, + { "opname" : "OpControlBarrierArriveINTEL", "class" : "Barrier", "opcode" : 6142, @@ -10717,6 +10800,15 @@ "version" : "None" }, { + "enumerant" : "RegisterMapInterfaceINTEL", + "value" : 6160, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'WaitForDoneWrite'" } + ], + "capabilities" : [ "FPGAKernelAttributesv2INTEL" ], + "version" : "None" + }, + { "enumerant" : "NamedBarrierCountINTEL", "value" : 6417, "parameters" : [ @@ -11988,6 +12080,18 @@ "version" : "1.4" }, { + "enumerant" : "WeightTextureQCOM", + "value" : 4487, + "extensions" : [ "SPV_QCOM_image_processing" ], + "version" : "None" + }, + { + "enumerant" : "BlockMatchTextureQCOM", + "value" : 4488, + "extensions" : [ "SPV_QCOM_image_processing" ], + "version" : "None" + }, + { "enumerant" : "ExplicitInterpAMD", "value" : 4999, "extensions" : [ "SPV_AMD_shader_explicit_vertex_parameter" ], @@ -12517,6 +12621,98 @@ "value" : 6140, "capabilities" : [ "VectorComputeINTEL" ], "version" : "None" + }, + { + "enumerant" : "LatencyControlLabelINTEL", + "value" : 6172, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Latency Label'" } + ], + "capabilities" : [ "FPGALatencyControlINTEL" ], + "version" : "None" + }, + { + "enumerant" : "LatencyControlConstraintINTEL", + "value" : 6173, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Relative To'" }, + { "kind" : "LiteralInteger", "name" : "'Control Type'" }, + { "kind" : "LiteralInteger", "name" : "'Relative Cycle'" } + ], + "capabilities" : [ "FPGALatencyControlINTEL" ], + "version" : "None" + }, + { + "enumerant" : "ConduitKernelArgumentINTEL", + "value" : 6175, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "version" : "None" + }, + { + "enumerant" : "RegisterMapKernelArgumentINTEL", + "value" : 6176, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "version" : "None" + }, + { + "enumerant" : "MMHostInterfaceAddressWidthINTEL", + "value" : 6177, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'AddressWidth'" } + ], + "version" : "None" + }, + { + "enumerant" : "MMHostInterfaceDataWidthINTEL", + "value" : 6178, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'DataWidth'" } + ], + "version" : "None" + }, + { + "enumerant" : "MMHostInterfaceLatencyINTEL", + "value" : 6179, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Latency'" } + ], + "version" : "None" + }, + { + "enumerant" : "MMHostInterfaceReadWriteModeINTEL", + "value" : 6180, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "parameters" : [ + { "kind" : "AccessQualifier", "name" : "'ReadWriteMode'" } + ], + "version" : "None" + }, + { + "enumerant" : "MMHostInterfaceMaxBurstINTEL", + "value" : 6181, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'MaxBurstCount'" } + ], + "version" : "None" + }, + { + "enumerant" : "MMHostInterfaceWaitRequestINTEL", + "value" : 6182, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Waitrequest'" } + ], + "version" : "None" + }, + { + "enumerant" : "StableKernelArgumentINTEL", + "value" : 6183, + "capabilities" : [ "FPGAArgumentInterfacesINTEL" ], + "version" : "None" } ] }, @@ -14012,6 +14208,24 @@ "version" : "None" }, { + "enumerant" : "TextureSampleWeightedQCOM", + "value" : 4484, + "extensions" : [ "SPV_QCOM_image_processing" ], + "version" : "None" + }, + { + "enumerant" : "TextureBoxFilterQCOM", + "value" : 4485, + "extensions" : [ "SPV_QCOM_image_processing" ], + "version" : "None" + }, + { + "enumerant" : "TextureBlockMatchQCOM", + "value" : 4486, + "extensions" : [ "SPV_QCOM_image_processing" ], + "version" : "None" + }, + { "enumerant" : "Float16ImageAMD", "value" : 5008, "capabilities" : [ "Shader" ], @@ -14056,7 +14270,6 @@ { "enumerant" : "ShaderClockKHR", "value" : 5055, - "capabilities" : [ "Shader" ], "extensions" : [ "SPV_KHR_shader_clock" ], "version" : "None" }, @@ -14818,12 +15031,37 @@ "version" : "None" }, { + "enumerant" : "BFloat16ConversionINTEL", + "value" : 6115, + "extensions" : [ "SPV_INTEL_bfloat16_conversion" ], + "version" : "None" + }, + { "enumerant" : "SplitBarrierINTEL", "value" : 6141, "extensions" : [ "SPV_INTEL_split_barrier" ], "version" : "None" }, { + "enumerant" : "FPGAKernelAttributesv2INTEL", + "value" : 6161, + "capabilities" : [ "FPGAKernelAttributesINTEL" ], + "extensions" : [ "SPV_INTEL_kernel_attributes" ], + "version" : "None" + }, + { + "enumerant" : "FPGALatencyControlINTEL", + "value" : 6171, + "extensions" : [ "SPV_INTEL_fpga_latency_control" ], + "version" : "None" + }, + { + "enumerant" : "FPGAArgumentInterfacesINTEL", + "value" : 6174, + "extensions" : [ "SPV_INTEL_fpga_argument_interfaces" ], + "version" : "None" + }, + { "enumerant" : "GroupUniformArithmeticKHR", "value" : 6400, "extensions" : [ "SPV_KHR_uniform_group_instructions"], diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.cs new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.cs --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.cs 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.cs 2023-03-08 18:22:35.000000000 +0100 @@ -192,6 +192,7 @@ NumSIMDWorkitemsINTEL = 5896, SchedulerTargetFmaxMhzINTEL = 5903, StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, } @@ -506,6 +507,8 @@ MaxByteOffsetId = 47, NoSignedWrap = 4469, NoUnsignedWrap = 4470, + WeightTextureQCOM = 4487, + BlockMatchTextureQCOM = 4488, ExplicitInterpAMD = 4999, OverrideCoverageNV = 5248, PassthroughNV = 5250, @@ -574,6 +577,17 @@ SingleElementVectorINTEL = 6085, VectorComputeCallableFunctionINTEL = 6087, MediaBlockIOINTEL = 6140, + LatencyControlLabelINTEL = 6172, + LatencyControlConstraintINTEL = 6173, + ConduitKernelArgumentINTEL = 6175, + RegisterMapKernelArgumentINTEL = 6176, + MMHostInterfaceAddressWidthINTEL = 6177, + MMHostInterfaceDataWidthINTEL = 6178, + MMHostInterfaceLatencyINTEL = 6179, + MMHostInterfaceReadWriteModeINTEL = 6180, + MMHostInterfaceMaxBurstINTEL = 6181, + MMHostInterfaceWaitRequestINTEL = 6182, + StableKernelArgumentINTEL = 6183, } public enum BuiltIn @@ -1009,6 +1023,9 @@ RayQueryKHR = 4472, RayTraversalPrimitiveCullingKHR = 4478, RayTracingKHR = 4479, + TextureSampleWeightedQCOM = 4484, + TextureBoxFilterQCOM = 4485, + TextureBlockMatchQCOM = 4486, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, FragmentMaskAMD = 5010, @@ -1136,7 +1153,11 @@ OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, + FPGAKernelAttributesv2INTEL = 6161, + FPGALatencyControlINTEL = 6171, + FPGAArgumentInterfacesINTEL = 6174, GroupUniformArithmeticKHR = 6400, } @@ -1623,6 +1644,10 @@ OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryProceedKHR = 4477, OpRayQueryGetIntersectionTypeKHR = 4479, + OpImageSampleWeightedQCOM = 4480, + OpImageBoxFilterQCOM = 4481, + OpImageBlockMatchSSDQCOM = 4482, + OpImageBlockMatchSADQCOM = 4483, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -1940,6 +1965,8 @@ OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.h new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.h --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.h 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.h 2023-03-08 18:22:35.000000000 +0100 @@ -200,6 +200,7 @@ SpvExecutionModeNumSIMDWorkitemsINTEL = 5896, SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903, SpvExecutionModeStreamingInterfaceINTEL = 6154, + SpvExecutionModeRegisterMapInterfaceINTEL = 6160, SpvExecutionModeNamedBarrierCountINTEL = 6417, SpvExecutionModeMax = 0x7fffffff, } SpvExecutionMode; @@ -512,6 +513,8 @@ SpvDecorationMaxByteOffsetId = 47, SpvDecorationNoSignedWrap = 4469, SpvDecorationNoUnsignedWrap = 4470, + SpvDecorationWeightTextureQCOM = 4487, + SpvDecorationBlockMatchTextureQCOM = 4488, SpvDecorationExplicitInterpAMD = 4999, SpvDecorationOverrideCoverageNV = 5248, SpvDecorationPassthroughNV = 5250, @@ -580,6 +583,17 @@ SpvDecorationSingleElementVectorINTEL = 6085, SpvDecorationVectorComputeCallableFunctionINTEL = 6087, SpvDecorationMediaBlockIOINTEL = 6140, + SpvDecorationLatencyControlLabelINTEL = 6172, + SpvDecorationLatencyControlConstraintINTEL = 6173, + SpvDecorationConduitKernelArgumentINTEL = 6175, + SpvDecorationRegisterMapKernelArgumentINTEL = 6176, + SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177, + SpvDecorationMMHostInterfaceDataWidthINTEL = 6178, + SpvDecorationMMHostInterfaceLatencyINTEL = 6179, + SpvDecorationMMHostInterfaceReadWriteModeINTEL = 6180, + SpvDecorationMMHostInterfaceMaxBurstINTEL = 6181, + SpvDecorationMMHostInterfaceWaitRequestINTEL = 6182, + SpvDecorationStableKernelArgumentINTEL = 6183, SpvDecorationMax = 0x7fffffff, } SpvDecoration; @@ -1009,6 +1023,9 @@ SpvCapabilityRayQueryKHR = 4472, SpvCapabilityRayTraversalPrimitiveCullingKHR = 4478, SpvCapabilityRayTracingKHR = 4479, + SpvCapabilityTextureSampleWeightedQCOM = 4484, + SpvCapabilityTextureBoxFilterQCOM = 4485, + SpvCapabilityTextureBlockMatchQCOM = 4486, SpvCapabilityFloat16ImageAMD = 5008, SpvCapabilityImageGatherBiasLodAMD = 5009, SpvCapabilityFragmentMaskAMD = 5010, @@ -1136,7 +1153,11 @@ SpvCapabilityOptNoneINTEL = 6094, SpvCapabilityAtomicFloat16AddEXT = 6095, SpvCapabilityDebugInfoModuleINTEL = 6114, + SpvCapabilityBFloat16ConversionINTEL = 6115, SpvCapabilitySplitBarrierINTEL = 6141, + SpvCapabilityFPGAKernelAttributesv2INTEL = 6161, + SpvCapabilityFPGALatencyControlINTEL = 6171, + SpvCapabilityFPGAArgumentInterfacesINTEL = 6174, SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityMax = 0x7fffffff, } SpvCapability; @@ -1621,6 +1642,10 @@ SpvOpRayQueryConfirmIntersectionKHR = 4476, SpvOpRayQueryProceedKHR = 4477, SpvOpRayQueryGetIntersectionTypeKHR = 4479, + SpvOpImageSampleWeightedQCOM = 4480, + SpvOpImageBoxFilterQCOM = 4481, + SpvOpImageBlockMatchSSDQCOM = 4482, + SpvOpImageBlockMatchSADQCOM = 4483, SpvOpGroupIAddNonUniformAMD = 5000, SpvOpGroupFAddNonUniformAMD = 5001, SpvOpGroupFMinNonUniformAMD = 5002, @@ -1938,6 +1963,8 @@ SpvOpTypeStructContinuedINTEL = 6090, SpvOpConstantCompositeContinuedINTEL = 6091, SpvOpSpecConstantCompositeContinuedINTEL = 6092, + SpvOpConvertFToBF16INTEL = 6116, + SpvOpConvertBF16ToFINTEL = 6117, SpvOpControlBarrierArriveINTEL = 6142, SpvOpControlBarrierWaitINTEL = 6143, SpvOpGroupIMulKHR = 6401, @@ -2329,6 +2356,10 @@ case SpvOpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break; case SpvOpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break; case SpvOpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -2641,6 +2672,8 @@ case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.hpp new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.hpp --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.hpp 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.hpp 2023-03-08 18:22:35.000000000 +0100 @@ -196,6 +196,7 @@ ExecutionModeNumSIMDWorkitemsINTEL = 5896, ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903, ExecutionModeStreamingInterfaceINTEL = 6154, + ExecutionModeRegisterMapInterfaceINTEL = 6160, ExecutionModeNamedBarrierCountINTEL = 6417, ExecutionModeMax = 0x7fffffff, }; @@ -508,6 +509,8 @@ DecorationMaxByteOffsetId = 47, DecorationNoSignedWrap = 4469, DecorationNoUnsignedWrap = 4470, + DecorationWeightTextureQCOM = 4487, + DecorationBlockMatchTextureQCOM = 4488, DecorationExplicitInterpAMD = 4999, DecorationOverrideCoverageNV = 5248, DecorationPassthroughNV = 5250, @@ -576,6 +579,17 @@ DecorationSingleElementVectorINTEL = 6085, DecorationVectorComputeCallableFunctionINTEL = 6087, DecorationMediaBlockIOINTEL = 6140, + DecorationLatencyControlLabelINTEL = 6172, + DecorationLatencyControlConstraintINTEL = 6173, + DecorationConduitKernelArgumentINTEL = 6175, + DecorationRegisterMapKernelArgumentINTEL = 6176, + DecorationMMHostInterfaceAddressWidthINTEL = 6177, + DecorationMMHostInterfaceDataWidthINTEL = 6178, + DecorationMMHostInterfaceLatencyINTEL = 6179, + DecorationMMHostInterfaceReadWriteModeINTEL = 6180, + DecorationMMHostInterfaceMaxBurstINTEL = 6181, + DecorationMMHostInterfaceWaitRequestINTEL = 6182, + DecorationStableKernelArgumentINTEL = 6183, DecorationMax = 0x7fffffff, }; @@ -1005,6 +1019,9 @@ CapabilityRayQueryKHR = 4472, CapabilityRayTraversalPrimitiveCullingKHR = 4478, CapabilityRayTracingKHR = 4479, + CapabilityTextureSampleWeightedQCOM = 4484, + CapabilityTextureBoxFilterQCOM = 4485, + CapabilityTextureBlockMatchQCOM = 4486, CapabilityFloat16ImageAMD = 5008, CapabilityImageGatherBiasLodAMD = 5009, CapabilityFragmentMaskAMD = 5010, @@ -1132,7 +1149,11 @@ CapabilityOptNoneINTEL = 6094, CapabilityAtomicFloat16AddEXT = 6095, CapabilityDebugInfoModuleINTEL = 6114, + CapabilityBFloat16ConversionINTEL = 6115, CapabilitySplitBarrierINTEL = 6141, + CapabilityFPGAKernelAttributesv2INTEL = 6161, + CapabilityFPGALatencyControlINTEL = 6171, + CapabilityFPGAArgumentInterfacesINTEL = 6174, CapabilityGroupUniformArithmeticKHR = 6400, CapabilityMax = 0x7fffffff, }; @@ -1617,6 +1638,10 @@ OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryProceedKHR = 4477, OpRayQueryGetIntersectionTypeKHR = 4479, + OpImageSampleWeightedQCOM = 4480, + OpImageBoxFilterQCOM = 4481, + OpImageBlockMatchSSDQCOM = 4482, + OpImageBlockMatchSADQCOM = 4483, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -1934,6 +1959,8 @@ OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, @@ -2325,6 +2352,10 @@ case OpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break; case OpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break; case OpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break; + case OpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break; + case OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; + case OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; + case OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; case OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -2637,6 +2668,8 @@ case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.hpp11 new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.hpp11 --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.hpp11 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.hpp11 2023-03-08 18:22:35.000000000 +0100 @@ -196,6 +196,7 @@ NumSIMDWorkitemsINTEL = 5896, SchedulerTargetFmaxMhzINTEL = 5903, StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, Max = 0x7fffffff, }; @@ -508,6 +509,8 @@ MaxByteOffsetId = 47, NoSignedWrap = 4469, NoUnsignedWrap = 4470, + WeightTextureQCOM = 4487, + BlockMatchTextureQCOM = 4488, ExplicitInterpAMD = 4999, OverrideCoverageNV = 5248, PassthroughNV = 5250, @@ -576,6 +579,17 @@ SingleElementVectorINTEL = 6085, VectorComputeCallableFunctionINTEL = 6087, MediaBlockIOINTEL = 6140, + LatencyControlLabelINTEL = 6172, + LatencyControlConstraintINTEL = 6173, + ConduitKernelArgumentINTEL = 6175, + RegisterMapKernelArgumentINTEL = 6176, + MMHostInterfaceAddressWidthINTEL = 6177, + MMHostInterfaceDataWidthINTEL = 6178, + MMHostInterfaceLatencyINTEL = 6179, + MMHostInterfaceReadWriteModeINTEL = 6180, + MMHostInterfaceMaxBurstINTEL = 6181, + MMHostInterfaceWaitRequestINTEL = 6182, + StableKernelArgumentINTEL = 6183, Max = 0x7fffffff, }; @@ -1005,6 +1019,9 @@ RayQueryKHR = 4472, RayTraversalPrimitiveCullingKHR = 4478, RayTracingKHR = 4479, + TextureSampleWeightedQCOM = 4484, + TextureBoxFilterQCOM = 4485, + TextureBlockMatchQCOM = 4486, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, FragmentMaskAMD = 5010, @@ -1132,7 +1149,11 @@ OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, + FPGAKernelAttributesv2INTEL = 6161, + FPGALatencyControlINTEL = 6171, + FPGAArgumentInterfacesINTEL = 6174, GroupUniformArithmeticKHR = 6400, Max = 0x7fffffff, }; @@ -1617,6 +1638,10 @@ OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryProceedKHR = 4477, OpRayQueryGetIntersectionTypeKHR = 4479, + OpImageSampleWeightedQCOM = 4480, + OpImageBoxFilterQCOM = 4481, + OpImageBlockMatchSSDQCOM = 4482, + OpImageBlockMatchSADQCOM = 4483, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -1934,6 +1959,8 @@ OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, @@ -2325,6 +2352,10 @@ case Op::OpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break; case Op::OpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break; case Op::OpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -2637,6 +2668,8 @@ case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.json new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.json --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.json 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.json 2023-03-08 18:22:35.000000000 +0100 @@ -215,6 +215,7 @@ "NumSIMDWorkitemsINTEL": 5896, "SchedulerTargetFmaxMhzINTEL": 5903, "StreamingInterfaceINTEL": 6154, + "RegisterMapInterfaceINTEL": 6160, "NamedBarrierCountINTEL": 6417 } }, @@ -534,6 +535,8 @@ "MaxByteOffsetId": 47, "NoSignedWrap": 4469, "NoUnsignedWrap": 4470, + "WeightTextureQCOM": 4487, + "BlockMatchTextureQCOM": 4488, "ExplicitInterpAMD": 4999, "OverrideCoverageNV": 5248, "PassthroughNV": 5250, @@ -601,7 +604,18 @@ "FunctionFloatingPointModeINTEL": 6080, "SingleElementVectorINTEL": 6085, "VectorComputeCallableFunctionINTEL": 6087, - "MediaBlockIOINTEL": 6140 + "MediaBlockIOINTEL": 6140, + "LatencyControlLabelINTEL": 6172, + "LatencyControlConstraintINTEL": 6173, + "ConduitKernelArgumentINTEL": 6175, + "RegisterMapKernelArgumentINTEL": 6176, + "MMHostInterfaceAddressWidthINTEL": 6177, + "MMHostInterfaceDataWidthINTEL": 6178, + "MMHostInterfaceLatencyINTEL": 6179, + "MMHostInterfaceReadWriteModeINTEL": 6180, + "MMHostInterfaceMaxBurstINTEL": 6181, + "MMHostInterfaceWaitRequestINTEL": 6182, + "StableKernelArgumentINTEL": 6183 } }, { @@ -985,6 +999,9 @@ "RayQueryKHR": 4472, "RayTraversalPrimitiveCullingKHR": 4478, "RayTracingKHR": 4479, + "TextureSampleWeightedQCOM": 4484, + "TextureBoxFilterQCOM": 4485, + "TextureBlockMatchQCOM": 4486, "Float16ImageAMD": 5008, "ImageGatherBiasLodAMD": 5009, "FragmentMaskAMD": 5010, @@ -1112,7 +1129,11 @@ "OptNoneINTEL": 6094, "AtomicFloat16AddEXT": 6095, "DebugInfoModuleINTEL": 6114, + "BFloat16ConversionINTEL": 6115, "SplitBarrierINTEL": 6141, + "FPGAKernelAttributesv2INTEL": 6161, + "FPGALatencyControlINTEL": 6171, + "FPGAArgumentInterfacesINTEL": 6174, "GroupUniformArithmeticKHR": 6400 } }, @@ -1607,6 +1628,10 @@ "OpRayQueryConfirmIntersectionKHR": 4476, "OpRayQueryProceedKHR": 4477, "OpRayQueryGetIntersectionTypeKHR": 4479, + "OpImageSampleWeightedQCOM": 4480, + "OpImageBoxFilterQCOM": 4481, + "OpImageBlockMatchSSDQCOM": 4482, + "OpImageBlockMatchSADQCOM": 4483, "OpGroupIAddNonUniformAMD": 5000, "OpGroupFAddNonUniformAMD": 5001, "OpGroupFMinNonUniformAMD": 5002, @@ -1924,6 +1949,8 @@ "OpTypeStructContinuedINTEL": 6090, "OpConstantCompositeContinuedINTEL": 6091, "OpSpecConstantCompositeContinuedINTEL": 6092, + "OpConvertFToBF16INTEL": 6116, + "OpConvertBF16ToFINTEL": 6117, "OpControlBarrierArriveINTEL": 6142, "OpControlBarrierWaitINTEL": 6143, "OpGroupIMulKHR": 6401, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.lua new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.lua --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.lua 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.lua 2023-03-08 18:22:35.000000000 +0100 @@ -183,6 +183,7 @@ NumSIMDWorkitemsINTEL = 5896, SchedulerTargetFmaxMhzINTEL = 5903, StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, }, @@ -481,6 +482,8 @@ MaxByteOffsetId = 47, NoSignedWrap = 4469, NoUnsignedWrap = 4470, + WeightTextureQCOM = 4487, + BlockMatchTextureQCOM = 4488, ExplicitInterpAMD = 4999, OverrideCoverageNV = 5248, PassthroughNV = 5250, @@ -549,6 +552,17 @@ SingleElementVectorINTEL = 6085, VectorComputeCallableFunctionINTEL = 6087, MediaBlockIOINTEL = 6140, + LatencyControlLabelINTEL = 6172, + LatencyControlConstraintINTEL = 6173, + ConduitKernelArgumentINTEL = 6175, + RegisterMapKernelArgumentINTEL = 6176, + MMHostInterfaceAddressWidthINTEL = 6177, + MMHostInterfaceDataWidthINTEL = 6178, + MMHostInterfaceLatencyINTEL = 6179, + MMHostInterfaceReadWriteModeINTEL = 6180, + MMHostInterfaceMaxBurstINTEL = 6181, + MMHostInterfaceWaitRequestINTEL = 6182, + StableKernelArgumentINTEL = 6183, }, BuiltIn = { @@ -967,6 +981,9 @@ RayQueryKHR = 4472, RayTraversalPrimitiveCullingKHR = 4478, RayTracingKHR = 4479, + TextureSampleWeightedQCOM = 4484, + TextureBoxFilterQCOM = 4485, + TextureBlockMatchQCOM = 4486, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, FragmentMaskAMD = 5010, @@ -1094,7 +1111,11 @@ OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, + FPGAKernelAttributesv2INTEL = 6161, + FPGALatencyControlINTEL = 6171, + FPGAArgumentInterfacesINTEL = 6174, GroupUniformArithmeticKHR = 6400, }, @@ -1568,6 +1589,10 @@ OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryProceedKHR = 4477, OpRayQueryGetIntersectionTypeKHR = 4479, + OpImageSampleWeightedQCOM = 4480, + OpImageBoxFilterQCOM = 4481, + OpImageBlockMatchSSDQCOM = 4482, + OpImageBlockMatchSADQCOM = 4483, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -1885,6 +1910,8 @@ OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.py new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.py --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spirv.py 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spirv.py 2023-03-08 18:22:35.000000000 +0100 @@ -183,6 +183,7 @@ 'NumSIMDWorkitemsINTEL' : 5896, 'SchedulerTargetFmaxMhzINTEL' : 5903, 'StreamingInterfaceINTEL' : 6154, + 'RegisterMapInterfaceINTEL' : 6160, 'NamedBarrierCountINTEL' : 6417, }, @@ -481,6 +482,8 @@ 'MaxByteOffsetId' : 47, 'NoSignedWrap' : 4469, 'NoUnsignedWrap' : 4470, + 'WeightTextureQCOM' : 4487, + 'BlockMatchTextureQCOM' : 4488, 'ExplicitInterpAMD' : 4999, 'OverrideCoverageNV' : 5248, 'PassthroughNV' : 5250, @@ -549,6 +552,17 @@ 'SingleElementVectorINTEL' : 6085, 'VectorComputeCallableFunctionINTEL' : 6087, 'MediaBlockIOINTEL' : 6140, + 'LatencyControlLabelINTEL' : 6172, + 'LatencyControlConstraintINTEL' : 6173, + 'ConduitKernelArgumentINTEL' : 6175, + 'RegisterMapKernelArgumentINTEL' : 6176, + 'MMHostInterfaceAddressWidthINTEL' : 6177, + 'MMHostInterfaceDataWidthINTEL' : 6178, + 'MMHostInterfaceLatencyINTEL' : 6179, + 'MMHostInterfaceReadWriteModeINTEL' : 6180, + 'MMHostInterfaceMaxBurstINTEL' : 6181, + 'MMHostInterfaceWaitRequestINTEL' : 6182, + 'StableKernelArgumentINTEL' : 6183, }, 'BuiltIn' : { @@ -967,6 +981,9 @@ 'RayQueryKHR' : 4472, 'RayTraversalPrimitiveCullingKHR' : 4478, 'RayTracingKHR' : 4479, + 'TextureSampleWeightedQCOM' : 4484, + 'TextureBoxFilterQCOM' : 4485, + 'TextureBlockMatchQCOM' : 4486, 'Float16ImageAMD' : 5008, 'ImageGatherBiasLodAMD' : 5009, 'FragmentMaskAMD' : 5010, @@ -1094,7 +1111,11 @@ 'OptNoneINTEL' : 6094, 'AtomicFloat16AddEXT' : 6095, 'DebugInfoModuleINTEL' : 6114, + 'BFloat16ConversionINTEL' : 6115, 'SplitBarrierINTEL' : 6141, + 'FPGAKernelAttributesv2INTEL' : 6161, + 'FPGALatencyControlINTEL' : 6171, + 'FPGAArgumentInterfacesINTEL' : 6174, 'GroupUniformArithmeticKHR' : 6400, }, @@ -1568,6 +1589,10 @@ 'OpRayQueryConfirmIntersectionKHR' : 4476, 'OpRayQueryProceedKHR' : 4477, 'OpRayQueryGetIntersectionTypeKHR' : 4479, + 'OpImageSampleWeightedQCOM' : 4480, + 'OpImageBoxFilterQCOM' : 4481, + 'OpImageBlockMatchSSDQCOM' : 4482, + 'OpImageBlockMatchSADQCOM' : 4483, 'OpGroupIAddNonUniformAMD' : 5000, 'OpGroupFAddNonUniformAMD' : 5001, 'OpGroupFMinNonUniformAMD' : 5002, @@ -1885,6 +1910,8 @@ 'OpTypeStructContinuedINTEL' : 6090, 'OpConstantCompositeContinuedINTEL' : 6091, 'OpSpecConstantCompositeContinuedINTEL' : 6092, + 'OpConvertFToBF16INTEL' : 6116, + 'OpConvertBF16ToFINTEL' : 6117, 'OpControlBarrierArriveINTEL' : 6142, 'OpControlBarrierWaitINTEL' : 6143, 'OpGroupIMulKHR' : 6401, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spv.d new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spv.d --- old/SPIRV-Headers-sdk-1.3.239.0/include/spirv/unified1/spv.d 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/include/spirv/unified1/spv.d 2023-03-08 18:22:35.000000000 +0100 @@ -195,6 +195,7 @@ NumSIMDWorkitemsINTEL = 5896, SchedulerTargetFmaxMhzINTEL = 5903, StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, } @@ -509,6 +510,8 @@ MaxByteOffsetId = 47, NoSignedWrap = 4469, NoUnsignedWrap = 4470, + WeightTextureQCOM = 4487, + BlockMatchTextureQCOM = 4488, ExplicitInterpAMD = 4999, OverrideCoverageNV = 5248, PassthroughNV = 5250, @@ -577,6 +580,17 @@ SingleElementVectorINTEL = 6085, VectorComputeCallableFunctionINTEL = 6087, MediaBlockIOINTEL = 6140, + LatencyControlLabelINTEL = 6172, + LatencyControlConstraintINTEL = 6173, + ConduitKernelArgumentINTEL = 6175, + RegisterMapKernelArgumentINTEL = 6176, + MMHostInterfaceAddressWidthINTEL = 6177, + MMHostInterfaceDataWidthINTEL = 6178, + MMHostInterfaceLatencyINTEL = 6179, + MMHostInterfaceReadWriteModeINTEL = 6180, + MMHostInterfaceMaxBurstINTEL = 6181, + MMHostInterfaceWaitRequestINTEL = 6182, + StableKernelArgumentINTEL = 6183, } enum BuiltIn : uint @@ -1012,6 +1026,9 @@ RayQueryKHR = 4472, RayTraversalPrimitiveCullingKHR = 4478, RayTracingKHR = 4479, + TextureSampleWeightedQCOM = 4484, + TextureBoxFilterQCOM = 4485, + TextureBlockMatchQCOM = 4486, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, FragmentMaskAMD = 5010, @@ -1139,7 +1156,11 @@ OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, + FPGAKernelAttributesv2INTEL = 6161, + FPGALatencyControlINTEL = 6171, + FPGAArgumentInterfacesINTEL = 6174, GroupUniformArithmeticKHR = 6400, } @@ -1626,6 +1647,10 @@ OpRayQueryConfirmIntersectionKHR = 4476, OpRayQueryProceedKHR = 4477, OpRayQueryGetIntersectionTypeKHR = 4479, + OpImageSampleWeightedQCOM = 4480, + OpImageBoxFilterQCOM = 4481, + OpImageBlockMatchSSDQCOM = 4482, + OpImageBlockMatchSADQCOM = 4483, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -1943,6 +1968,8 @@ OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-sdk-1.3.239.0/tools/buildHeaders/bin/makeExtinstHeaders.py new/SPIRV-Headers-sdk-1.3.243.0/tools/buildHeaders/bin/makeExtinstHeaders.py --- old/SPIRV-Headers-sdk-1.3.239.0/tools/buildHeaders/bin/makeExtinstHeaders.py 2023-01-04 16:17:40.000000000 +0100 +++ new/SPIRV-Headers-sdk-1.3.243.0/tools/buildHeaders/bin/makeExtinstHeaders.py 2023-03-08 18:22:35.000000000 +0100 @@ -26,3 +26,4 @@ mk_extinst('AMD_shader_trinary_minmax', 'extinst.spv-amd-shader-trinary-minmax.grammar.json') mk_extinst('NonSemanticDebugPrintf', 'extinst.nonsemantic.debugprintf.grammar.json') mk_extinst('NonSemanticClspvReflection', 'extinst.nonsemantic.clspvreflection.grammar.json') +mk_extinst('NonSemanticDebugBreak', 'extinst.nonsemantic.debugbreak.grammar.json')
