Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package rshim for openSUSE:Factory checked in at 2023-04-22 22:03:17 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/rshim (Old) and /work/SRC/openSUSE:Factory/.rshim.new.1533 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "rshim" Sat Apr 22 22:03:17 2023 rev:10 rq:1082118 version:2.0.6.19.2 Changes: -------- --- /work/SRC/openSUSE:Factory/rshim/rshim.changes 2022-09-19 16:04:28.406332551 +0200 +++ /work/SRC/openSUSE:Factory/.rshim.new.1533/rshim.changes 2023-04-22 22:03:54.598453859 +0200 @@ -1,0 +2,10 @@ +Thu Mar 16 11:18:48 UTC 2023 - Matthias Brugger <mbrug...@suse.com> + +- update to 2.0.6.19.2 + * fix potential NULL pointer access during USB disconnection + * fix vfio and direct mapping mode with several devices + * avoid use of stale cached pci_dev pointer after device reset + * adjust reset delay + * update to dual-licensese GPL-2.0/BSD-3-Clause + +------------------------------------------------------------------- Old: ---- rshim-2.0.6.13.7.tar New: ---- rshim-2.0.6.19.2.tar ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ rshim.spec ++++++ --- /var/tmp/diff_new_pack.oizVTo/_old 2023-04-22 22:03:55.070456681 +0200 +++ /var/tmp/diff_new_pack.oizVTo/_new 2023-04-22 22:03:55.078456729 +0200 @@ -18,10 +18,10 @@ Name: rshim -Version: 2.0.6.13.7 +Version: 2.0.6.19.2 Release: 0 Summary: User-space driver for Mellanox BlueField SoC -License: GPL-2.0-only +License: GPL-2.0 or BSD-3-Clause Group: System/Management URL: https://github.com/mellanox/rshim-user-space Source0: %{name}-%{version}.tar ++++++ rshim-2.0.6.13.7.tar -> rshim-2.0.6.19.2.tar ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/debian/changelog new/rshim-2.0.6.19.2/debian/changelog --- old/rshim-2.0.6.13.7/debian/changelog 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/debian/changelog 2023-02-16 21:59:38.000000000 +0100 @@ -1,3 +1,46 @@ +rshim (2.0.6-19) UNRELEASED; urgency=low + + * BF3: Support 4B access for PCIe + + -- Liming Sun <limi...@nvidia.com> Sun, 20 Nov 2022 07:42:10 -0400 + +rshim (2.0.6-18) UNRELEASED; urgency=low + + * pcie: fix initialization issue when setting DROP_MODE in rshim.conf + + -- Liming Sun <limi...@nvidia.com> Tue, 25 Oct 2022 11:56:20 -0400 + +rshim (2.0.6-17) UNRELEASED; urgency=low + + * pcie: Avoid using cached pci_dev + * rshim_fuse: display misc file even when rshim is not accessible + + -- Liming Sun <limi...@nvidia.com> Thu, 20 Oct 2022 22:08:20 -0400 + +rshim (2.0.6-16) UNRELEASED; urgency=low + + * pcie: Support mixed vfio and direct mapping mode + + -- Liming Sun <limi...@nvidia.com> Thu, 06 Oct 2022 08:23:10 -0400 + +rshim (2.0.6-15) UNRELEASED; urgency=low + + * Add dependency of libfuse2 for .deb + * rshim-pcie: add a new bad-access code + * Fix a potential NULL pointer access during USB disonnect + * Adjust default boot timeout to 150s + + -- Liming Sun <limi...@nvidia.com> Thu, 29 Sep 2022 10:26:15 -0400 + +rshim (2.0.6-14) UNRELEASED; urgency=low + + * Avoid potential race when stopping the rshim process + * Add configuration option to enable/disable PCIe VFIO/UIO + * Fix warnings for compiling on 32-bit BMC + * Mustang rshim usb supports for 4B and 8B transactions + + -- Liming Sun <limi...@nvidia.com> Tue, 16 Aug 2022 15:40:15 -0400 + rshim (2.0.6-13) UNRELEASED; urgency=low * BF3: Support 32-bit CR-space access via USB diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/debian/control new/rshim-2.0.6.19.2/debian/control --- old/rshim-2.0.6.13.7/debian/control 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/debian/control 2023-02-16 21:59:38.000000000 +0100 @@ -6,7 +6,7 @@ Standards-Version: 4.1.4 Package: rshim -Depends: ${misc:Depends} +Depends: ${misc:Depends}, libfuse2 Architecture: any Homepage: https://github.com/Mellanox/rshim-user-space Description: driver for Mellanox BlueField SoC diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/etc/rshim.conf new/rshim-2.0.6.19.2/etc/rshim.conf --- old/rshim-2.0.6.13.7/etc/rshim.conf 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/etc/rshim.conf 2023-02-16 21:59:38.000000000 +0100 @@ -8,8 +8,8 @@ #DISPLAY_LEVEL 0 #BOOT_TIMEOUT 150 #DROP_MODE 0 -#USB_RESET_DELAY 3 -#PCIE_RESET_DELAY 10 +#USB_RESET_DELAY 1 +#PCIE_RESET_DELAY 5 #PCIE_INTR_POLL_INTERVAL 10 #PCIE_HAS_VFIO 1 #PCIE_HAS_UIO 1 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/rhel/rshim.spec.in new/rshim-2.0.6.19.2/rhel/rshim.spec.in --- old/rshim-2.0.6.13.7/rhel/rshim.spec.in 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/rhel/rshim.spec.in 2023-02-16 21:59:38.000000000 +0100 @@ -4,7 +4,7 @@ Name: rshim Version: @VERSION@ -Release: 13%{?dist} +Release: 19%{?dist} Summary: User-space driver for Mellanox BlueField SoC License: GPLv2 @@ -54,6 +54,31 @@ %{_mandir}/man8/rshim.8.gz %changelog +* Sun Nov 20 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-19 +- BF3: Support 4B access for PCIe + +* Tue Oct 25 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-18 +- pcie: fix initialization issue when setting DROP_MODE in rshim.conf + +* Thu Oct 20 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-17 +- pcie: Avoid using cached pci_dev +- rshim_fuse: display misc file even when rshim is not accessible + +* Thu Oct 06 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-16 +- pcie: Support mixed vfio and direct mapping mode + +* Thu Sep 29 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-15 +- Add dependency of libfuse2 for .deb +- rshim-pcie: add a new bad-access code +- Fix a potential NULL pointer access during USB disconnect +- Adjust default boot timeout to 150s + +* Tue Aug 16 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-14 +- Avoid potential race when stopping the rshim process +- Add configuration option to enable/disable PCIe VFIO/UIO +- Fix warnings for compiling on 32-bit BMC +- Mustang rshim usb supports for 4B and 8B transactions + * Sun Jul 17 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-13 - BF3: Support 32-bit CR-space access via USB - Avoid kernel-modules-extra dependency on ctyunos diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/rshim.spec.in new/rshim-2.0.6.19.2/rshim.spec.in --- old/rshim-2.0.6.13.7/rshim.spec.in 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/rshim.spec.in 2023-02-16 21:59:38.000000000 +0100 @@ -4,7 +4,7 @@ Name: rshim Version: @VERSION@ -Release: 13%{?dist} +Release: 19%{?dist} Summary: User-space driver for Mellanox BlueField SoC License: GPLv2 @@ -95,6 +95,31 @@ %{_mandir}/man8/bfb-install.8.gz %changelog +* Sun Nov 20 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-19 +- BF3: Support 4B access for PCIe + +* Tue Oct 25 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-18 +- pcie: fix initialization issue when setting DROP_MODE in rshim.conf + +* Thu Oct 20 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-17 +- pcie: Avoid using cached pci_dev +- rshim_fuse: display misc file even when rshim is not accessible + +* Thu Oct 06 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-16 +- pcie: Support mixed vfio and direct mapping mode + +* Thu Sep 29 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-15 +- Add dependency of libfuse2 for .deb +- rshim-pcie: add a new bad-access code +- Fix a potential NULL pointer access during USB disconnect +- Adjust default boot timeout to 150s + +* Tue Aug 16 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-14 +- Avoid potential race when stopping the rshim process +- Add configuration option to enable/disable PCIe VFIO/UIO +- Fix warnings for compiling on 32-bit BMC +- Mustang rshim usb supports for 4B and 8B transactions + * Sun Jul 17 2022 Liming Sun <limi...@nvidia.com> - 2.0.6-13 - BF3: Support 32-bit CR-space access via USB - Avoid kernel-modules-extra dependency on ctyunos diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim.c new/rshim-2.0.6.19.2/src/rshim.c --- old/rshim-2.0.6.13.7/src/rshim.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim.c 2023-02-16 21:59:38.000000000 +0100 @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause /* - * Copyright (C) 2019 Mellanox Technologies. All Rights Reserved. + * Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved. * */ @@ -23,7 +23,7 @@ #include "rshim.h" -#define REVISION "13" +#define REVISION "19" /* Maximum number of devices supported (currently it's limited to 64). */ #define RSHIM_MAX_DEV 64 @@ -186,8 +186,10 @@ static int rshim_display_level = 0; static int rshim_boot_timeout = 150; int rshim_drop_mode = -1; -int rshim_usb_reset_delay = 5; -int rshim_pcie_reset_delay = 10; +int rshim_usb_reset_delay = 1; +bool rshim_has_usb_reset_delay = false; +int rshim_pcie_reset_delay = 5; +bool rshim_has_pcie_reset_delay = false; int rshim_pcie_enable_vfio = 1; int rshim_pcie_enable_uio = 1; int rshim_pcie_intr_poll_interval = 10; /* Interrupt polling in milliseconds */ @@ -531,7 +533,7 @@ * is not fully ready yet. Add a delay here to avoid race codition. */ if (!bd->is_booting && bd->has_reprobe) - sleep(rshim_usb_reset_delay); + sleep(bd->reset_delay); } if (!bd->has_rshim) @@ -784,7 +786,7 @@ * Add a small delay for the reset. */ if (!bd->has_reprobe) - sleep(rshim_pcie_reset_delay); + sleep(bd->reset_delay); time(&bd->boot_write_time); pthread_mutex_unlock(&bd->mutex); @@ -2659,25 +2661,49 @@ int rshim_get_opn(rshim_backend_t *bd, char *opn, int len) { - uint32_t value, br_opn = 0; + uint32_t value32 = 0; + uint64_t value64 = 0; int i, rc; if (len) opn[0] = 0; - if (bd->ver_id < RSHIM_BLUEFIELD_2) - return -EOPNOTSUPP; + switch (bd->ver_id) { + case RSHIM_BLUEFIELD_2: + for (i = 0; + i < RSHIM_YU_BOOT_RECORD_OPN_SIZE && len >= 4; + i += 4, len -= 4) { + rc = rshim_mmio_read32(bd, RSHIM_YU_BASE_ADDR + + RSHIM_YU_BOOT_RECORD_OPN + i, &value32); + if (rc) + return rc; + value32 = le32toh(value32); + opn[i] = (value32 >> 24) & 0xff; + opn[i + 1] = (value32 >> 16) & 0xff; + opn[i + 2] = (value32 >> 8) & 0xff; + opn[i + 3] = value32 & 0xff; + } + break; - for (i = 0; i < RSHIM_YU_BOOT_RECORD_OPN_SIZE && len >= 4; i += 4, len -= 4) { - rc = rshim_mmio_read32(bd, RSHIM_YU_BASE_ADDR + - RSHIM_YU_BOOT_RECORD_OPN + i, &br_opn); - if (rc) - return rc; - value = le32toh(br_opn); - opn[i] = (value >> 24) & 0xff; - opn[i + 1] = (value >> 16) & 0xff; - opn[i + 2] = (value >> 8) & 0xff; - opn[i + 3] = value & 0xff; + case RSHIM_BLUEFIELD_3: + for (i = 0; + i < RSHIM_YU_BOOT_RECORD_OPN_SIZE && len >= 4; + i += 4, len -= 4) { + rc = bd->read_rshim(bd, YU_CHANNEL, RSHIM_YU_BF3_BOOT_RECORD_OPN + i, + &value64, RSHIM_REG_SIZE_4B); + if (rc) + return rc; + value32 = value64 & 0xFFFFFFFF; + value32 = le32toh(value32); + opn[i] = (value32 >> 24) & 0xff; + opn[i + 1] = (value32 >> 16) & 0xff; + opn[i + 2] = (value32 >> 8) & 0xff; + opn[i + 3] = value32 & 0xff; + } + break; + + default: + return -EOPNOTSUPP; } return 0; @@ -2685,19 +2711,40 @@ int rshim_set_opn(rshim_backend_t *bd, const char *opn, int len) { - uint32_t value; + uint32_t value32; + uint64_t value64; int i, rc; - if (bd->ver_id < RSHIM_BLUEFIELD_2) - return -EOPNOTSUPP; + switch (bd->ver_id) { + case RSHIM_BLUEFIELD_2: + for (i = 0; + i < RSHIM_YU_BOOT_RECORD_OPN_SIZE && len >= 4; + i += 4, len -= 4) { + value32 = htole32((opn[i] << 24) | (opn[i + 1] << 16) | (opn[i + 2] << 8) | + opn[i + 3]); + rc = rshim_mmio_write32(bd, RSHIM_YU_BASE_ADDR + RSHIM_YU_BOOT_RECORD_OPN + i, + value32); + if (rc) + return rc; + } + break; - for (i = 0; i < RSHIM_YU_BOOT_RECORD_OPN_SIZE && len >= 4; i += 4, len -= 4) { - value = htole32((opn[i] << 24) | (opn[i + 1] << 16) | (opn[i + 2] << 8) | - opn[i + 3]); - rc = rshim_mmio_write32(bd, RSHIM_YU_BASE_ADDR + RSHIM_YU_BOOT_RECORD_OPN + i, - value); - if (rc) - return rc; + case RSHIM_BLUEFIELD_3: + for (i = 0; + i < RSHIM_YU_BOOT_RECORD_OPN_SIZE && len >= 4; + i += 4, len -= 4) { + value32 = htole32((opn[i] << 24) | (opn[i + 1] << 16) | (opn[i + 2] << 8) | + opn[i + 3]); + value64 = value32; + rc = bd->write_rshim(bd, YU_CHANNEL, RSHIM_YU_BF3_BOOT_RECORD_OPN + i, + value64, RSHIM_REG_SIZE_4B); + if (rc) + return rc; + } + break; + + default: + return -EOPNOTSUPP; } return 0; @@ -2730,9 +2777,11 @@ continue; } else if (!strcmp(key, "USB_RESET_DELAY")) { rshim_usb_reset_delay = atoi(value); + rshim_has_usb_reset_delay = true; continue; } else if (!strcmp(key, "PCIE_RESET_DELAY")) { rshim_pcie_reset_delay = atoi(value); + rshim_has_pcie_reset_delay = true; continue; } else if (!strcmp(key, "PCIE_INTR_POLL_INTERVAL")) { rshim_pcie_intr_poll_interval = atoi(value); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim.h new/rshim-2.0.6.19.2/src/rshim.h --- old/rshim-2.0.6.13.7/src/rshim.h 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim.h 2023-02-16 21:59:38.000000000 +0100 @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ /* - * Copyright (C) 2019 Mellanox Technologies. All Rights Reserved. + * Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved. * */ @@ -41,7 +41,9 @@ extern bool rshim_daemon_mode; extern int rshim_drop_mode; extern int rshim_usb_reset_delay; +extern bool rshim_has_usb_reset_delay; extern int rshim_pcie_reset_delay; +extern bool rshim_has_pcie_reset_delay; extern int rshim_pcie_intr_poll_interval; extern int rshim_pcie_enable_vfio; extern int rshim_pcie_enable_uio; @@ -98,7 +100,8 @@ #define BF3_MAX_BOOT_FIFO_SIZE 8192 /* bytes */ -#define RSHIM_BAD_CTRL_REG(v) (((v) == 0xbad00acce55) || ((v) == (uint64_t)-1)) +#define RSHIM_BAD_CTRL_REG(v) \ + (((v) == 0xbad00acce55) || ((v) == (uint64_t)-1) || ((v) == 0xbadacce55)) /* Sub-device types. */ enum { @@ -183,6 +186,7 @@ #define RSHIM_YU_BASE_ADDR 0x2800000 #define RSHIM_YU_BOOT_RECORD_OPN 0xfd8 #define RSHIM_YU_BOOT_RECORD_OPN_SIZE 16 +#define RSHIM_YU_BF3_BOOT_RECORD_OPN 0x9bdc #define YU_RESET_MODE_TRIGGER 0x0011 #define YU_BOOT_DEVID 0x0014 @@ -389,6 +393,9 @@ /* Boot timeout in seconds. */ int boot_timeout; + /* Delay after reset. */ + int reset_delay; + /* Configured MAC address of the peer-side. */ uint8_t peer_mac[6]; @@ -414,11 +421,11 @@ void (*destroy)(rshim_backend_t *bd); /* API to read <size> bytes from RShim. */ - int (*read_rshim)(rshim_backend_t *bd, int chan, int addr, + int (*read_rshim)(rshim_backend_t *bd, uint32_t chan, uint32_t addr, uint64_t *value, int size); /* API to write <size> bytes to RShim. */ - int (*write_rshim)(rshim_backend_t *bd, int chan, int addr, + int (*write_rshim)(rshim_backend_t *bd, uint32_t chan, uint32_t addr, uint64_t value, int size); /* API to enable the device. */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_fuse.c new/rshim-2.0.6.19.2/src/rshim_fuse.c --- old/rshim-2.0.6.13.7/src/rshim_fuse.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_fuse.c 2023-02-16 21:59:38.000000000 +0100 @@ -645,14 +645,8 @@ /* Boot mode. */ rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->boot_control, &value, RSHIM_REG_SIZE_8B); if (rc) { - pthread_mutex_unlock(&bd->mutex); - RSHIM_ERR("couldn't read rshim register\n"); -#ifdef __linux__ - fuse_reply_err(req, -rc); - return; -#elif defined(__FreeBSD__) - return CUSE_ERR_INVALID; -#endif + RSHIM_ERR("couldn't read BOOT_CONTROL register\n"); + value = 0; } p = rm->buffer; @@ -891,7 +885,7 @@ if (!bd->has_reprobe) { /* Attach. */ - sleep(rshim_pcie_reset_delay); + sleep(bd->reset_delay); pthread_mutex_lock(&bd->mutex); bd->is_booting = 0; rshim_notify(bd, RSH_EVENT_ATTACH, 0); @@ -1122,9 +1116,8 @@ */ chan = msg2.addr >> 16; offset = msg2.addr & 0xFFFF; - if (bd->ver_id <= RSHIM_BLUEFIELD_2 || strncmp(bd->dev_name, "usb", 3)) { + if (bd->ver_id <= RSHIM_BLUEFIELD_2) chan &= 0xF; - } if (cmd == RSHIM_IOC_WRITE2) { pthread_mutex_lock(&bd->mutex); @@ -1192,7 +1185,7 @@ if (rc == CUSE_ERR_NONE) { data = msg2.data; rc = bd->read_rshim(bd, - (msg2.addr >> 16) & 0xF, /* channel # */ + msg2.addr >> 16, /* channel # */ msg2.addr & 0xFFFF, /* addr */ &data, msg2.data_size); if (!rc) @@ -1206,7 +1199,7 @@ rc = cuse_copy_in(peer_data, &msg2, sizeof(msg2)); rc = bd->write_rshim(bd, - (msg2.addr >> 16) & 0xF, /* channel # */ + msg2.addr >> 16, /* channel # */ msg2.addr & 0xFFFF, /* addr */ msg2.data, msg2.data_size); if (rc) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_log.c new/rshim-2.0.6.19.2/src/rshim_log.c --- old/rshim-2.0.6.13.7/src/rshim_log.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_log.c 2023-02-16 21:59:38.000000000 +0100 @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause /* - * Copyright (C) 2019 Mellanox Technologies. All Rights Reserved. + * Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved. * */ @@ -11,7 +11,7 @@ /* Log module */ const char * const rshim_log_mod[] = { - "MISC", "BL1", "BL2", "BL2R", "BL31", "UEFI" + "MISC", "BL1", "BL2", "BL2R", "BL31", "UEFI", "PSC" }; /* Log level */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_net.c new/rshim-2.0.6.19.2/src/rshim_net.c --- old/rshim-2.0.6.13.7/src/rshim_net.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_net.c 2023-02-16 21:59:38.000000000 +0100 @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause /* - * Copyright (C) 2019 Mellanox Technologies. All Rights Reserved. + * Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved. * */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_pcie.c new/rshim-2.0.6.19.2/src/rshim_pcie.c --- old/rshim-2.0.6.13.7/src/rshim_pcie.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_pcie.c 2023-02-16 21:59:38.000000000 +0100 @@ -30,6 +30,7 @@ #ifdef __linux__ #include <dirent.h> #include <linux/vfio.h> +#include <pci/header.h> #include <sys/eventfd.h> #include <sys/vfs.h> #include <unistd.h> @@ -44,11 +45,9 @@ #define BLUEFIELD3_DEVICE_ID 0xc2d4 #define BLUEFIELD3_DEVICE_ID2 0xc2d5 -/* The offset in BAR2 of the RShim region. */ -#define PCI_RSHIM_WINDOW_OFFSET 0x0 - /* The size the RShim region. */ #define PCI_RSHIM_WINDOW_SIZE 0x100000 +#define BF3_PCI_RSHIM_WINDOW_SIZE 0x800000 #define VFIO_GET_REGION_ADDR(x) ((uint64_t) x << 40ULL) @@ -145,11 +144,31 @@ *(volatile uint64_t *)addr = value; } +static inline uint32_t +readl(const volatile void *addr) +{ + uint32_t value = *(const volatile uint32_t *)addr; + __sync_synchronize(); + return value; +} + +static inline void +writel(uint32_t value, volatile void *addr) +{ + __sync_synchronize(); + *(volatile uint32_t *)addr = value; +} + typedef struct { /* RShim backend structure. */ rshim_backend_t bd; - struct pci_dev *pci_dev; + /* Device info */ + int domain; + uint16_t device_id; + uint8_t bus; + uint8_t dev; + uint8_t func; /* Address of the RShim registers. */ volatile uint8_t *rshim_regs; @@ -183,6 +202,9 @@ /* Memory map and PCI sysfs path. */ int mmap_mode; const char *pci_path; + + /* BAR size */ + uint32_t bar_size; } rshim_pcie_t; static const int bf3_rshim_pcie_chan_map[] = { @@ -220,6 +242,48 @@ static int rshim_pcie_enable_irq(rshim_pcie_t *dev, bool enable); +static uint16_t rshim_pci_read_word(rshim_pcie_t *dev, int pos) +{ + char path[RSHIM_PATH_MAX]; + uint16_t data = 0xFFFF; + int fd; + + snprintf(path, sizeof(path), "%s/%04x:%02x:%02x.%1u/config", + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); + fd = open(path, O_RDWR | O_SYNC); + if (fd != -1) { + if (pread(fd, &data, sizeof(data), pos) != sizeof(data)) { + data = 0xFFFF; + } + data = le16toh(data); + close(fd); + } else { + RSHIM_WARN("Unable to open %s\n", path); + } + return data; +} + +int rshim_pci_write_word(rshim_pcie_t *dev, int pos, uint16_t data) +{ + char path[RSHIM_PATH_MAX]; + int fd, len = 0; + + snprintf(path, sizeof(path), "%s/%04x:%02x:%02x.%1u/config", + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); + fd = open(path, O_RDWR | O_SYNC); + if (fd != -1) { + data = htole16(data); + len = pwrite(fd, &data, sizeof(data), pos); + close(fd); + } else { + RSHIM_WARN("Unable to open %s\n", path); + } + + return len; +} + /* Release pcie resource. */ static void rshim_pcie_mmap_release(rshim_pcie_t *dev) { @@ -230,7 +294,7 @@ if (ptr) { dev->rshim_regs = NULL; __sync_synchronize(); - munmap((void *)ptr, PCI_RSHIM_WINDOW_SIZE); + munmap((void *)ptr, dev->bar_size); } if (dev->device_fd >= 0) { @@ -251,7 +315,6 @@ static void rshim_pcie_bind(rshim_pcie_t *dev, bool enable) { - struct pci_dev *pci_dev = dev->pci_dev; char cmd[RSHIM_CMD_MAX]; int rc; @@ -267,6 +330,15 @@ if (dev->mmap_mode == RSHIM_PCIE_MMAP_VFIO || dev->mmap_mode == RSHIM_PCIE_MMAP_UIO) { + if (!enable) { + snprintf(cmd, sizeof(cmd), + "echo %04x:%02x:%02x.%1u > %s/unbind 2>/dev/null", + dev->domain, dev->bus, dev->dev, dev->func, + dev->pci_path); + if (system(cmd) == -1) + RSHIM_DBG("Failed to unbind device\n"); + } + snprintf(cmd, sizeof(cmd), "echo '%x %x' > %s/%s 2>/dev/null", TILERA_VENDOR_ID, BLUEFIELD1_DEVICE_ID, dev->pci_path, enable ? "new_id" : "remove_id"); @@ -281,16 +353,34 @@ if (rc == -1) RSHIM_DBG("Failed to write device id %m\n"); + if (enable) { + snprintf(cmd, sizeof(cmd), + "echo %04x:%02x:%02x.%1u > %s/bind 2>/dev/null", + dev->domain, dev->bus, dev->dev, dev->func, + dev->pci_path); + if (system(cmd) == -1) + RSHIM_DBG("Failed to bind device\n"); + } + } else if (dev->mmap_mode == RSHIM_PCIE_MMAP_DIRECT) { + if (enable) { + snprintf(cmd, sizeof(cmd), "echo 1 > %s/%04x:%02x:%02x.%1u/enable", + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); + if (system(cmd) == -1) + RSHIM_DBG("Failed to enable pcie\n"); + } + + /* + * There is no driver in direct map mode. Set a faked driver name here + * to prevent the "new_id" command from reassigning driver automatically + * for this rshim PF. This is to avoid issues when there multiple rshim + * devices exist with mixed mode. + */ snprintf(cmd, sizeof(cmd), - "echo %04x:%02x:%02x.%1u > %s/%s 2>/dev/null", - pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev->func, - dev->pci_path, enable ? "bind" : "unbind"); - if (system(cmd) == -1) - RSHIM_DBG("Failed to bind/unbind device\n"); - } else if (dev->mmap_mode == RSHIM_PCIE_MMAP_DIRECT && enable) { - snprintf(cmd, sizeof(cmd), "echo 1 > %s/%04x:%02x:%02x.%1u/enable", - SYS_BUS_PCI_PATH, pci_dev->domain, pci_dev->bus, - pci_dev->dev, pci_dev->func); + "echo %s > %s/%04x:%02x:%02x.%1u/driver_override 2>/dev/null", + enable ? "rshim" : "", + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); if (system(cmd) == -1) RSHIM_DBG("Failed to enable pcie\n"); } @@ -299,30 +389,23 @@ /* Memory map over sysfs. */ static int rshim_pcie_mmap_direct(rshim_pcie_t *dev) { - struct pci_dev *pci_dev = dev->pci_dev; char path[RSHIM_PATH_MAX]; uint16_t reg; - /* Some sanity check. */ - if (pci_dev->size[0] < PCI_RSHIM_WINDOW_SIZE) { - RSHIM_ERR("BAR[0] size 0x%x too small\n", (int)pci_dev->size[0]); - return -ENOMEM; - } - snprintf(path, sizeof(path), "%s/%04x:%02x:%02x.%1u/resource0", - SYS_BUS_PCI_PATH, pci_dev->domain, pci_dev->bus, - pci_dev->dev, pci_dev->func); + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); dev->device_fd = open(path, O_RDWR | O_SYNC); if (dev->device_fd < 0) { RSHIM_ERR("Failed to open %s\n", path); return -ENODEV; } - dev->rshim_regs = mmap(NULL, PCI_RSHIM_WINDOW_SIZE, + dev->rshim_regs = mmap(NULL, dev->bar_size, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, dev->device_fd, - PCI_RSHIM_WINDOW_OFFSET); + 0); if (dev->rshim_regs == MAP_FAILED) { dev->rshim_regs = NULL; RSHIM_ERR("Failed to map RShim registers\n"); @@ -330,8 +413,9 @@ } /* Set PCI bus mastering */ - reg = pci_read_word(pci_dev, PCI_COMMAND); - pci_write_word(pci_dev, PCI_COMMAND, reg | RSHIM_PCI_COMMAND); + reg = rshim_pci_read_word(dev, PCI_COMMAND); + if (reg != 0xFFFF) + rshim_pci_write_word(dev, PCI_COMMAND, reg | RSHIM_PCI_COMMAND); return 0; } @@ -342,20 +426,20 @@ int32_t intr_fd; } irq_set_buf; -#include <pci/header.h> static int rshim_pcie_enable_irq(rshim_pcie_t *dev, bool enable) { - struct pci_dev *pci_dev = dev->pci_dev; struct vfio_irq_set *irq_set = (struct vfio_irq_set *) &irq_set_buf; int len, ret; uint16_t reg; if (dev->mmap_mode == RSHIM_PCIE_MMAP_UIO) { - reg = pci_read_word(pci_dev, PCI_COMMAND); - if (enable && (reg & PCI_COMMAND_DISABLE_INTx)) - pci_write_word(pci_dev, PCI_COMMAND, reg & ~PCI_COMMAND_DISABLE_INTx); - else if (!enable && !(reg & PCI_COMMAND_DISABLE_INTx)) - pci_write_word(pci_dev, PCI_COMMAND, reg | PCI_COMMAND_DISABLE_INTx); + reg = rshim_pci_read_word(dev, PCI_COMMAND); + if (reg != 0xFFFF) { + if (enable && (reg & PCI_COMMAND_DISABLE_INTx)) + rshim_pci_write_word(dev, PCI_COMMAND, reg & ~PCI_COMMAND_DISABLE_INTx); + else if (!enable && !(reg & PCI_COMMAND_DISABLE_INTx)) + rshim_pci_write_word(dev, PCI_COMMAND, reg | PCI_COMMAND_DISABLE_INTx); + } return 0; } else if (dev->mmap_mode != RSHIM_PCIE_MMAP_VFIO) { return 0; @@ -423,7 +507,6 @@ int rc, group_id, container_fd = -1, group_fd = -1, device_fd = -1; struct vfio_irq_info irq = { .argsz = sizeof(irq) }; char path[RSHIM_PATH_MAX], name[PATH_MAX], *p; - struct pci_dev *pci_dev = dev->pci_dev; struct vfio_group_status group_status = { .argsz = sizeof(group_status) @@ -459,8 +542,8 @@ /* Find the group_id. */ snprintf(path, sizeof(path), "%s/%04x:%02x:%02x.%1u/iommu_group", - SYS_BUS_PCI_PATH, pci_dev->domain, pci_dev->bus, - pci_dev->dev, pci_dev->func); + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); rc = readlink(path, name, sizeof(name)); if (rc < 0 || !name[0] || rc >= sizeof(name)) { RSHIM_ERR("%s: failed to read iommu link\n", path); @@ -501,8 +584,8 @@ ioctl(container_fd, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU); } - snprintf(path, sizeof(path), "%04x:%02x:%02x.%d", pci_dev->domain, - pci_dev->bus, pci_dev->dev, pci_dev->func); + snprintf(path, sizeof(path), "%04x:%02x:%02x.%d", dev->domain, + dev->bus, dev->dev, dev->func); device_fd = ioctl(group_fd, VFIO_GROUP_GET_DEVICE_FD, path); if (device_fd < 0) { RSHIM_ERR("Failed to get vfio device %s\n", path); @@ -596,20 +679,19 @@ static int rshim_pcie_mmap_uio(rshim_pcie_t *dev) { char dirname[RSHIM_PATH_MAX], devname[RSHIM_PATH_MAX], *str = NULL; - struct pci_dev *pci_dev = dev->pci_dev; struct dirent *e; int uio_num, rc; DIR *dir; /* Find the uio number. */ snprintf(dirname, sizeof(dirname), "%s/%04x:%02x:%02x.%1u/uio", - SYS_BUS_PCI_PATH, pci_dev->domain, pci_dev->bus, - pci_dev->dev, pci_dev->func); + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); dir = opendir(dirname); if (!dir) { snprintf(dirname, sizeof(dirname), "%s/%04x:%02x:%02x.%1u", - SYS_BUS_PCI_PATH, pci_dev->domain, pci_dev->bus, - pci_dev->dev, pci_dev->func); + SYS_BUS_PCI_PATH, dev->domain, dev->bus, + dev->dev, dev->func); dir = opendir(dirname); if (!dir) return -ENOENT; @@ -679,16 +761,20 @@ if (dev->intr_cnt > RSHIM_PCIE_NIC_IRQ_RATE) return; - rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, &info.word, RSHIM_REG_SIZE_8B); + pthread_mutex_lock(&bd->mutex); + + rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, + &info.word, RSHIM_REG_SIZE_8B); if (rc || RSHIM_BAD_CTRL_REG(info.word)) { - RSHIM_WARN("Failed to read irq request\n"); - return; + if (!bd->drop_mode) + RSHIM_WARN("Failed to read irq request\n"); + goto intr_done; } /* Only handles NIC reset for now. */ if (info.rst_type != RSHIM_PCIE_RST_TYPE_NIC_RESET && info.rst_type != RSHIM_PCIE_RST_TYPE_DPU_RESET) { - return; + goto intr_done; } RSHIM_INFO("Receive interrupt for %s reset\n", @@ -700,21 +786,24 @@ info.rst_reply = RSHIM_PCIE_RST_REPLY_ACK; dev->nic_reset = true; __sync_synchronize(); - bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, info.word, RSHIM_REG_SIZE_8B); + bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, + info.word, RSHIM_REG_SIZE_8B); sleep(RSHIM_PCIE_NIC_RESET_WAIT); dev->nic_reset = false; } - rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, &info.word, RSHIM_REG_SIZE_8B); + rc = bd->read_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, + &info.word, RSHIM_REG_SIZE_8B); if (rc || RSHIM_BAD_CTRL_REG(info.word)) { RSHIM_WARN("Failed to read irq request\n"); - return; + goto intr_done; } if (info.rst_state == RSHIM_PCIE_RST_STATE_ABORT) { RSHIM_INFO("NIC reset ABORT\n"); info.word &= 0xFFFFFFFFUL; - bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, info.word, RSHIM_REG_SIZE_8B); + bd->write_rshim(bd, RSHIM_CHANNEL, bd->regs->scratchpad6, + info.word, RSHIM_REG_SIZE_8B); } else if (info.rst_type == RSHIM_PCIE_RST_TYPE_DPU_RESET) { /* * Both NIC and ARM reset. @@ -725,28 +814,27 @@ */ drop_mode = bd->drop_mode; bd->drop_mode = 1; - pthread_mutex_lock(&bd->mutex); rshim_fifo_reset(bd); sleep(2); bd->drop_mode = drop_mode; - pthread_mutex_unlock(&bd->mutex); } if (!bd->drop_mode) rshim_pcie_enable_irq(dev, true); + +intr_done: + pthread_mutex_unlock(&bd->mutex); } static void rshim_pcie_intr_poll(rshim_pcie_t *dev) { - struct pci_dev *pci_dev = dev->pci_dev; uint16_t reg; usleep(rshim_pcie_intr_poll_interval * 1000); - reg = pci_read_word(pci_dev, PCI_STATUS); - if (reg & PCI_STATUS_INTx) { + reg = rshim_pci_read_word(dev, PCI_STATUS); + if ((reg != 0xFFFF) && (reg & PCI_STATUS_INTx)) rshim_pcie_intr(dev); - } } static void *rshim_pcie_intr_thread(void *arg) @@ -784,12 +872,11 @@ static int rshim_pcie_mmap(rshim_pcie_t *dev, bool enable) { - struct pci_dev *pci_dev = dev->pci_dev; struct pci_bar_mmap pbm = { - .pbm_sel.pc_func = pci_dev->func, - .pbm_sel.pc_dev = pci_dev->dev, - .pbm_sel.pc_bus = pci_dev->bus, - .pbm_sel.pc_domain = pci_dev->domain_16, + .pbm_sel.pc_func = dev->func, + .pbm_sel.pc_dev = dev->dev, + .pbm_sel.pc_bus = dev->bus, + .pbm_sel.pc_domain = dev->domain, .pbm_reg = 0x10, .pbm_flags = PCIIO_BAR_MMAP_RW, .pbm_memattr = VM_MEMATTR_UNCACHEABLE, @@ -817,8 +904,8 @@ } dev->rshim_regs = (void *)((uintptr_t)pbm.pbm_map_base + - (uintptr_t)pbm.pbm_bar_off + PCI_RSHIM_WINDOW_OFFSET); - if (pbm.pbm_bar_length < PCI_RSHIM_WINDOW_SIZE) { + (uintptr_t)pbm.pbm_bar_off); + if (pbm.pbm_bar_length < dev->bar_size) { dev->rshim_regs = NULL; RSHIM_ERR("BAR length is too small\n"); rc = -ENOMEM; @@ -837,52 +924,75 @@ #error "Platform not supported" #endif /* __linux__ */ +static uint32_t +rshim_pcie_bf3_chan_addr_convert(uint32_t chan, uint32_t addr) +{ + if (chan < 0xF) + addr += bf3_rshim_pcie_chan_map[chan] + BF3_RSH_BASE_ADDR; + else + addr = (chan << 16) + addr; + + return addr; +} + /* RShim read/write routines */ static int __attribute__ ((noinline)) -rshim_pcie_read(rshim_backend_t *bd, int chan, int addr, uint64_t *result, int size) +rshim_pcie_read(rshim_backend_t *bd, uint32_t chan, uint32_t addr, + uint64_t *result, int size) { rshim_pcie_t *dev = container_of(bd, rshim_pcie_t, bd); int rc = 0; - if (!bd->has_rshim || !bd->has_tm || !dev->rshim_regs) - return -ENODEV; - - if (dev->nic_reset && addr != bd->regs->scratchpad6) + if (dev->nic_reset && + (chan != RSHIM_CHANNEL || addr != bd->regs->scratchpad6)) sleep(RSHIM_PCIE_NIC_RESET_WAIT); if (bd->drop_mode) { *result = 0; return 0; - } else if (!dev->rshim_regs) { - return -ENODEV; } + if (!bd->has_rshim || !bd->has_tm || !dev->rshim_regs) + return -ENODEV; + dev->write_count = 0; - if (rshim_is_bluefield3(dev->pci_dev->device_id)) - *result = readq(dev->rshim_regs + bf3_rshim_pcie_chan_map[chan] + addr); + if (rshim_is_bluefield3(dev->device_id)) { + addr = rshim_pcie_bf3_chan_addr_convert(chan, addr); + if (addr < BF3_RSH_BASE_ADDR || + addr >= (BF3_RSH_BASE_ADDR + BF3_PCI_RSHIM_WINDOW_SIZE)) + return -EINVAL; + addr -= BF3_RSH_BASE_ADDR; + } else { + addr = addr | (chan << 16); + } + + if (size == 4) + *result = readl(dev->rshim_regs + addr); + else if (size == 8) + *result = readq(dev->rshim_regs + addr); else - *result = readq(dev->rshim_regs + (addr | (chan << 16))); + rc = -EINVAL; return rc; } static int __attribute__ ((noinline)) -rshim_pcie_write(rshim_backend_t *bd, int chan, int addr, uint64_t value, int size) +rshim_pcie_write(rshim_backend_t *bd, uint32_t chan, uint32_t addr, + uint64_t value, int size) { rshim_pcie_t *dev = container_of(bd, rshim_pcie_t, bd); uint64_t result; int rc = 0; - if (!bd->has_rshim || !bd->has_tm || !dev->rshim_regs) - return -ENODEV; - - if (dev->nic_reset && addr != bd->regs->scratchpad6) + if (dev->nic_reset && + (chan != RSHIM_CHANNEL || addr != bd->regs->scratchpad6)) sleep(RSHIM_PCIE_NIC_RESET_WAIT); if (bd->drop_mode) return 0; - else if (!dev->rshim_regs) + + if (!bd->has_rshim || !bd->has_tm || !dev->rshim_regs) return -ENODEV; /* @@ -891,17 +1001,30 @@ * doing a read from another register within the BAR, * which forces previous writes to drain. */ - if (rshim_is_bluefield1(dev->pci_dev->device_id)) { + if (rshim_is_bluefield1(dev->device_id)) { if (dev->write_count == 15) { __sync_synchronize(); rshim_pcie_read(bd, chan, RSH_SCRATCHPAD1, &result, rc); } dev->write_count++; } - if (rshim_is_bluefield3(dev->pci_dev->device_id)) - writeq(value, dev->rshim_regs + bf3_rshim_pcie_chan_map[chan] + addr); + + if (rshim_is_bluefield3(dev->device_id)) { + addr = rshim_pcie_bf3_chan_addr_convert(chan, addr); + if (addr < BF3_RSH_BASE_ADDR || + addr >= (BF3_RSH_BASE_ADDR + BF3_PCI_RSHIM_WINDOW_SIZE)) + return -EINVAL; + addr -= BF3_RSH_BASE_ADDR; + } else { + addr = addr | (chan << 16); + } + + if (size == 4) + writel(value, dev->rshim_regs + addr); + else if (size == 8) + writeq(value, dev->rshim_regs + addr); else - writeq(value, dev->rshim_regs + (addr | (chan << 16))); + rc = -EINVAL; return rc; } @@ -921,15 +1044,17 @@ int rc = 0; #ifdef __linux__ - if (!dev->pci_dev) + if (!dev->device_id) return -ENODEV; /* * Clear scratchpad1 since it's checked by FW for rshim driver. * This needs to be done before the resources are unmapped. */ - if (!enable) - rshim_pcie_write(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, 0, RSHIM_REG_SIZE_8B); + if (!enable) { + rshim_pcie_write(bd, RSHIM_CHANNEL, bd->regs->scratchpad1, 0, + RSHIM_REG_SIZE_8B); + } /* Unmap existing resource first. */ rshim_pcie_mmap(dev, false); @@ -958,6 +1083,7 @@ rshim_pcie_bind(dev, false); dev->pci_path = NULL; dev->mmap_mode = RSHIM_PCIE_MMAP_DIRECT; + rshim_pcie_bind(dev, true); rc = rshim_pcie_mmap(dev, true); } } @@ -1032,20 +1158,32 @@ case BLUEFIELD3_DEVICE_ID2: bd->regs = &bf3_rshim_regs; bd->ver_id = RSHIM_BLUEFIELD_3; + dev->bar_size = BF3_PCI_RSHIM_WINDOW_SIZE; break; case BLUEFIELD2_DEVICE_ID: bd->regs = &bf1_bf2_rshim_regs; bd->ver_id = RSHIM_BLUEFIELD_2; + dev->bar_size = PCI_RSHIM_WINDOW_SIZE; break; default: bd->regs = &bf1_bf2_rshim_regs; bd->ver_id = RSHIM_BLUEFIELD_1; + dev->bar_size = PCI_RSHIM_WINDOW_SIZE; break; } bd->rev_id = pci_read_byte(pci_dev, PCI_REVISION_ID); + if (rshim_has_pcie_reset_delay || bd->ver_id < RSHIM_BLUEFIELD_3) + bd->reset_delay = rshim_pcie_reset_delay; + else + bd->reset_delay = 1; /* minimum delay for BF3 */ + /* Initialize object */ - dev->pci_dev = pci_dev; + dev->device_id = pci_dev->device_id; + dev->domain = pci_dev->domain; + dev->bus = pci_dev->bus; + dev->dev = pci_dev->dev; + dev->func = pci_dev->func; /* Enable the device and setup memory map. */ if (!bd->drop_mode) { @@ -1207,6 +1345,8 @@ dev_present = true; } + pci_cleanup(pci); + if (!dev_present) return -ENODEV; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_pcie_lf.c new/rshim-2.0.6.19.2/src/rshim_pcie_lf.c --- old/rshim-2.0.6.13.7/src/rshim_pcie_lf.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_pcie_lf.c 2023-02-16 21:59:38.000000000 +0100 @@ -646,7 +646,8 @@ /* RShim read/write routines */ static int __attribute__ ((noinline)) -rshim_pcie_read(struct rshim_backend *bd, int chan, int addr, uint64_t *result, int size) +rshim_pcie_read(struct rshim_backend *bd, uint32_t chan, uint32_t addr, + uint64_t *result, int size) { rshim_pcie_lf_t *dev = container_of(bd, rshim_pcie_lf_t, bd); struct pci_dev *pci_dev = dev->pci_dev; @@ -673,7 +674,8 @@ } static int __attribute__ ((noinline)) -rshim_pcie_write(struct rshim_backend *bd, int chan, int addr, uint64_t value, int size) +rshim_pcie_write(struct rshim_backend *bd, uint32_t chan, uint32_t addr, + uint64_t value, int size) { rshim_pcie_lf_t *dev = container_of(bd, rshim_pcie_lf_t, bd); struct pci_dev *pci_dev = dev->pci_dev; @@ -783,6 +785,11 @@ } bd->rev_id = pci_read_byte(pci_dev, PCI_REVISION_ID); + if (rshim_has_pcie_reset_delay || bd->ver_id < RSHIM_BLUEFIELD_3) + bd->reset_delay = rshim_pcie_reset_delay; + else + bd->reset_delay = 1; /* minimum delay for BF3 */ + /* Initialize object */ dev->pci_dev = pci_dev; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_regs.c new/rshim-2.0.6.19.2/src/rshim_regs.c --- old/rshim-2.0.6.13.7/src/rshim_regs.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_regs.c 2023-02-16 21:59:38.000000000 +0100 @@ -1,3 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause +/* + * Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved. + * + */ + #include "rshim_regs.h" #include "rshim.h" diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_regs.h new/rshim-2.0.6.19.2/src/rshim_regs.h --- old/rshim-2.0.6.13.7/src/rshim_regs.h 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_regs.h 2023-02-16 21:59:38.000000000 +0100 @@ -1,6 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ /* - * Copyright (C) 2019 Mellanox Technologies. All Rights Reserved. + * Copyright (C) 2019-2023 Mellanox Technologies. All Rights Reserved. * */ @@ -166,6 +166,7 @@ #define RSH_FABRIC_DIM 0x0110 // Mustang-specific registers' addresses, masks, shifts +#define BF3_RSH_BASE_ADDR 0x13000000 #define BF3_RSH_BOOT_FIFO_DATA 0x2000 #define BF3_RSH_BOOT_FIFO_COUNT 0x1000 #define BF3_RSH_BOOT_FIFO_COUNT__BOOT_FIFO_COUNT_MASK 0x3ff diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rshim-2.0.6.13.7/src/rshim_usb.c new/rshim-2.0.6.19.2/src/rshim_usb.c --- old/rshim-2.0.6.13.7/src/rshim_usb.c 2022-09-12 18:05:02.000000000 +0200 +++ new/rshim-2.0.6.19.2/src/rshim_usb.c 2023-02-16 21:59:38.000000000 +0100 @@ -84,7 +84,7 @@ uint16_t windex; }; -struct rshim_usb_addr bf3_wvalue_widx_pair_map[] = { +struct rshim_usb_addr bf3_wval_widx_pair_map[] = { [RSHIM_CHANNEL] = { .wvalue = 0x0300, .windex = 0x0000, @@ -135,14 +135,15 @@ }, }; -static struct rshim_usb_addr get_wvalue_windex(int chan, int addr, uint16_t ver_id) +static struct rshim_usb_addr get_wvalue_windex(int chan, int addr, + uint16_t ver_id) { struct rshim_usb_addr rsh_usb_addr; if (ver_id == RSHIM_BLUEFIELD_3) { if (chan <= 0xF) { - rsh_usb_addr.wvalue = bf3_wvalue_widx_pair_map[chan].wvalue + BF_MMIO_BASE; - rsh_usb_addr.windex = bf3_wvalue_widx_pair_map[chan].windex + addr; + rsh_usb_addr.wvalue = bf3_wval_widx_pair_map[chan].wvalue + BF_MMIO_BASE; + rsh_usb_addr.windex = bf3_wval_widx_pair_map[chan].windex + addr; } else { rsh_usb_addr.wvalue = chan; rsh_usb_addr.windex = addr; @@ -157,8 +158,8 @@ /* Rshim read/write routines */ -static int rshim_usb_read_rshim(rshim_backend_t *bd, int chan, int addr, - uint64_t *result, int size) +static int rshim_usb_read_rshim(rshim_backend_t *bd, uint32_t chan, + uint32_t addr, uint64_t *result, int size) { rshim_usb_t *dev = container_of(bd, rshim_usb_t, bd); struct rshim_usb_addr rsh_usb_addr; @@ -175,6 +176,7 @@ rsh_usb_addr = get_wvalue_windex(chan, addr, bd->ver_id); /* Do a blocking control read and endian conversion. */ + dev->ctrl_data = 0; rc = libusb_control_transfer(dev->handle, LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | @@ -200,8 +202,8 @@ return rc >= 0 ? (rc > size ? -EINVAL : -ENXIO) : rc; } -static int rshim_usb_write_rshim(rshim_backend_t *bd, int chan, int addr, - uint64_t value, int size) +static int rshim_usb_write_rshim(rshim_backend_t *bd, uint32_t chan, + uint32_t addr, uint64_t value, int size) { rshim_usb_t *dev = container_of(bd, rshim_usb_t, bd); struct rshim_usb_addr rsh_usb_addr; @@ -662,12 +664,18 @@ { rshim_usb_t *dev = container_of(bd, rshim_usb_t, bd); + if (!dev->handle) + return; + switch (devtype) { case RSH_DEV_TYPE_TMFIFO: - if (is_write) - libusb_cancel_transfer(dev->write_urb); - else - libusb_cancel_transfer(dev->read_or_intr_urb); + if (is_write) { + if (dev->write_urb) + libusb_cancel_transfer(dev->write_urb); + } else { + if (dev->read_or_intr_urb) + libusb_cancel_transfer(dev->read_or_intr_urb); + } break; default: @@ -799,6 +807,11 @@ } bd->rev_id = desc->bcdDevice; + if (rshim_has_usb_reset_delay || bd->ver_id < RSHIM_BLUEFIELD_3) + bd->reset_delay = rshim_usb_reset_delay; + else + bd->reset_delay = 1; /* minimum delay for BF3 */ + if (!dev->intr_buf) { dev->intr_buf = calloc(1, sizeof(*dev->intr_buf)); if (dev->intr_buf != NULL)
