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Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2023-06-04 16:42:21
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.15902 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Sun Jun 4 16:42:21 2023 rev:27 rq:1090739 version:1.96.2
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2023-05-15
16:54:38.056277022 +0200
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.15902/CoreFreq.changes
2023-06-04 16:42:57.886259076 +0200
@@ -1,0 +2,13 @@
+Sun Jun 4 08:53:05 UTC 2023 - Michael Pujos <pujos.mich...@gmail.com>
+
+- update to 1.96.2
+ * [Driver]
+ - Allows compilation to keep going without CONFIG_ACPI_CPPC_LIB
+ * [Client]
+ - Adding two command line arguments:
+ -Op Show Package C-States
+ -OW Toggle Energy units
+ * [AMD]
+ - Specification of some Configuration MSRs
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.96.1.tar.gz
New:
----
CoreFreq-1.96.2.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.lZCpaC/_old 2023-06-04 16:42:58.378262004 +0200
+++ /var/tmp/diff_new_pack.lZCpaC/_new 2023-06-04 16:42:58.382262027 +0200
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.96.1
+Version: 1.96.2
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.96.1.tar.gz -> CoreFreq-1.96.2.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.1/amd_reg.h
new/CoreFreq-1.96.2/amd_reg.h
--- old/CoreFreq-1.96.1/amd_reg.h 2023-05-13 16:07:20.000000000 +0200
+++ new/CoreFreq-1.96.2/amd_reg.h 2023-05-31 03:08:53.000000000 +0200
@@ -111,6 +111,16 @@
#define MSR_AMD_DC_CFG 0xc0011022
#endif
+#define MSR_AMD_TW_CFG 0xc0011023
+
+#ifndef MSR_AMD64_DE_CFG
+ #define MSR_AMD64_DE_CFG 0xc0011029
+#endif
+
+#ifndef MSR_AMD64_BU_CFG2
+ #define MSR_AMD64_BU_CFG2 0xc001102a
+#endif
+
#ifndef MSR_AMD_CU_CFG3
#define MSR_AMD_CU_CFG3 0xc001102b
#endif
@@ -844,30 +854,77 @@
HW_IP_Prefetch : 6-5, /* F17h: 1=Disable Instruction Cache */
ReservedBits2 : 9-6,
DisSpecTlbRld : 10-9, /* F16h: 1=Disable speculative ITLB reloads */
- ReservedBits3 : 26-10,
+ ReservedBits3 : 11-10,
+ DIS_SEQ_PREFETCH: 12-11, /* K8: 1=Disable IC sequential prefetch */
+ ReservedBits4 : 26-12,
WIDEREAD_PWRSAVE: 27-26, /* F16h: 1=Disable wide read power mgmt */
- ReservedBits4 : 39-27,
+ ReservedBits5 : 39-27,
DisLoopPredictor: 40-39, /* F15h-C0: 1=Disable loop predictor */
- ReservedBits5 : 64-40;
+ ReservedBits6 : 64-40;
};
} AMD_IC_CFG;
typedef union
{
- unsigned long long value; /* Scope[?]: MSR 0xc0011022 */
+ unsigned long long value; /* Scope[Core]: MSR 0xc0011022 */
struct
{
unsigned long long
ReservedBits1 : 4-0,
DisSpecTlbRld : 5-4, /* 1=Disable speculative DTLB reloads */
- ReservedBits2 : 13-5,
+ ReservedBits2 : 8-5,
+ Dis_WBTOL2 : 9-8, /* F12h: 1=DIS_CLR_WBTOL2_SMC_HIT */
+ ReservedBits3 : 13-9,
DisHwPf : 14-13,
- ReservedBits3 : 15-14,
+ ReservedBits4 : 15-14,
DisPfHwForSw : 16-15,
L1_HW_Prefetch : 17-16, /* F17h (BIOS) , Disable=1 */
- ReservedBits4 : 64-17;
+ ReservedBits5 : 64-17;
+ };
+} AMD_DC_CFG; /* Family: 12h(BKDG) ... 17h(BIOS) */
+
+typedef union
+{
+ unsigned long long value; /* Scope[Core]: MSR 0xc0011023 */
+ struct
+ {
+ unsigned long long
+ ReservedBits1 : 49-0,
+ CombineCr0Cd : 50-49,
+ ReservedBits5 : 64-50;
+ };
+} AMD_TW_CFG; /* Family: 10h(BKDG) ... 17h */
+
+typedef union
+{
+ unsigned long long value; /* Scope[?]: MSR 0xc0011029 */
+ struct
+ {
+ unsigned long long
+ ReservedBits1 : 1-0,
+ LFENCE_SER : 2-1, /* F10h: LFENCE as serializing instruction */
+ ReservedBits2 : 23-2,
+ CLFLUSH_SER : 24-23, /* F12h: CLFLUSH as serializing instruction */
+ ReservedBits3 : 64-24;
+ };
+} AMD_DE_CFG; /* Family: 12h ... 17h */
+
+typedef union
+{
+ unsigned long long value; /* SharedC: MSR 0xc001102a */
+ struct
+ {
+ unsigned long long
+ ReservedBits1 : 35-0,
+ IcDisSpecTlbWr : 36-35, /* F12h: 1=Dis Speculative writes to ITLB */
+ ReservedBits2 : 50-36,
+ RdMmExtCfgDwDis : 51-50, /* F12h: 1=Dis Read MMIO extended config */
+ ReservedBits3 : 56-51,
+ L2ClkGatingEn : 57-56, /* F12h: 1=Enable L2 clock gating */
+ L2HystCnt : 59-57, /* F12h: Periodic clocks max number */
+ ReservedBits4 : 64-59;
};
-} AMD_DC_CFG; /* Family: 15h(BKDG), 17h(BIOS), Other(TODO) */
+} AMD_BU_CFG2; /* Family: 12h ... 17h */
typedef union
{
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.1/corefreq-cli-rsc-en.h
new/CoreFreq-1.96.2/corefreq-cli-rsc-en.h
--- old/CoreFreq-1.96.1/corefreq-cli-rsc-en.h 2023-05-13 16:07:20.000000000
+0200
+++ new/CoreFreq-1.96.2/corefreq-cli-rsc-en.h 2023-05-31 03:08:53.000000000
+0200
@@ -1906,9 +1906,11 @@
"Usage:\t%s [-Option <argument>] [-Command <argument>]\n"\
"\n Interface options\n" \
"\t-Oa\tAbsolute frequency\n" \
+ "\t-Op\tShow Package C-States\n" \
"\t-Ok\tMemory unit in kilobyte\n" \
"\t-Om\tMemory unit in megabyte\n" \
"\t-Og\tMemory unit in gigabyte\n" \
+ "\t-OW\tToggle Energy units\n" \
"\t-OF\tTemperature in Fahrenheit\n" \
"\t-OJ #\tSMBIOS string index number\n" \
"\t-OE #\tColor theme index number\n" \
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.1/corefreq-cli-rsc-fr.h
new/CoreFreq-1.96.2/corefreq-cli-rsc-fr.h
--- old/CoreFreq-1.96.1/corefreq-cli-rsc-fr.h 2023-05-13 16:07:20.000000000
+0200
+++ new/CoreFreq-1.96.2/corefreq-cli-rsc-fr.h 2023-05-31 03:08:53.000000000
+0200
@@ -1371,9 +1371,11 @@
"Usage:\t%s [-Option <argument>] [-Commande <argument>]\n"\
"\n Options de l'interface\n" \
"\t-Oa\tFréquence absolue\n" \
+ "\t-Op\tAfficher Ãtats-Package\n" \
"\t-Ok\tUnité mémoire en kilo-octet\n"
\
"\t-Om\tUnité mémoire en méga-octet\n"
\
"\t-Og\tUnité mémoire en giga-octet\n"
\
+ "\t-OW\tChanger d'unité d'Ãnergie\n" \
"\t-OF\tTempérature en Fahrenheit\n" \
"\t-OJ #\tNuméro d'index de chaîne SMBIOS\n" \
"\t-OE #\tNuméro d'index du thème de couleurs\n" \
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.1/corefreq-cli.c
new/CoreFreq-1.96.2/corefreq-cli.c
--- old/CoreFreq-1.96.1/corefreq-cli.c 2023-05-13 16:07:20.000000000 +0200
+++ new/CoreFreq-1.96.2/corefreq-cli.c 2023-05-31 03:08:53.000000000 +0200
@@ -21007,6 +21007,9 @@
case 'a':
Draw.Load = 1;
break;
+ case 'p':
+ Draw.Flag.avgOrPC = 1;
+ break;
case 'k':
Draw.Unit.Memory = 10 * 0;
break;
@@ -21016,6 +21019,9 @@
case 'g':
Draw.Unit.Memory = 10 * 2;
break;
+ case 'W':
+ Setting.jouleWatt = !Setting.jouleWatt;
+ break;
case 'F':
Setting.fahrCels = 1;
break;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.1/corefreqk.c
new/CoreFreq-1.96.2/corefreqk.c
--- old/CoreFreq-1.96.1/corefreqk.c 2023-05-13 16:07:20.000000000 +0200
+++ new/CoreFreq-1.96.2/corefreqk.c 2023-05-31 03:08:53.000000000 +0200
@@ -3,6 +3,9 @@
* Copyright (C) 2015-2023 CYRIL COURTIAT
* Licenses: GPL2
*
+ * Vedolizumab [05.25.2023]
+ * First injection
+ *
* CYRIL INGENIERIE[11.30.2022]
* Company closed down
*
@@ -4174,7 +4177,8 @@
void For_All_ACPI_CPPC(signed int(*CPPC_Func)(unsigned int, void*), void *arg)
{
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
+ #if defined(CONFIG_ACPI_CPPC_LIB) \
+ && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
signed int rc = acpi_cpc_valid() == false;
#else
signed int rc = acpi_disabled;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.1/coretypes.h
new/CoreFreq-1.96.2/coretypes.h
--- old/CoreFreq-1.96.1/coretypes.h 2023-05-13 16:07:20.000000000 +0200
+++ new/CoreFreq-1.96.2/coretypes.h 2023-05-31 03:08:53.000000000 +0200
@@ -6,7 +6,7 @@
#define COREFREQ_MAJOR 1
#define COREFREQ_MINOR 96
-#define COREFREQ_REV 1
+#define COREFREQ_REV 2
#if !defined(CORE_COUNT)
#define CORE_COUNT 256
