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Hello community,
here is the log from the commit of package intel-graphics-compiler for
openSUSE:Factory checked in at 2024-03-13 22:18:23
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/intel-graphics-compiler (Old)
and /work/SRC/openSUSE:Factory/.intel-graphics-compiler.new.1770 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "intel-graphics-compiler"
Wed Mar 13 22:18:23 2024 rev:12 rq:1157139 version:1.0.15985.7
Changes:
--------
---
/work/SRC/openSUSE:Factory/intel-graphics-compiler/intel-graphics-compiler.changes
2024-03-11 15:43:18.067123417 +0100
+++
/work/SRC/openSUSE:Factory/.intel-graphics-compiler.new.1770/intel-graphics-compiler.changes
2024-03-13 22:19:34.206464315 +0100
@@ -1,0 +2,9 @@
+Tue Mar 12 07:06:59 UTC 2024 - Patrik Jakobsson <patrik.jakobs...@suse.com>
+
+- Update to version 1.0.15985.7
+ * No changelog was made available.
+- Update vc_intrinsics to v0.16.0
+ * Add support for XeHPCVG platform
+ * Add support for Arrow Lake and Lunar Lake devices
+
+-------------------------------------------------------------------
Old:
----
igc-1.0.15610.11.tar.gz
New:
----
igc-1.0.15985.7.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ intel-graphics-compiler.spec ++++++
--- /var/tmp/diff_new_pack.eMSTux/_old 2024-03-13 22:19:35.690519023 +0100
+++ /var/tmp/diff_new_pack.eMSTux/_new 2024-03-13 22:19:35.690519023 +0100
@@ -19,9 +19,9 @@
%global llvm_commit llvmorg-14.0.5
%global opencl_clang_commit cf95b338d14685e4f3402ab1828bef31d48f1fd6
%global spirv_llvm_translator_commit 493353d7fdc655f9f31abc874dd0adef7dd241c1
-%global vc_intrinsics_commit v0.14.0
+%global vc_intrinsics_commit v0.16.0
Name: intel-graphics-compiler
-Version: 1.0.15610.11
+Version: 1.0.15985.7
Release: 1%{?dist}
Summary: Intel Graphics Compiler for OpenCL
License: MIT
++++++ igc-1.0.15610.11.tar.gz -> igc-1.0.15985.7.tar.gz ++++++
/work/SRC/openSUSE:Factory/intel-graphics-compiler/igc-1.0.15610.11.tar.gz
/work/SRC/openSUSE:Factory/.intel-graphics-compiler.new.1770/igc-1.0.15985.7.tar.gz
differ: char 13, line 1
++++++ vc-intrinsics.zip ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
new/vc-intrinsics-0.16.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
2023-12-15 01:16:29.000000000 +0100
@@ -1,6 +1,6 @@
/*========================== begin_copyright_notice
============================
-Copyright (C) 2019-2021 Intel Corporation
+Copyright (C) 2019-2023 Intel Corporation
SPDX-License-Identifier: MIT
@@ -86,6 +86,8 @@
Prefetch2D,
Store,
Store2D,
+ Load2DTyped,
+ Store2DTyped,
Fence,
LegacyAtomic,
Atomic,
@@ -475,6 +477,8 @@
return LSCCategory::Load;
case GenXIntrinsic::genx_lsc_load2d_stateless:
return LSCCategory::Load2D;
+ case GenXIntrinsic::genx_lsc_load2d_typed_bti:
+ return LSCCategory::Load2DTyped;
case GenXIntrinsic::genx_lsc_prefetch_bti:
case GenXIntrinsic::genx_lsc_prefetch_stateless:
return LSCCategory::Prefetch;
@@ -490,6 +494,8 @@
return LSCCategory::Store;
case GenXIntrinsic::genx_lsc_store2d_stateless:
return LSCCategory::Store2D;
+ case GenXIntrinsic::genx_lsc_store2d_typed_bti:
+ return LSCCategory::Store2DTyped;
case GenXIntrinsic::genx_lsc_fence:
return LSCCategory::Fence;
case GenXIntrinsic::genx_lsc_atomic_bti:
@@ -539,6 +545,17 @@
return isLSCLoad2D(getGenXIntrinsicID(F));
}
+inline bool isLSCLoad2DTyped(unsigned IntrinID) {
+ return getLSCCategory(IntrinID) == LSCCategory::Load2DTyped;
+}
+
+inline bool isLSCLoad2DTyped(const Value *V) {
+ return isLSCLoad2DTyped(getGenXIntrinsicID(V));
+}
+
+inline bool isLSCLoad2DTyped(const Function *F) {
+ return isLSCLoad2DTyped(getGenXIntrinsicID(F));
+}
inline bool isLSCPrefetch(unsigned IntrinID) {
return getLSCCategory(IntrinID) == LSCCategory::Prefetch;
@@ -588,6 +605,17 @@
return isLSCStore2D(getGenXIntrinsicID(F));
}
+inline bool isLSCStore2DTyped(unsigned IntrinID) {
+ return getLSCCategory(IntrinID) == LSCCategory::Store2DTyped;
+}
+
+inline bool isLSCStore2DTyped(const Value *V) {
+ return isLSCStore2DTyped(getGenXIntrinsicID(V));
+}
+
+inline bool isLSCStore2DTyped(const Function *F) {
+ return isLSCStore2DTyped(getGenXIntrinsicID(F));
+}
inline bool isLSCFence(unsigned IntrinID) {
return getLSCCategory(IntrinID) == LSCCategory::Fence;
@@ -642,6 +670,8 @@
case LSCCategory::Load2D:
case LSCCategory::Prefetch2D:
case LSCCategory::Store2D:
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
return true;
case LSCCategory::Load:
case LSCCategory::Prefetch:
@@ -663,6 +693,33 @@
return isLSC2D(getGenXIntrinsicID(F));
}
+inline bool isLSCTyped(unsigned IntrinID) {
+ switch (getLSCCategory(IntrinID)) {
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
+ return true;
+ case LSCCategory::Store2D:
+ case LSCCategory::Load:
+ case LSCCategory::Load2D:
+ case LSCCategory::Prefetch:
+ case LSCCategory::Prefetch2D:
+ case LSCCategory::Store:
+ case LSCCategory::Fence:
+ case LSCCategory::LegacyAtomic:
+ case LSCCategory::Atomic:
+ case LSCCategory::NotLSC:
+ return false;
+ }
+ llvm_unreachable("Unknown LSC category");
+}
+
+inline bool isLSCTyped(const Value *V) {
+ return isLSCTyped(getGenXIntrinsicID(V));
+}
+
+inline bool isLSCTyped(const Function *F) {
+ return isLSCTyped(getGenXIntrinsicID(F));
+}
// Dependency from visa_igc_common_header.
// Converts vector size into LSC-appropriate code.
@@ -710,6 +767,8 @@
case LSCCategory::Prefetch2D:
case LSCCategory::Load2D:
case LSCCategory::Store2D:
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
case LSCCategory::Fence:
case LSCCategory::NotLSC:
llvm_unreachable("no such argument");
@@ -736,6 +795,8 @@
case LSCCategory::Store2D:
return 3;
case LSCCategory::Fence:
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
case LSCCategory::NotLSC:
llvm_unreachable("no such argument");
return Invalid;
@@ -759,6 +820,8 @@
case LSCCategory::Prefetch2D:
case LSCCategory::Load2D:
case LSCCategory::Store2D:
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
case LSCCategory::Fence:
case LSCCategory::NotLSC:
llvm_unreachable("no such argument");
@@ -786,6 +849,8 @@
case LSCCategory::Store2D:
return 4;
case LSCCategory::Fence:
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
case LSCCategory::NotLSC:
llvm_unreachable("no such argument");
return Invalid;
@@ -809,6 +874,8 @@
case LSCCategory::Load2D:
case LSCCategory::Prefetch2D:
case LSCCategory::Store2D:
+ case LSCCategory::Load2DTyped:
+ case LSCCategory::Store2DTyped:
return 0;
case LSCCategory::NotLSC:
llvm_unreachable("no such argument");
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py
new/vc-intrinsics-0.16.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py
2023-12-15 01:16:29.000000000 +0100
@@ -1,6 +1,6 @@
# ========================== begin_copyright_notice
============================
#
-# Copyright (C) 2019-2022 Intel Corporation
+# Copyright (C) 2019-2023 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -1584,7 +1584,8 @@
###
"dpas" : { "result" : "anyvector",
"arguments" : [0,"anyvector","anyvector","int"],
- "attributes" : "NoMem"
+ "attributes" : "NoMem",
+ "platforms" : [ "XeHP+", "~XeLPG", "~XeHPCVG" ],
},
### ``llvm.genx.dpas2.<return type>.<vector type>.<vector type>.<vector
type>`` : dpas instruction (Dot Product Accumulate Systolic)
@@ -1604,7 +1605,8 @@
###
"dpas2" : { "result" : "anyvector",
"arguments" :
["anyvector","anyvector","anyvector","int","int", "int", "int", "int", "int"],
- "attributes" : "NoMem"
+ "attributes" : "NoMem",
+ "platforms" : [ "XeHP+", "~XeLPG", "~XeHPCVG" ],
},
### ``llvm.genx.dpas.nosrc0.<return type>.<vector type>.<vector type>`` : dpas
instruction (Dot Product Accumulate Systolic) with no src0
@@ -1618,7 +1620,8 @@
###
"dpas_nosrc0" : { "result" : "anyvector",
"arguments" : ["anyvector","anyvector","int"],
- "attributes" : "NoMem"
+ "attributes" : "NoMem",
+ "platforms" : [ "XeHP+", "~XeLPG", "~XeHPCVG" ],
},
### ``llvm.genx.dpasw.<return type>.<vector type>.<vector type>`` : dpasw
instruction (Dot Product Accumulate Systolic)
@@ -1633,7 +1636,9 @@
###
"dpasw" : { "result" : "anyvector",
"arguments" : [0,"anyvector","anyvector","int"],
- "attributes" : "NoMem"
+ "attributes" : "NoMem",
+ "platforms" : [
+ "XeHP", "XeHPG", "XeLPGPlus" ],
},
### ``llvm.genx.dpasw.nosrc0.<return type>.<vector type>.<vector type>`` :
dpasw instruction (Dot Product Accumulate Systolic) with no src0
@@ -1647,7 +1652,9 @@
###
"dpasw_nosrc0" : { "result" : "anyvector",
"arguments" : ["anyvector","anyvector","int"],
- "attributes" : "NoMem"
+ "attributes" : "NoMem",
+ "platforms" : [
+ "XeHP", "XeHPG", "XeLPGPlus" ],
},
### ``llvm.genx.*dp4a*.<return type>.<vector type>.<vector type>.<vector
type>`` : dp4a instruction (Dot Product 4 Accumulate)
@@ -1905,6 +1912,7 @@
### - 4 -> .wt (writethrough)
### - 5 -> .st (streaming)
### - 6 -> .ri (read-invalidate)
+### - 7 -> .cc (const-cached)
###
### Only certain combinations of CachingL1 with CachingL3 are valid on
hardware.
###
@@ -1928,6 +1936,32 @@
### | .ri | .ca | read-invalidate (e.g. last-use) on L1 loads / cache in
L3 |
###
+---------+-----+-----------------------------------------------------------------------+
###
+### Xe2 caching combinations
+###
+###
+---------+-----+-----------------------------------------------------------------------+
+### | L1 | L3 | Notes
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS
settings) |
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .uc | .uc | uncached (bypass) both L1 and L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .st | .uc | streaming L1 / bypass L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .uc | .ca | bypass L1 / cache in L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .ca | .uc | cache in L1 / bypass L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .ca | .ca | cache in both L1 and L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .st | .ca | streaming L1 / cache in L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .ca | .cc | cache in L1 / L3 cached as constant
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .uc | .cc | bypass L1 / L3 cached as constant
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .ri | .ri | read-invalidate both L1 and L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+###
### Immediate offset. The compiler may be able to fuse this add into the
message, otherwise
### additional instructions are generated to honor the semantics.
###
@@ -2025,6 +2059,7 @@
### - 4 -> .wt (writethrough)
### - 5 -> .st (streaming)
### - 6 -> .ri (read-invalidate)
+### - 7 -> .cc (const-cached)
###
### Only certain combinations of CachingL1 with CachingL3 are valid on
hardware.
###
@@ -2048,6 +2083,16 @@
### | .ri | .ca | read-invalidate (e.g. last-use) on L1 loads / cache in
L3 |
###
+---------+-----+-----------------------------------------------------------------------+
###
+### Xe2 caching combinations - same as above w/o(".ri.ca") plus next variants:
+###
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .ca | .cc | cache in L1 / L3 cached as constant
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .uc | .cc | bypass L1 / L3 cached as constant
|
+###
+---------+-----+-----------------------------------------------------------------------+
+### | .ri | .ri | read-invalidate both L1 and L3
|
+###
+---------+-----+-----------------------------------------------------------------------+
+###
### Immediate offset. The compiler may be able to fuse this add into the
message, otherwise
### additional instructions are generated to honor the semantics.
### Alternative variant for predicated variant of loads - merge destination
for disabled
@@ -2249,6 +2294,60 @@
"attributes" : "None"
},
+### ``llvm.genx.lsc.*.quad.typed.bti.<return type>.<predicate type>.<address
type>``: LSC typed load/store/prefetch
+###
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+###
+### * arg0: vXi1 predicate (overloaded)
+### * arg1: i8 Caching behavior for L1, [MBC]
+### * arg2: i8 Caching behavior for L3, [MBC]
+### * arg3: i8 Channel mask for quad versions, [MBC]
+### * arg4: i32 Surface index (BTI)
+### * arg5: vxi32 U pixel address (overloaded)
+### * arg6: vxi32 V pixel address
+### * arg7: vxi32 R pixel address
+### * arg8: vxi32 LOD pixel address
+### * arg9: vXi32 or vXf32 old value of the data read (load) or data to write
(store)
+###
+### * Return value: the value read or void
+###
+ "lsc_load_merge_quad_typed_bti": { "result": "anyvector",
+ "arguments": ["anyvector", "char",
"char", "char", "int", "anyvector", 2, 2, 2, 0],
+ "attributes": "ReadMem",
+ "platforms" : "Xe2+", },
+ "lsc_store_quad_typed_bti": { "result": "void",
+ "arguments": ["anyvector", "char", "char",
"char", "int", "anyvector", 1, 1, 1, "anyvector"],
+ "attributes": "WriteMem",
+ "platforms" : "Xe2+", },
+ "lsc_prefetch_quad_typed_bti": { "result": "void",
+ "arguments": ["anyvector", "char",
"char", "char", "int", "anyvector", 1, 1, 1],
+ "attributes": "None",
+ "platforms" : "Xe2+", },
+
+### ``llvm.genx.lsc.*2d.typed.bti.[return type/vector type]`` : LSC typed 2d
block load/store/prefetch
+###
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+### * arg0: i8 Caching behavior for L1
+### * arg1: i8 Caching behavior for L3
+### * arg2: i32 Surface
+### * arg3: i32 BlockHeight
+### * arg4: i32 BlockWidth
+### * arg5: i32 XOff
+### * arg6: i32 YOff
+### * arg7: data to write (store only)
+###
+### * Return value: the value read or void
+###
+ "lsc_load2d_typed_bti":{ "result" : "anyvector",
+ "arguments" : ["char", "char", "int", "int",
"int", "int", "int"],
+ "attributes" : "ReadMem",
+ "platforms" : "Xe2+", },
+ "lsc_store2d_typed_bti":{ "result" : "void",
+ "arguments" : ["char", "char", "int", "int",
"int", "int", "int", "anyvector"],
+ "attributes" : "WriteMem",
+ "platforms" : "Xe2+", },
+ "lsc_prefetch2d_typed_bti":{ "result" : "void",
+ "arguments" : ["char", "char", "int", "int",
"int", "int", "int"],
+ "attributes" : "ReadMem",
+ "platforms" : "Xe2+", },
### ``llvm.genx.lsc.atomic.*.<return type>.<any type>.<any vector>`` :
lsc_atomic instructions
###
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -2606,42 +2705,52 @@
"dword_atomic_add" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_sub" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_min" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_max" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_xchg" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_and" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_or" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_xor" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_imin" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_imax" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic2.*.<return type>.<vector type.<any int>`` : dword
atomic with binary operator (variant with no oldval)
@@ -2671,42 +2780,52 @@
"dword_atomic2_add" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_sub" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_min" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_max" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_xchg" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_and" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_or" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_xor" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_imin" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_imax" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic.*.<return type>.<vector type>.<any int>`` : dword
atomic with fmin/fmax operation
@@ -2729,18 +2848,22 @@
"dword_atomic_fmin" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_fmax" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_fadd" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_fsub" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic2.*.<return type>.<vector type>.<any int>`` :
dword atomic with fmin/fmax operation (variant with no oldval)
@@ -2762,18 +2885,22 @@
"dword_atomic2_fmin" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_fmax" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_fadd" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_fsub" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
@@ -2796,10 +2923,12 @@
"dword_atomic_inc" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic_dec" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic2.*.<return type>.<any vector>`` : dword atomic
with inc/dec operation (variant with no oldval)
@@ -2820,10 +2949,12 @@
"dword_atomic2_inc" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_dec" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic.cmpxchg.<return type>.<vector type>`` : vISA
DWORD_ATOMIC CMPXCHG instruction
@@ -2845,6 +2976,7 @@
"dword_atomic_cmpxchg" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,0,0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic2.cmpxchg.<return type>.<vector type>`` : vISA
DWORD_ATOMIC CMPXCHG instruction (variant with no oldval)
@@ -2865,6 +2997,7 @@
"dword_atomic2_cmpxchg" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic.fcmpwr.<return type>.<vector type>.<any int>`` :
vISA DWORD_ATOMIC FCMPWR instruction
@@ -2886,6 +3019,7 @@
"dword_atomic_fcmpwr" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.dword.atomic2.fcmpwr.<return type>.<vector type>.<any int>`` :
vISA DWORD_ATOMIC FCMPWR instruction (variant with no oldval)
@@ -2906,6 +3040,7 @@
"dword_atomic2_fcmpwr" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.typed.atomic.*.<return type>.<vector type>.<any int>`` :
atomic typed with binary operator
@@ -2937,42 +3072,52 @@
###
"typed_atomic_add" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_sub" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_min" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_max" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_xchg" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_and" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_or" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_xor" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_imin" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_imax" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -2997,18 +3142,22 @@
###
"typed_atomic_fmin" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_fmax" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_fadd" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_fsub" : { "result" : "anyvector",
"arguments" : ["anyvector","int",0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3032,10 +3181,12 @@
###
"typed_atomic_inc" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"typed_atomic_dec" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3059,6 +3210,7 @@
###
"typed_atomic_cmpxchg" : { "result" : "anyvector",
"arguments" :
["anyvector","int",0,0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3082,6 +3234,7 @@
###
"typed_atomic_fcmpwr" : { "result" : "anyvector",
"arguments" :
["anyvector","int",0,0,"anyint",2,2,2],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3132,6 +3285,7 @@
"gather_scaled" : { "result" : "anyvector",
"arguments" :
["anyvector","int","short","int","int","anyint",0],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.gather.scaled2`` : vISA GATHER_SCALED instruction
@@ -3158,6 +3312,7 @@
"gather_scaled2" : { "result" : "anyvector",
"arguments" : ["int","short","int","int","anyint"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.gather.masked.scaled2`` : vISA GATHER_SCALED instruction
@@ -3177,6 +3332,7 @@
"gather_masked_scaled2" : { "result" : "anyvector",
"arguments" :
["int","short","int","int","anyint","anyvector"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
@@ -3208,6 +3364,7 @@
"gather4_scaled" : { "result" : "anyvector",
"arguments" :
["anyvector","int","short","int","int","anyint",0],
"attributes" : "ReadMem" ,
+ "platforms" : "-Xe2",
},
### ``llvm.genx.gather4.scaled2`` : vISA GATHER4_SCALED instruction
@@ -3239,6 +3396,7 @@
"gather4_scaled2" : { "result" : "anyvector",
"arguments" : ["int","short","int","int","anyint"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.gather4.masked.scaled2`` : vISA GATHER4_SCALED instruction
@@ -3257,6 +3415,7 @@
"gather4_masked_scaled2" : { "result" : "anyvector",
"arguments" :
["int","short","int","int","anyint","anyvector"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
@@ -3288,6 +3447,7 @@
"gather4_typed" : { "result" : "anyvector",
"arguments" :
["int","anyvector","int","anyvector",2,2,0],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.media.ld.<return type>`` : vISA MEDIA_LD instruction
@@ -3314,6 +3474,7 @@
"media_ld" : { "result" : "anyvector",
"arguments" : ["int","int","int","int","int","int"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.media.st.<vector type>`` : vISA MEDIA_ST instruction
@@ -3339,6 +3500,7 @@
"media_st" : { "result" : "void",
"arguments" :
["int","int","int","int","int","int","anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.oword.ld*.<return type>`` : oword load instruction
@@ -3358,10 +3520,12 @@
"oword_ld" : { "result" : "anyvector",
"arguments" : ["int","int","int"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
"oword_ld_unaligned" : { "result" : "anyvector",
"arguments" : ["int","int","int"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.oword.st.<vector type>`` : vISA OWORD_ST instruction
@@ -3377,6 +3541,7 @@
"oword_st" : { "result" : "void",
"arguments" : ["int","int","anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.scatter.private.<vector type>.<ptr type>.<any int>.<vector
type>`` : CM internal, no VISA
@@ -3419,6 +3584,7 @@
"scatter_scaled" : { "result" : "void",
"arguments" :
["anyvector","int","short","int","int","anyint","anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.scatter4.scaled.<vector type>.<any int>.<vector type>`` : vISA
SCATTER4_SCALED instruction
@@ -3448,6 +3614,7 @@
"scatter4_scaled" : { "result" : "void",
"arguments" :
["anyvector","int","short","int","int","anyint","anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.scatter4.typed.<vector type>.<vector type>.<vector type>`` :
vISA SCATTER4_TYPED instruction
@@ -3476,6 +3643,7 @@
"scatter4_typed" : { "result" : "void",
"arguments" :
["int","anyvector","int","anyvector",1,1,"anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
### ``llvm.genx.transpose.ld.<return type>`` : vISA TRANSPOSE_LD instruction
@@ -3496,6 +3664,7 @@
###
"transpose_ld" : { "result" : "anyvector",
"arguments" : ["int","int","int","int"],
+ "platforms" : "-Xe2",
"attributes" : "ReadMem"
},
@@ -3526,42 +3695,52 @@
###
"untyped_atomic_add" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_sub" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_min" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_max" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_xchg" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_and" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_or" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_xor" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_imin" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_imax" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3583,10 +3762,12 @@
###
"untyped_atomic_inc" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"untyped_atomic_dec" : { "result" : "anyvector",
"arguments" : ["anyvector","int","int",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3608,6 +3789,7 @@
###
"untyped_atomic_cmpxchg" : { "result" : "anyvector",
"arguments" :
["anyvector","int","int",0,0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3628,10 +3810,12 @@
###
"svm_block_ld" : { "result" : "anyvector",
"arguments" : ["anyint"],
+ "platforms" : "-Xe2",
"attributes" : "ReadMem"
},
"svm_block_ld_unaligned" : { "result" : "anyvector",
"arguments" : ["anyint"],
+ "platforms" : "-Xe2",
"attributes" : "ReadMem"
},
@@ -3647,6 +3831,7 @@
###
"svm_block_st" : { "result" : "void",
"arguments" : ["anyint","anyvector"],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3669,6 +3854,7 @@
###
"svm_gather" : { "result" : "anyvector",
"arguments" : ["anyvector","int","anyint",0],
+ "platforms" : "-Xe2",
"attributes" : "ReadMem"
},
@@ -3699,6 +3885,7 @@
###
"svm_gather4_scaled" : { "result" : "anyvector",
"arguments" :
["anyvector","int","short","long","anyint",0],
+ "platforms" : "-Xe2",
"attributes" : "ReadMem"
},
@@ -3719,6 +3906,7 @@
###
"svm_scatter" : { "result" : "void",
"arguments" : ["anyvector","int","anyint","anyvector"],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3747,6 +3935,7 @@
###
"svm_scatter4_scaled" : { "result" : "void",
"arguments" :
["anyvector","int","short","long","anyint","anyvector"],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3775,42 +3964,52 @@
###
"svm_atomic_add" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_sub" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_min" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_max" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_xchg" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_and" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_or" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_xor" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_imin" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_imax" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3830,10 +4029,12 @@
###
"svm_atomic_inc" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_dec" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3853,6 +4054,7 @@
###
"svm_atomic_cmpxchg" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3873,10 +4075,12 @@
###
"svm_atomic_fmin" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
"svm_atomic_fmax" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -3896,6 +4100,7 @@
###
"svm_atomic_fcmpwr" : { "result" : "anyvector",
"arguments" : ["anyvector","anyint",0,0,0],
+ "platforms" : "-Xe2",
"attributes" : "None"
},
@@ -5234,42 +5439,52 @@
"dword_atomic2_add_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_sub_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_min_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_max_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_xchg_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_and_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_or_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_xor_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_imin_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_imax_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with fmin/fmax
operation with predefined surface
@@ -5293,18 +5508,22 @@
"dword_atomic2_fmin_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_fmax_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_fadd_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_fsub_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with inc/dec
operation with predefined surface
@@ -5325,10 +5544,12 @@
"dword_atomic2_inc_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
"dword_atomic2_dec_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.dword.atomic2.cmpxchg.predef.surface`` : vISA DWORD_ATOMIC
CMPXCHG instruction with predefined surface
@@ -5349,6 +5570,7 @@
"dword_atomic2_cmpxchg_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.dword.atomic2.fcmpwr.predef.surface`` : vISA DWORD_ATOMIC
FCMPWR instruction with predefined surface
@@ -5369,6 +5591,7 @@
"dword_atomic2_fcmpwr_predef_surface" : { "result" : "anyvector",
"arguments" :
["anyvector","anyptr","anyint",0,0],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.gather.masked.scaled2.predef.surface`` : vISA GATHER_SCALED
instruction with predefined surface
@@ -5387,6 +5610,7 @@
"gather_masked_scaled2_predef_surface" : { "result" : "anyvector",
"arguments" :
["int","short","anyptr","int","anyint","anyvector"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.gather4.masked.scaled2.predef.surface`` : vISA GATHER4_SCALED
instruction with predefined surface
@@ -5405,6 +5629,7 @@
"gather4_masked_scaled2_predef_surface" : { "result" : "anyvector",
"arguments" :
["int","short","anyptr","int","anyint","anyvector"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.scatter.scaled.predef.surface`` : vISA SCATTER_SCALED
instruction with predefined surface
@@ -5430,6 +5655,7 @@
"scatter_scaled_predef_surface" : { "result" : "void",
"arguments" :
["anyvector","int","short","anyptr","int","anyint","anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.scatter4.scaled.predef.surface`` : vISA SCATTER4_SCALED
instruction with predefined surface
@@ -5459,6 +5685,7 @@
"scatter4_scaled_predef_surface" : { "result" : "void",
"arguments" :
["anyvector","int","short","anyptr","int","anyint","anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.oword.ld*.predef.surface`` : oword load instruction with
predefined surface
@@ -5478,11 +5705,13 @@
"oword_ld_predef_surface" : { "result" : "anyvector",
"arguments" : ["int", "anyptr", "int"],
"attributes": "ReadMem",
+ "platforms" : "-Xe2",
},
"oword_ld_unaligned_predef_surface" : { "result" : "anyvector",
"arguments": ["int", "anyptr",
"int"],
"attributes" : "ReadMem",
+ "platforms" : "-Xe2",
},
## ``llvm.genx.oword.st.predef.surface`` : vISA OWORD_ST instruction with
predefined surface
@@ -5498,6 +5727,7 @@
"oword_st_predef_surface" : { "result" : "void",
"arguments" : ["anyptr", "int", "anyvector"],
"attributes" : "None",
+ "platforms" : "-Xe2",
},
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py
new/vc-intrinsics-0.16.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py
2023-12-15 01:16:29.000000000 +0100
@@ -2,7 +2,7 @@
# ========================== begin_copyright_notice
============================
#
-# Copyright (C) 2019-2022 Intel Corporation
+# Copyright (C) 2019-2023 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@@ -87,7 +87,10 @@
"XeHP",
"XeHPG",
"XeLPG",
+ "XeLPGPlus",
"XeHPC",
+ "XeHPCVG",
+ "Xe2",
]
def getAttributeList(Attrs):
@@ -570,7 +573,7 @@
platf_id = platforms.get(platf_expr[1:])
if platf_id is None:
raise NameError("Error in platf in " +
str(Intrinsics[ID_array[i]]))
- curr_line[j] = 0;
+ curr_line[platf_id] = 0;
elif platf_expr == "ALL":
curr_line = [1]*len(platforms)
else:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp
2023-12-15 01:16:29.000000000 +0100
@@ -40,7 +40,9 @@
continue;
#if VC_INTR_LLVM_VERSION_MAJOR >= 13
+#if VC_INTR_LLVM_VERSION_MAJOR < 18
if (PTy->isOpaque())
+#endif // VC_INTR_LLVM_VERSION_MAJOR < 18
continue;
#endif // VC_INTR_LLVM_VERSION_MAJOR >= 13
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
2023-12-15 01:16:29.000000000 +0100
@@ -1,6 +1,6 @@
/*========================== begin_copyright_notice
============================
-Copyright (C) 2019-2021 Intel Corporation
+Copyright (C) 2019-2023 Intel Corporation
SPDX-License-Identifier: MIT
@@ -426,10 +426,14 @@
/// parse ffXX as f(fXX) or f(fX)X. (X is a placeholder for any other type.)
static std::string getMangledTypeStr(Type *Ty) {
std::string Result;
+ if (!Ty)
+ return Result;
if (PointerType *PTyp = dyn_cast<PointerType>(Ty)) {
Result += "p" + llvm::utostr(PTyp->getAddressSpace());
#if VC_INTR_LLVM_VERSION_MAJOR >= 13
+#if VC_INTR_LLVM_VERSION_MAJOR < 18
if (PTyp->isOpaque())
+#endif // VC_INTR_LLVM_VERSION_MAJOR < 18
return Result;
#endif // VC_INTR_LLVM_VERSION_MAJOR >= 13
Result += getMangledTypeStr(VCINTR::Type::getNonOpaquePtrEltTy(PTyp));
@@ -463,7 +467,7 @@
for (auto I : TargetTy->int_params())
Result += "_" + llvm::utostr(I);
#endif // VC_INTR_LLVM_VERSION_MAJOR >= 16
- } else if (Ty) {
+ } else {
Result += EVT::getEVT(Ty).getEVTString();
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
2023-12-15 01:16:29.000000000 +0100
@@ -542,6 +542,11 @@
for (auto &&ArgPair : llvm::zip(F.args(), NewF->args()))
rewriteArgumentUses(InsPt, std::get<0>(ArgPair), std::get<1>(ArgPair));
+#if VC_INTR_LLVM_VERSION_MAJOR >= 17
+ // There might be module level named metadata referencing old function, so
replace those usages with new function.
+ // This can be done safely (will not cause type mismatch) when only opaque
pointers are used (since LLVM 17).
+ F.replaceAllUsesWith(NewF);
+#endif
F.eraseFromParent();
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
2023-12-15 01:16:29.000000000 +0100
@@ -1,6 +1,6 @@
/*========================== begin_copyright_notice
============================
-Copyright (C) 2015-2022 Intel Corporation
+Copyright (C) 2015-2023 Intel Corporation
SPDX-License-Identifier: MIT
@@ -1840,7 +1840,7 @@
for (auto bi = BB->begin(), be = BB->end(); bi != be; ++bi) {
Instruction *Inst = &*bi;
// doing the work
- if (auto CIE = dyn_cast_or_null<CallInst>(Inst)) {
+ if (auto *CIE = dyn_cast<CallInst>(Inst)) {
if (GenXIntrinsic::getGenXIntrinsicID(CIE) ==
GenXIntrinsic::genx_unmask_end) {
auto LoadV = dyn_cast<LoadInst>(CIE->getArgOperand(0));
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
2023-12-15 01:16:29.000000000 +0100
@@ -204,7 +204,8 @@
return T;
} else if (auto *StructTy = dyn_cast<StructType>(T)) {
auto It = SEVRichStructMap.find(StructTy);
- assert(It != SEVRichStructMap.end());
+ if (It == SEVRichStructMap.end())
+ llvm_unreachable("Unexpected SEV StructType");
return It->second;
}
auto NPtrs = getPointerNesting(T);
@@ -613,7 +614,11 @@
NewF.copyAttributesFrom(&F);
NewF.takeName(&F);
NewF.copyMetadata(&F, 0);
+#if VC_INTR_LLVM_VERSION_MAJOR >= 18
+ NewF.updateAfterNameChange();
+#else // VC_INTR_LLVM_VERSION_MAJOR >= 18
NewF.recalculateIntrinsicID();
+#endif // VC_INTR_LLVM_VERSION_MAJOR >= 18
F.getParent()->getFunctionList().insert(F.getIterator(), &NewF);
#if VC_INTR_LLVM_VERSION_MAJOR > 15
NewF.splice(NewF.begin(), &F);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.14.0/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp
new/vc-intrinsics-0.16.0/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp
---
old/vc-intrinsics-0.14.0/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp
2023-10-25 00:27:31.000000000 +0200
+++
new/vc-intrinsics-0.16.0/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp
2023-12-15 01:16:29.000000000 +0100
@@ -1,6 +1,6 @@
/*========================== begin_copyright_notice
============================
-Copyright (C) 2019-2021 Intel Corporation
+Copyright (C) 2019-2023 Intel Corporation
SPDX-License-Identifier: MIT
@@ -27,5 +27,19 @@
true);
EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_simdcf_any, 0),
true);
+ EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 0),
true);
+ EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 1),
true);
+ EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 2),
true);
+ EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_dpasw_nosrc0,
2),
+ false);
+ EXPECT_EQ(
+ GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 10),
+ true);
+ EXPECT_EQ(
+ GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 11),
+ true);
+ EXPECT_EQ(
+ GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 12),
+ false);
}
} // namespace
