Swatantra-66 opened a new pull request, #21427: URL: https://github.com/apache/nuttx/pull/21427
## Summary In `stm32serial_setformat()` (`arch/arm/src/common/stm32/stm32_serial_m33_v3.c`), the baud rate register (`BRR`), `CR2` STOP bits, and the parity/word length bits (`PCE`, `PS`, `M0`, `M1`) in `CR1` were modified while the USART remained enabled (`UE = 1`). Per ST Reference Manuals (e.g. RM0456 for STM32H5, RM0454 for STM32U5, RM0438 for STM32L5, and RM0481 for STM32C5), these registers and configuration bits can only be written while the USART is disabled (`UE = 0`). Consequently, run-time `tcsetattr()` calls attempting to change baud rate, parity, or word length returned success (`0`) while leaving hardware USART registers unchanged. This patch clears `USART_CR1_UE` before updating the line configuration and restores it upon completion inside a critical section, aligning `stm32_serial_m33_v3.c` with the approved implementations in: - STM32N6 (commit `2b1b82c73b`, PR #21380) - STM32WL5 (PR #21336) - STM32WB (PR #21334) - STM32L4 (commit `47180bf5ea`) - STM32H7 / F7 This unified fix resolves the hardware write-protection bug across all 5 modern STM32 Cortex-M33 chip families sharing this driver (`STM32H5`, `STM32U5`, `STM32L5`, `STM32U3`, `STM32C5`). ## Impact * **Impact on user:** Run-time `tcsetattr()` calls to change serial line configuration (baud rate, parity, word length, stop bits) now reliably update the hardware registers instead of being ignored by the MCU. * **Impact on build:** None. * **Impact on hardware:** Covers all STM32 Cortex-M33 platforms utilizing `CONFIG_STM32_HAVE_IP_USART_M33_V3` (`STM32H5`, `STM32U5`, `STM32L5`, `STM32U3`, `STM32C5`). ## Testing * **Style verification:** Verified with `nxstyle` with 0 errors and 0 warnings. * **Build host:** Linux Docker / Windows 11 -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
