hujun260 opened a new pull request, #21435: URL: https://github.com/apache/nuttx/pull/21435
## Summary On ARMv7-A, the CP15 PMU cycle counter (`PMCCNTR`) and its control registers are local to each CPU. The current boot sequence calls `up_perf_init()` on the boot CPU only. Consequently, with SMP enabled, the counters on secondary CPUs do not run, and `perf_gettime()` reports no elapsed time for work performed there. This change initializes the PMU cycle counter on each secondary CPU during CPU bring-up. ## Impact | Configuration | Before | After | |---|---|---| | Boot CPU (CPU 0) | Counter initialized | Counter initialized | | Secondary CPUs (CPUs 1–3) | Counter not initialized; measured CPU time stays at `0 ms` | Counter initialized; measured CPU time advances | | Non-SMP configuration | Existing behavior | Unchanged | This affects performance-based timing on ARMv7-A SMP targets, including thread CPU-time measurements and critical-section monitoring. There are no API or documentation changes. ## Test Case **Environment** - Target: `qemu-armv7a` - CPUs: 4 - Emulator: QEMU TCG - Configuration: SMP, `CONFIG_ARCH_PERF_EVENTS`, and `CONFIG_SCHED_CRITMONITOR` - Measurement: `CLOCK_THREAD_CPUTIME_ID` **Procedure** 1. Start one worker thread per CPU. 2. Pin each thread to its CPU with `pthread_attr_setaffinity_np()`. 3. Run a busy loop for approximately 500 ms per thread. 4. Compare each thread's CPU-time delta. **Results** | CPU | Before this change | After this change | |---|---:|---:| | 0 | Counter runs; time is measurable | Counter runs; time is measurable | | 1 | `0 ms` | Non-zero; advances during the busy loop | | 2 | `0 ms` | Non-zero; advances during the busy loop | | 3 | `0 ms` | Non-zero; advances during the busy loop | The test confirms the regression on secondary CPUs is fixed. Exact elapsed values depend on QEMU scheduling and system load; the expected value for each busy loop is approximately 500 ms. The 32-bit PMU cycle counter wraps after approximately 4.29 seconds at 1 GHz. Measurements spanning a wrap may therefore be offset by approximately 4.29 seconds; this is existing counter-wrap behavior and is not introduced by this change. ## Build Verification Built with `-Werror`, `CONFIG_ARCH_PERF_EVENTS`, and `CONFIG_SCHED_CRITMONITOR`: - `qemu-armv7a:smp` — SMP build - `qemu-armv7a:knsh_smp` — kernel-mode SMP build - `qemu-armv7a:nsh` — non-SMP build All three configurations built successfully. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
