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commit dd90ffbc3cc46bd52a5fd2fa3aba2480a2743a4a Author: Marco Casaroli <[email protected]> AuthorDate: Tue Nov 3 21:45:47 2026 +0100 arch/arm/rp23xx: Start the perf counter with ARCH_PERF_EVENTS. The RP23XX never calls up_perf_init(), so the DWT cycle counter does not run and its rate stays ULONG_MAX. With ARCH_PERF_EVENTS (the default with SCHED_CRITMONITOR) all perf times are then 0. Call up_perf_init() with the system clock (BOARD_SYS_FREQ) in __start(), as the other Cortex-M chips do, and in core1_boot(): the DWT is a register of each core. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Marco Casaroli <[email protected]> --- arch/arm/src/rp23xx/rp23xx_cpustart.c | 7 +++++++ arch/arm/src/rp23xx/rp23xx_start.c | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/src/rp23xx/rp23xx_cpustart.c b/arch/arm/src/rp23xx/rp23xx_cpustart.c index 266976bb409..7f89fc9425e 100644 --- a/arch/arm/src/rp23xx/rp23xx_cpustart.c +++ b/arch/arm/src/rp23xx/rp23xx_cpustart.c @@ -35,6 +35,7 @@ #include <nuttx/arch.h> #include <nuttx/sched_note.h> +#include <arch/board/board.h> #include "nvic.h" #include "sched/sched.h" @@ -158,6 +159,12 @@ static void core1_boot(void) up_irqinitialize(); +#ifdef CONFIG_ARCH_PERF_EVENTS + /* The cycle counter (DWT) is a register of each core */ + + up_perf_init((void *)BOARD_SYS_FREQ); +#endif + /* Enable inter-processor FIFO interrupt */ irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL); diff --git a/arch/arm/src/rp23xx/rp23xx_start.c b/arch/arm/src/rp23xx/rp23xx_start.c index 142317f47a7..f5797778332 100644 --- a/arch/arm/src/rp23xx/rp23xx_start.c +++ b/arch/arm/src/rp23xx/rp23xx_start.c @@ -294,6 +294,10 @@ void __start(void) rp23xx_mpu_share_sram(); #endif +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init((void *)BOARD_SYS_FREQ); +#endif + /* Then start NuttX */ showprogress('\r');
