raiden00pl opened a new pull request, #21447: URL: https://github.com/apache/nuttx/pull/21447
- Revert cffaf366b0b (#21400). It was not a cleanup: it changed the
`board.h` clock contract (register field macros and fixed frequencies) that all
STM32 families use, replacing it with numeric divisors for H7R/S only. That is
an unannounced breaking change for out-of-tree boards that splits H7R/S from
the STM32 ports being unified. Such a change must be done for all STM32
families. It also ran APB2, APB4 and APB5 at twice the `board.h` frequency, and
made nucleo-h7s3l8 ignore its HSE option.
- Remove the PLL1 R output: PLL1 on H7R/S has no R output, and `RCC_PLLCFGR`
bit 7 and `RCC_PLL1DIVR1` bits 30:24 are reserved.
- nucleo-h7s3l8: use HSE without bypass. With bypass, HSE never becomes
ready and `NUCLEO_H7S3L8_USE_HSE` does not boot.
- stm32h7s8-dk: HSE is the X3 24 MHz oscillator, not the ST-LINK MCO
(comment only).
- Document the board clock configuration convention in `stm32_ports.rst`.
## Impact
nucleo-h7s3l8 and stm32h7s8-dk only. `board.h` uses the same clock macros as
all other STM32 ports again. APB2, APB4 and APB5 run at the `board.h`
frequencies. `NUCLEO_H7S3L8_USE_HSE` works.
## Testing
NUCLEO-H7S3L8 with HSI and with HSE: `RCC_APBCFGR` reads `0x4444` (was
`0x0004`). TIM and LPTIM1-5 timer and oneshot devices run at the expected rates
(19/19 checks each). With HSE, 10 s of board time measures 10.0 s on the host.
All defconfigs of both boards build with HSI and HSE.
stm32h7s8-dk not tested.
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