Re: [PR] arch/tricore: support per-task CSA in task stacks [nuttx]

Sat, 07 Nov 2026 04:46:52 -0800 


casaroli commented on code in PR #21512:
URL: https://github.com/apache/nuttx/pull/21512#discussion_r4501770593


##########
arch/tricore/src/common/tricore_fpu.c:
##########
@@ -52,19 +52,5 @@ void tricore_fpuinit(void)
 
 bool up_fpucmp(const void *saveregs1, const void *saveregs2)
 {
-  const uintptr_t *regs1 = (const uintptr_t *)saveregs1 + TC_CONTEXT_REGS;
-  const uintptr_t *regs2 = (const uintptr_t *)saveregs2 + TC_CONTEXT_REGS;
-
-  /* TriCore uses D8-D15 in upper CSA as FPU data registers.
-   * Skip A12-A15 (offsets 8-11) which naturally differ between saves.
-   */
-
-  if (memcmp(&regs1[REG_D8], &regs2[REG_D8],
-             4 * sizeof(uintptr_t)) != 0)
-    {
-      return false;
-    }
-
-  return memcmp(&regs1[REG_D12], &regs2[REG_D12],
-                4 * sizeof(uintptr_t)) == 0;
+  return memcmp(saveregs1, saveregs2, TC_CONTEXT_SIZE) == 0;

Review Comment:
   `up_fpucmp()` now compares the whole upper CSA, including A10-A15, PCXI and 
PSW, which the removed code skipped because they "naturally differ between 
saves". ostest fpu.c saves at three different call sites, so the result depends 
on how the compiler uses A12-A15.
   Fix: compare only D8-D15 of the upper CSA, which is now at offset 0 of the 
save area.



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