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from 46675996e5 [Hexagon] Register basic strategies and schedules for
common operators (#10919)
add 19784c8c83 [TVMScript] Fixing T.buffer with typed positional arguments
other than int32 (#10892)
add fc0473885f [TIR] VNNI and ARM dot product intrinsic for tensorization
(#10925)
No new revisions were added by this update.
Summary of changes:
python/tvm/script/tir/__init__.pyi | 4 +-
python/tvm/script/tir/special_stmt.py | 9 +-
python/tvm/script/tir/ty.py | 3 +
.../_ctypes => tir/tensor_intrin}/__init__.py | 5 +-
python/tvm/tir/tensor_intrin/arm_cpu.py | 142 +++++++++++++++++++++
python/tvm/tir/tensor_intrin/x86.py | 75 +++++++++++
.../unittest/test_meta_schedule_tune_relay.py | 57 +--------
.../python/unittest/test_tir_schedule_tensorize.py | 66 +++++++++-
.../python/unittest/test_tvmscript_syntax_sugar.py | 37 ++++++
9 files changed, 335 insertions(+), 63 deletions(-)
copy python/tvm/{_ffi/_ctypes => tir/tensor_intrin}/__init__.py (87%)
create mode 100644 python/tvm/tir/tensor_intrin/arm_cpu.py
create mode 100644 python/tvm/tir/tensor_intrin/x86.py
