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The following commit(s) were added to refs/heads/master by this push:
new 4b6ea06 Add support for riscv64 (#769)
4b6ea06 is described below
commit 4b6ea065c1d76b4bae73ecbf44c2b23623627f5f
Author: Felix Yan <[email protected]>
AuthorDate: Fri Sep 17 05:34:38 2021 +0800
Add support for riscv64 (#769)
* Fix riscv64 target_arch
This should be defined for riscv64 instead, as `riscv` doesn't match it.
I have no idea for riscv32 though.
* parquet: Use murmur_hash2_64a for riscv64
---
arrow/src/alloc/alignment.rs | 2 +-
parquet/src/util/hash_util.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arrow/src/alloc/alignment.rs b/arrow/src/alloc/alignment.rs
index dbf4602..1bd15c5 100644
--- a/arrow/src/alloc/alignment.rs
+++ b/arrow/src/alloc/alignment.rs
@@ -62,7 +62,7 @@ pub const ALIGNMENT: usize = 1 << 6;
// -
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt#L41
// in general all of them are the same.
/// Cache and allocation multiple alignment size
-#[cfg(target_arch = "riscv")]
+#[cfg(target_arch = "riscv64")]
pub const ALIGNMENT: usize = 1 << 6;
// This size is same across all hardware for this architecture.
diff --git a/parquet/src/util/hash_util.rs b/parquet/src/util/hash_util.rs
index f7849da..1f9c159 100644
--- a/parquet/src/util/hash_util.rs
+++ b/parquet/src/util/hash_util.rs
@@ -33,7 +33,7 @@ fn hash_(data: &[u8], seed: u32) -> u32 {
}
}
- #[cfg(any(target_arch = "aarch64", target_arch = "arm"))]
+ #[cfg(any(target_arch = "aarch64", target_arch = "arm", target_arch =
"riscv64"))]
unsafe {
murmur_hash2_64a(data, seed as u64) as u32
}